| /linux-6.14.4/arch/arm/mach-tegra/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
36 static void tegra_secondary_init(unsigned int cpu) in tegra_secondary_init() argument
38 cpumask_set_cpu(cpu, &tegra_cpu_init_mask); in tegra_secondary_init()
42 static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle) in tegra20_boot_secondary() argument
44 cpu = cpu_logical_map(cpu); in tegra20_boot_secondary()
47 * Force the CPU into reset. The CPU must remain in reset when in tegra20_boot_secondary()
48 * the flow controller state is cleared (which will cause the in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | sm4450.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 interrupt-parent = <&intc>;
[all …]
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| /linux-6.14.4/kernel/ |
| D | cpu_pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
53 * cpu_pm_register_notifier - register a driver with cpu_pm
57 * CPU and CPU cluster low power entry and exit.
74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm
77 * Remove a driver from the CPU PM notifier list.
94 * cpu_pm_enter - CPU low power entry notifier
96 * Notifies listeners that a single CPU is entering a low power state that may
97 * cause some blocks in the same power domain as the cpu to reset.
99 * Must be called on the affected CPU with interrupts disabled. Platform is
101 * CPU before cpu_pm_exit is called. Notified drivers can include VFP
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/apple/ |
| D | t8103.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
[all …]
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| D | t8112.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
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| /linux-6.14.4/arch/arm/mach-versatile/ |
| D | tc2_pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright: (C) 2012-2013 Linaro Limited
17 #include <linux/irqchip/arm-gic.h>
20 #include <asm/proc-fns.h>
25 #include <linux/arm-cci.h>
31 #define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu))) argument
32 #define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu))) argument
46 static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster) in tc2_pm_cpu_powerup() argument
48 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); in tc2_pm_cpu_powerup()
49 if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) in tc2_pm_cpu_powerup()
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/renesas/ |
| D | r8a779f0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
[all …]
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| /linux-6.14.4/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca15_a7.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/amlogic/ |
| D | amlogic-t7.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
[all …]
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| D | meson-sm1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <2>;
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/mediatek/ |
| D | mt6795.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
[all …]
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| D | mt8365.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/power/mediatek,mt8365-power.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <1>;
[all …]
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| D | mt8192.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
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| D | mt8173.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
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| D | mt8188.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
15 #include <dt-bindings/power/mediatek,mt8188-power.h>
[all …]
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| /linux-6.14.4/arch/arm/mach-omap2/ |
| D | omap-mpuss-lowpower.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP MPUSS low power code
8 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
9 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
11 * CPU0, CPU1 and MPUSS each have there own power domain and
12 * hence multiple low power combinations of MPUSS are possible.
17 * to the Cortex-A9 processor must be asserted by the external
18 * power controller.
21 * below modes are supported from power gain vs latency point of view.
24 * ----------------------------------------------
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <[email protected]>
11 - Jonathan Hunter <[email protected]>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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| /linux-6.14.4/arch/arm/boot/dts/renesas/ |
| D | r8a7779.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
[all …]
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| /linux-6.14.4/drivers/powercap/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Generic power capping sysfs interface configuration
9 The power capping sysfs interface allows kernel subsystems to expose power
12 power zones representing parts of the system that can be subject to power
29 This enables support for the Intel Running Average Power Limit (RAPL)
30 technology via MSR interface, which allows power limits to be enforced
35 controller, CPU core (Power Plane 0), graphics uncore (Power Plane
44 This enables support for the Intel Running Average Power Limit (RAPL)
45 technology via TPMI interface, which allows power limits to be enforced
50 controller, platform, etc.
[all …]
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| /linux-6.14.4/arch/arm/boot/dts/actions/ |
| D | owl-s500.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
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| /linux-6.14.4/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "X1E80100 Camera Clock Controller"
27 Support for the camera clock controller on X1E80100 devices.
31 tristate "X1E80100 Display Clock Controller"
41 tristate "X1E80100 Global Clock Controller"
45 Support for the global clock controller on Qualcomm Technologies, Inc
51 tristate "X1E80100 Graphics Clock Controller"
55 Support for the graphics clock controller on X1E80100 devices.
56 Say Y if you want to support graphics controller devices and
60 tristate "X1E80100 TCSR Clock Controller"
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/hisilicon/ |
| D | hi6220.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
[all …]
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