xref: /XiangShan/src/main/scala/device/TLTimer.scala (revision 1b46b9591920008655d659ac88cd0250db769664) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chisel3.util._
21import freechips.rocketchip.tilelink._
22import chipsalliance.rocketchip.config._
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.regmapper.RegField
25import utils.{HasTLDump, XSDebug}
26
27class TLTimer(address: Seq[AddressSet], sim: Boolean, numCores: Int)(implicit p: Parameters) extends LazyModule {
28
29  val device = new SimpleDevice("clint", Seq("XiangShan", "clint"))
30  val node = TLRegisterNode(address, device, beatBytes = 8)
31
32  lazy val module = new LazyModuleImp(this) with HasTLDump {
33    val io = IO(new Bundle() {
34      val mtip = Output(Vec(numCores, Bool()))
35      val msip = Output(Vec(numCores, Bool()))
36    })
37
38    val mtime = RegInit(0.U(64.W))  // unit: us
39    val mtimecmp = Seq.fill(numCores)(RegInit(0.U(64.W)))
40    val msip = Seq.fill(numCores)(RegInit(0.U(32.W)))
41
42    val clk = (if (!sim) 1000000 /* 40MHz / 1000000 */ else 100)
43    val freq = RegInit(clk.U(64.W))
44    val inc = RegInit(1.U(64.W))
45
46    val cnt = RegInit(0.U(64.W))
47    val nextCnt = cnt + 1.U
48    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
49    val tick = (nextCnt === freq)
50    when (tick) { mtime := mtime + inc }
51
52    var clintMapping = Seq(
53      0x8000 -> RegField.bytes(freq),
54      0x8008 -> RegField.bytes(inc),
55      0xbff8 -> RegField.bytes(mtime))
56
57    for (i <- 0 until numCores) {
58      clintMapping = clintMapping ++ Seq(
59        0x0000 + i*4 -> RegField.bytes(msip(i)),
60        0x4000 + i*8 -> RegField.bytes(mtimecmp(i))
61      )
62    }
63
64    node.regmap( mapping = clintMapping:_* )
65
66    val in = node.in.head._1
67    when(in.a.valid){
68      XSDebug("[A] channel valid ready=%d ", in.a.ready)
69      in.a.bits.dump
70    }
71
72    for (i <- 0 until numCores) {
73      io.mtip(i) := RegNext(mtime >= mtimecmp(i))
74      io.msip(i) := RegNext(msip(i) =/= 0.U)
75    }
76  }
77}
78