1package top 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import system._ 8import chipsalliance.rocketchip.config._ 9import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 10import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 11import xiangshan.backend.dispatch.DispatchParameters 12import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 13import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 14 15class DefaultConfig(n: Int) extends Config((site, here, up) => { 16 case XLen => 64 17 case DebugOptionsKey => DebugOptions() 18 case SoCParamsKey => SoCParameters( 19 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 20 ) 21}) 22 23// TODO: disable L2 and L3 24class MinimalConfig(n: Int = 1) extends Config( 25 new DefaultConfig(n).alter((site, here, up) => { 26 case SoCParamsKey => up(SoCParamsKey).copy( 27 cores = up(SoCParamsKey).cores.map(_.copy( 28 IssQueSize = 8, 29 NRPhyRegs = 80, 30 LoadQueueSize = 16, 31 StoreQueueSize = 16, 32 RoqSize = 32, 33 BrqSize = 8, 34 FtqSize = 16, 35 IBufSize = 16, 36 dpParams = DispatchParameters( 37 IntDqSize = 8, 38 FpDqSize = 8, 39 LsDqSize = 8, 40 IntDqDeqWidth = 4, 41 FpDqDeqWidth = 4, 42 LsDqDeqWidth = 4 43 ), 44 EnableBPD = false, // disable TAGE 45 EnableLoop = false, 46 TlbEntrySize = 4, 47 TlbSPEntrySize = 2, 48 PtwL1EntrySize = 2, 49 PtwL2EntrySize = 2, 50 PtwL3EntrySize = 4, 51 PtwSPEntrySize = 2, 52 useFakeDCache = true, 53 useFakePTW = true, 54 useFakeL1plusCache = true, 55 )), 56 useFakeL3Cache = true 57 ) 58 }) 59)