1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => 2 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 _.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 CommitWidth = 6, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 24, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 // ============ VLSU ============ 81 VlMergeBufferSize = 8, 82 VsMergeBufferSize = 8, 83 UopWritebackWidth = 1, 84 SplitBufferSize = 8, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 8, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 4, 101 LsDqDeqWidth = 6 102 ), 103 intPreg = IntPregParams( 104 numEntries = 64, 105 numRead = None, 106 numWrite = None, 107 ), 108 vfPreg = VfPregParams( 109 numEntries = 160, 110 numRead = None, 111 numWrite = None, 112 ), 113 icacheParameters = ICacheParameters( 114 nSets = 64, // 16KB ICache 115 tagECC = Some("parity"), 116 dataECC = Some("parity"), 117 replacer = Some("setplru"), 118 nMissEntries = 2, 119 nReleaseEntries = 1, 120 nProbeEntries = 2, 121 // fdip 122 enableICachePrefetch = true, 123 prefetchToL1 = false, 124 ), 125 dcacheParametersOpt = Some(DCacheParameters( 126 nSets = 64, // 32KB DCache 127 nWays = 8, 128 tagECC = Some("secded"), 129 dataECC = Some("secded"), 130 replacer = Some("setplru"), 131 nMissEntries = 4, 132 nProbeEntries = 4, 133 nReleaseEntries = 8, 134 nMaxPrefetchEntry = 2, 135 )), 136 EnableBPD = false, // disable TAGE 137 EnableLoop = false, 138 itlbParameters = TLBParameters( 139 name = "itlb", 140 fetchi = true, 141 useDmode = false, 142 NWays = 4, 143 ), 144 ldtlbParameters = TLBParameters( 145 name = "ldtlb", 146 NWays = 4, 147 partialStaticPMP = true, 148 outsideRecvFlush = true, 149 outReplace = false, 150 lgMaxSize = 4 151 ), 152 sttlbParameters = TLBParameters( 153 name = "sttlb", 154 NWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false, 158 lgMaxSize = 4 159 ), 160 hytlbParameters = TLBParameters( 161 name = "hytlb", 162 NWays = 4, 163 partialStaticPMP = true, 164 outsideRecvFlush = true, 165 outReplace = false, 166 lgMaxSize = 4 167 ), 168 pftlbParameters = TLBParameters( 169 name = "pftlb", 170 NWays = 4, 171 partialStaticPMP = true, 172 outsideRecvFlush = true, 173 outReplace = false, 174 lgMaxSize = 4 175 ), 176 btlbParameters = TLBParameters( 177 name = "btlb", 178 NWays = 4, 179 ), 180 l2tlbParameters = L2TLBParameters( 181 l1Size = 4, 182 l2nSets = 4, 183 l2nWays = 4, 184 l3nSets = 4, 185 l3nWays = 8, 186 spSize = 2, 187 ), 188 L2CacheParamsOpt = Some(L2Param( 189 name = "L2", 190 ways = 8, 191 sets = 128, 192 echoField = Seq(huancun.DirtyField()), 193 prefetch = None 194 )), 195 L2NBanks = 2, 196 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 197 ) 198 ) 199 case SoCParamsKey => 200 val tiles = site(XSTileKey) 201 up(SoCParamsKey).copy( 202 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 203 sets = 1024, 204 inclusive = false, 205 clientCaches = tiles.map{ core => 206 val clientDirBytes = tiles.map{ t => 207 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 208 }.sum 209 val l2params = core.L2CacheParamsOpt.get.toCacheParams 210 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 211 }, 212 simulation = !site(DebugOptionsKey).FPGAPlatform, 213 prefetch = None 214 )), 215 L3NBanks = 1 216 ) 217 }) 218) 219 220// Non-synthesizable MinimalConfig, for fast simulation only 221class MinimalSimConfig(n: Int = 1) extends Config( 222 new MinimalConfig(n).alter((site, here, up) => { 223 case XSTileKey => up(XSTileKey).map(_.copy( 224 dcacheParametersOpt = None, 225 softPTW = true 226 )) 227 case SoCParamsKey => up(SoCParamsKey).copy( 228 L3CacheParamsOpt = None 229 ) 230 }) 231) 232 233class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 234 case XSTileKey => 235 val sets = n * 1024 / ways / 64 236 up(XSTileKey).map(_.copy( 237 dcacheParametersOpt = Some(DCacheParameters( 238 nSets = sets, 239 nWays = ways, 240 tagECC = Some("secded"), 241 dataECC = Some("secded"), 242 replacer = Some("setplru"), 243 nMissEntries = 16, 244 nProbeEntries = 8, 245 nReleaseEntries = 18, 246 nMaxPrefetchEntry = 6, 247 )) 248 )) 249}) 250 251class WithNKBL2 252( 253 n: Int, 254 ways: Int = 8, 255 inclusive: Boolean = true, 256 banks: Int = 1 257) extends Config((site, here, up) => { 258 case XSTileKey => 259 require(inclusive, "L2 must be inclusive") 260 val upParams = up(XSTileKey) 261 val l2sets = n * 1024 / banks / ways / 64 262 upParams.map(p => p.copy( 263 L2CacheParamsOpt = Some(L2Param( 264 name = "L2", 265 ways = ways, 266 sets = l2sets, 267 clientCaches = Seq(L1Param( 268 "dcache", 269 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 270 ways = p.dcacheParametersOpt.get.nWays + 2, 271 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 272 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 273 )), 274 reqField = Seq(utility.ReqSourceField()), 275 echoField = Seq(huancun.DirtyField()), 276 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 277 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 278 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 279 )), 280 L2NBanks = banks 281 )) 282}) 283 284class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 285 case SoCParamsKey => 286 val sets = n * 1024 / banks / ways / 64 287 val tiles = site(XSTileKey) 288 val clientDirBytes = tiles.map{ t => 289 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 290 }.sum 291 up(SoCParamsKey).copy( 292 L3NBanks = banks, 293 L3CacheParamsOpt = Some(HCCacheParameters( 294 name = "L3", 295 level = 3, 296 ways = ways, 297 sets = sets, 298 inclusive = inclusive, 299 clientCaches = tiles.map{ core => 300 val l2params = core.L2CacheParamsOpt.get.toCacheParams 301 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 302 }, 303 enablePerf = true, 304 ctrl = Some(CacheCtrl( 305 address = 0x39000000, 306 numCores = tiles.size 307 )), 308 reqField = Seq(utility.ReqSourceField()), 309 sramClkDivBy2 = true, 310 sramDepthDiv = 4, 311 tagECC = Some("secded"), 312 dataECC = Some("secded"), 313 simulation = !site(DebugOptionsKey).FPGAPlatform, 314 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 315 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 316 )) 317 ) 318}) 319 320class WithL3DebugConfig extends Config( 321 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 322) 323 324class MinimalL3DebugConfig(n: Int = 1) extends Config( 325 new WithL3DebugConfig ++ new MinimalConfig(n) 326) 327 328class DefaultL3DebugConfig(n: Int = 1) extends Config( 329 new WithL3DebugConfig ++ new BaseConfig(n) 330) 331 332class WithFuzzer extends Config((site, here, up) => { 333 case DebugOptionsKey => up(DebugOptionsKey).copy( 334 EnablePerfDebug = false, 335 ) 336 case SoCParamsKey => up(SoCParamsKey).copy( 337 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 338 enablePerf = false, 339 )), 340 ) 341 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 342 p.copy( 343 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 344 enablePerf = false, 345 )), 346 ) 347 } 348}) 349 350class MinimalAliasDebugConfig(n: Int = 1) extends Config( 351 new WithNKBL3(512, inclusive = false) ++ 352 new WithNKBL2(256, inclusive = true) ++ 353 new WithNKBL1D(128) ++ 354 new MinimalConfig(n) 355) 356 357class MediumConfig(n: Int = 1) extends Config( 358 new WithNKBL3(4096, inclusive = false, banks = 4) 359 ++ new WithNKBL2(512, inclusive = true) 360 ++ new WithNKBL1D(128) 361 ++ new BaseConfig(n) 362) 363 364class FuzzConfig(dummy: Int = 0) extends Config( 365 new WithFuzzer 366 ++ new DefaultConfig(1) 367) 368 369class DefaultConfig(n: Int = 1) extends Config( 370 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 371 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 372 ++ new WithNKBL1D(64, ways = 4) 373 ++ new BaseConfig(n) 374) 375