1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config._ 20import chisel3._ 21import chisel3.util._ 22import device.{EnableJtag, XSDebugModuleParams} 23import freechips.rocketchip.devices.debug._ 24import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 25import system._ 26import utility._ 27import utils._ 28import huancun._ 29import xiangshan._ 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend.icache.ICacheParameters 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 CommitWidth = 2, 61 FetchWidth = 4, 62 NRPhyRegs = 96, 63 IntPhyRegs = 96, 64 VfPhyRegs = 96, 65 LoadQueueSize = 16, 66 LoadQueueNWriteBanks = 4, 67 StoreQueueSize = 12, 68 StoreQueueNWriteBanks = 4, 69 RobSize = 32, 70 FtqSize = 8, 71 IBufSize = 16, 72 StoreBufferSize = 4, 73 StoreBufferThreshold = 3, 74 dpParams = DispatchParameters( 75 IntDqSize = 12, 76 FpDqSize = 12, 77 LsDqSize = 12, 78 IntDqDeqWidth = 4, 79 FpDqDeqWidth = 4, 80 LsDqDeqWidth = 4 81 ), 82 intPreg = IntPregParams( 83 numEntries = 128, 84 numRead = 14, 85 numWrite = 8, 86 ), 87 vfPreg = VfPregParams( 88 numEntries = 128, 89 numRead = 14, 90 numWrite = 8, 91 ), 92 icacheParameters = ICacheParameters( 93 nSets = 64, // 16KB ICache 94 tagECC = Some("parity"), 95 dataECC = Some("parity"), 96 replacer = Some("setplru"), 97 nMissEntries = 2, 98 nReleaseEntries = 1, 99 nProbeEntries = 2, 100 nPrefetchEntries = 2, 101 hasPrefetch = false 102 ), 103 dcacheParametersOpt = Some(DCacheParameters( 104 nSets = 64, // 32KB DCache 105 nWays = 8, 106 tagECC = Some("secded"), 107 dataECC = Some("secded"), 108 replacer = Some("setplru"), 109 nMissEntries = 4, 110 nProbeEntries = 4, 111 nReleaseEntries = 8, 112 )), 113 EnableBPD = false, // disable TAGE 114 EnableLoop = false, 115 itlbParameters = TLBParameters( 116 name = "itlb", 117 fetchi = true, 118 useDmode = false, 119 normalReplacer = Some("plru"), 120 superReplacer = Some("plru"), 121 normalNWays = 4, 122 normalNSets = 1, 123 superNWays = 2 124 ), 125 ldtlbParameters = TLBParameters( 126 name = "ldtlb", 127 normalNSets = 16, // when da or sa 128 normalNWays = 1, // when fa or sa 129 normalAssociative = "sa", 130 normalReplacer = Some("setplru"), 131 superNWays = 4, 132 normalAsVictim = true, 133 partialStaticPMP = true, 134 outsideRecvFlush = true, 135 outReplace = false 136 ), 137 sttlbParameters = TLBParameters( 138 name = "sttlb", 139 normalNSets = 16, // when da or sa 140 normalNWays = 1, // when fa or sa 141 normalAssociative = "sa", 142 normalReplacer = Some("setplru"), 143 normalAsVictim = true, 144 superNWays = 4, 145 partialStaticPMP = true, 146 outsideRecvFlush = true, 147 outReplace = false 148 ), 149 btlbParameters = TLBParameters( 150 name = "btlb", 151 normalNSets = 1, 152 normalNWays = 8, 153 superNWays = 2 154 ), 155 l2tlbParameters = L2TLBParameters( 156 l1Size = 4, 157 l2nSets = 4, 158 l2nWays = 4, 159 l3nSets = 4, 160 l3nWays = 8, 161 spSize = 2, 162 ), 163 L2CacheParamsOpt = None // remove L2 Cache 164 ) 165 ) 166 case SoCParamsKey => 167 val tiles = site(XSTileKey) 168 up(SoCParamsKey).copy( 169 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 170 sets = 1024, 171 inclusive = false, 172 clientCaches = tiles.map{ p => 173 CacheParameters( 174 "dcache", 175 sets = 2 * p.dcacheParametersOpt.get.nSets, 176 ways = p.dcacheParametersOpt.get.nWays + 2, 177 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 178 aliasBitsOpt = None 179 ) 180 }, 181 simulation = !site(DebugOptionsKey).FPGAPlatform 182 )), 183 L3NBanks = 1 184 ) 185 }) 186) 187 188// Non-synthesizable MinimalConfig, for fast simulation only 189class MinimalSimConfig(n: Int = 1) extends Config( 190 new MinimalConfig(n).alter((site, here, up) => { 191 case XSTileKey => up(XSTileKey).map(_.copy( 192 dcacheParametersOpt = None, 193 softPTW = true 194 )) 195 case SoCParamsKey => up(SoCParamsKey).copy( 196 L3CacheParamsOpt = None 197 ) 198 }) 199) 200 201class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 202 case XSTileKey => 203 val sets = n * 1024 / ways / 64 204 up(XSTileKey).map(_.copy( 205 dcacheParametersOpt = Some(DCacheParameters( 206 nSets = sets, 207 nWays = ways, 208 tagECC = Some("secded"), 209 dataECC = Some("secded"), 210 replacer = Some("setplru"), 211 nMissEntries = 16, 212 nProbeEntries = 8, 213 nReleaseEntries = 18 214 )) 215 )) 216}) 217 218class WithNKBL2 219( 220 n: Int, 221 ways: Int = 8, 222 inclusive: Boolean = true, 223 banks: Int = 1, 224 alwaysReleaseData: Boolean = false 225) extends Config((site, here, up) => { 226 case XSTileKey => 227 val upParams = up(XSTileKey) 228 val l2sets = n * 1024 / banks / ways / 64 229 upParams.map(p => p.copy( 230 L2CacheParamsOpt = Some(HCCacheParameters( 231 name = "L2", 232 level = 2, 233 ways = ways, 234 sets = l2sets, 235 inclusive = inclusive, 236 alwaysReleaseData = alwaysReleaseData, 237 clientCaches = Seq(CacheParameters( 238 "dcache", 239 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 240 ways = p.dcacheParametersOpt.get.nWays + 2, 241 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 242 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 243 )), 244 reqField = Seq(PreferCacheField()), 245 echoField = Seq(DirtyField()), 246 prefetch = Some(huancun.prefetch.BOPParameters()), 247 enablePerf = true, 248 sramDepthDiv = 2, 249 tagECC = Some("secded"), 250 dataECC = Some("secded"), 251 simulation = !site(DebugOptionsKey).FPGAPlatform 252 )), 253 L2NBanks = banks 254 )) 255}) 256 257class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 258 case SoCParamsKey => 259 val sets = n * 1024 / banks / ways / 64 260 val tiles = site(XSTileKey) 261 val clientDirBytes = tiles.map{ t => 262 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 263 }.sum 264 up(SoCParamsKey).copy( 265 L3NBanks = banks, 266 L3CacheParamsOpt = Some(HCCacheParameters( 267 name = "L3", 268 level = 3, 269 ways = ways, 270 sets = sets, 271 inclusive = inclusive, 272 clientCaches = tiles.map{ core => 273 val l2params = core.L2CacheParamsOpt.get.toCacheParams 274 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 275 }, 276 enablePerf = true, 277 ctrl = Some(CacheCtrl( 278 address = 0x39000000, 279 numCores = tiles.size 280 )), 281 sramClkDivBy2 = true, 282 sramDepthDiv = 4, 283 tagECC = Some("secded"), 284 dataECC = Some("secded"), 285 simulation = !site(DebugOptionsKey).FPGAPlatform 286 )) 287 ) 288}) 289 290class WithL3DebugConfig extends Config( 291 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 292) 293 294class MinimalL3DebugConfig(n: Int = 1) extends Config( 295 new WithL3DebugConfig ++ new MinimalConfig(n) 296) 297 298class DefaultL3DebugConfig(n: Int = 1) extends Config( 299 new WithL3DebugConfig ++ new BaseConfig(n) 300) 301 302class MinimalAliasDebugConfig(n: Int = 1) extends Config( 303 new WithNKBL3(512, inclusive = false) ++ 304 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 305 new WithNKBL1D(128) ++ 306 new MinimalConfig(n) 307) 308 309class MediumConfig(n: Int = 1) extends Config( 310 new WithNKBL3(4096, inclusive = false, banks = 4) 311 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 312 ++ new WithNKBL1D(128) 313 ++ new BaseConfig(n) 314) 315 316class DefaultConfig(n: Int = 1) extends Config( 317 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 318 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 319 ++ new WithNKBL1D(128) 320 ++ new BaseConfig(n) 321) 322