1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config._ 20import chisel3._ 21import chisel3.util._ 22import device.{EnableJtag, XSDebugModuleParams} 23import freechips.rocketchip.devices.debug._ 24import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 25import system._ 26import utility._ 27import utils._ 28import huancun._ 29import xiangshan._ 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37import xiangshan.frontend.icache.ICacheParameters 38 39class BaseConfig(n: Int) extends Config((site, here, up) => { 40 case XLen => 64 41 case DebugOptionsKey => DebugOptions() 42 case SoCParamsKey => SoCParameters() 43 case PMParameKey => PMParameters() 44 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 45 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 46 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 47 case JtagDTMKey => JtagDTMKey 48 case MaxHartIdBits => 2 49 case EnableJtag => true.B 50}) 51 52// Synthesizable minimal XiangShan 53// * It is still an out-of-order, super-scalaer arch 54// * L1 cache included 55// * L2 cache NOT included 56// * L3 cache included 57class MinimalConfig(n: Int = 1) extends Config( 58 new BaseConfig(n).alter((site, here, up) => { 59 case XSTileKey => up(XSTileKey).map( 60 _.copy( 61 DecodeWidth = 2, 62 RenameWidth = 2, 63 CommitWidth = 2, 64 FetchWidth = 4, 65 VirtualLoadQueueSize = 16, 66 LoadQueueRARSize = 16, 67 LoadQueueRAWSize = 12, 68 LoadQueueReplaySize = 8, 69 LoadUncacheBufferSize = 8, 70 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 71 RollbackGroupSize = 8, 72 StoreQueueSize = 12, 73 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 74 StoreQueueForwardWithMask = true, 75 RobSize = 32, 76 FtqSize = 8, 77 IBufSize = 16, 78 StoreBufferSize = 4, 79 StoreBufferThreshold = 3, 80 dpParams = DispatchParameters( 81 IntDqSize = 12, 82 FpDqSize = 12, 83 LsDqSize = 12, 84 IntDqDeqWidth = 4, 85 FpDqDeqWidth = 4, 86 LsDqDeqWidth = 4 87 ), 88 intPreg = IntPregParams( 89 numEntries = 64, 90 numRead = Some(14), 91 numWrite = Some(8), 92 ), 93 vfPreg = VfPregParams( 94 numEntries = 96, 95 numRead = Some(14), 96 numWrite = Some(8), 97 ), 98 icacheParameters = ICacheParameters( 99 nSets = 64, // 16KB ICache 100 tagECC = Some("parity"), 101 dataECC = Some("parity"), 102 replacer = Some("setplru"), 103 nMissEntries = 2, 104 nReleaseEntries = 1, 105 nProbeEntries = 2, 106 nPrefetchEntries = 2, 107 nPrefBufferEntries = 32, 108 hasPrefetch = true 109 ), 110 dcacheParametersOpt = Some(DCacheParameters( 111 nSets = 64, // 32KB DCache 112 nWays = 8, 113 tagECC = Some("secded"), 114 dataECC = Some("secded"), 115 replacer = Some("setplru"), 116 nMissEntries = 4, 117 nProbeEntries = 4, 118 nReleaseEntries = 8, 119 )), 120 EnableBPD = false, // disable TAGE 121 EnableLoop = false, 122 itlbParameters = TLBParameters( 123 name = "itlb", 124 fetchi = true, 125 useDmode = false, 126 normalReplacer = Some("plru"), 127 superReplacer = Some("plru"), 128 normalNWays = 4, 129 normalNSets = 1, 130 superNWays = 2 131 ), 132 ldtlbParameters = TLBParameters( 133 name = "ldtlb", 134 normalNSets = 16, // when da or sa 135 normalNWays = 1, // when fa or sa 136 normalAssociative = "sa", 137 normalReplacer = Some("setplru"), 138 superNWays = 4, 139 normalAsVictim = true, 140 partialStaticPMP = true, 141 outsideRecvFlush = true, 142 outReplace = false 143 ), 144 sttlbParameters = TLBParameters( 145 name = "sttlb", 146 normalNSets = 16, // when da or sa 147 normalNWays = 1, // when fa or sa 148 normalAssociative = "sa", 149 normalReplacer = Some("setplru"), 150 normalAsVictim = true, 151 superNWays = 4, 152 partialStaticPMP = true, 153 outsideRecvFlush = true, 154 outReplace = false 155 ), 156 pftlbParameters = TLBParameters( 157 name = "pftlb", 158 normalNSets = 16, // when da or sa 159 normalNWays = 1, // when fa or sa 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 normalAsVictim = true, 163 superNWays = 4, 164 partialStaticPMP = true, 165 outsideRecvFlush = true, 166 outReplace = false 167 ), 168 btlbParameters = TLBParameters( 169 name = "btlb", 170 normalNSets = 1, 171 normalNWays = 8, 172 superNWays = 2 173 ), 174 l2tlbParameters = L2TLBParameters( 175 l1Size = 4, 176 l2nSets = 4, 177 l2nWays = 4, 178 l3nSets = 4, 179 l3nWays = 8, 180 spSize = 2, 181 ), 182 L2CacheParamsOpt = Some(L2Param( 183 name = "L2", 184 ways = 8, 185 sets = 128, 186 echoField = Seq(huancun.DirtyField()), 187 prefetch = None 188 )), 189 L2NBanks = 2, 190 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 191 ) 192 ) 193 case SoCParamsKey => 194 val tiles = site(XSTileKey) 195 up(SoCParamsKey).copy( 196 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 197 sets = 1024, 198 inclusive = false, 199 clientCaches = tiles.map{ core => 200 val clientDirBytes = tiles.map{ t => 201 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 202 }.sum 203 val l2params = core.L2CacheParamsOpt.get.toCacheParams 204 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 205 }, 206 simulation = !site(DebugOptionsKey).FPGAPlatform 207 )), 208 L3NBanks = 1 209 ) 210 }) 211) 212 213// Non-synthesizable MinimalConfig, for fast simulation only 214class MinimalSimConfig(n: Int = 1) extends Config( 215 new MinimalConfig(n).alter((site, here, up) => { 216 case XSTileKey => up(XSTileKey).map(_.copy( 217 dcacheParametersOpt = None, 218 softPTW = true 219 )) 220 case SoCParamsKey => up(SoCParamsKey).copy( 221 L3CacheParamsOpt = None 222 ) 223 }) 224) 225 226class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 227 case XSTileKey => 228 val sets = n * 1024 / ways / 64 229 up(XSTileKey).map(_.copy( 230 dcacheParametersOpt = Some(DCacheParameters( 231 nSets = sets, 232 nWays = ways, 233 tagECC = Some("secded"), 234 dataECC = Some("secded"), 235 replacer = Some("setplru"), 236 nMissEntries = 16, 237 nProbeEntries = 8, 238 nReleaseEntries = 18 239 )) 240 )) 241}) 242 243class WithNKBL2 244( 245 n: Int, 246 ways: Int = 8, 247 inclusive: Boolean = true, 248 banks: Int = 1 249) extends Config((site, here, up) => { 250 case XSTileKey => 251 val upParams = up(XSTileKey) 252 val l2sets = n * 1024 / banks / ways / 64 253 upParams.map(p => p.copy( 254 L2CacheParamsOpt = Some(L2Param( 255 name = "L2", 256 ways = ways, 257 sets = l2sets, 258 clientCaches = Seq(L1Param( 259 "dcache", 260 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 261 ways = p.dcacheParametersOpt.get.nWays + 2, 262 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 263 )), 264 reqField = Seq(utility.ReqSourceField()), 265 echoField = Seq(huancun.DirtyField()), 266 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 267 )), 268 L2NBanks = banks 269 )) 270}) 271 272class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 273 case SoCParamsKey => 274 val sets = n * 1024 / banks / ways / 64 275 val tiles = site(XSTileKey) 276 val clientDirBytes = tiles.map{ t => 277 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 278 }.sum 279 up(SoCParamsKey).copy( 280 L3NBanks = banks, 281 L3CacheParamsOpt = Some(HCCacheParameters( 282 name = "L3", 283 level = 3, 284 ways = ways, 285 sets = sets, 286 inclusive = inclusive, 287 clientCaches = tiles.map{ core => 288 val l2params = core.L2CacheParamsOpt.get.toCacheParams 289 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 290 }, 291 enablePerf = true, 292 ctrl = Some(CacheCtrl( 293 address = 0x39000000, 294 numCores = tiles.size 295 )), 296 reqField = Seq(utility.ReqSourceField()), 297 sramClkDivBy2 = true, 298 sramDepthDiv = 4, 299 tagECC = Some("secded"), 300 dataECC = Some("secded"), 301 simulation = !site(DebugOptionsKey).FPGAPlatform 302 )) 303 ) 304}) 305 306class WithL3DebugConfig extends Config( 307 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 308) 309 310class MinimalL3DebugConfig(n: Int = 1) extends Config( 311 new WithL3DebugConfig ++ new MinimalConfig(n) 312) 313 314class DefaultL3DebugConfig(n: Int = 1) extends Config( 315 new WithL3DebugConfig ++ new BaseConfig(n) 316) 317 318class MinimalAliasDebugConfig(n: Int = 1) extends Config( 319 new WithNKBL3(512, inclusive = false) ++ 320 new WithNKBL2(256, inclusive = false) ++ 321 new WithNKBL1D(128) ++ 322 new MinimalConfig(n) 323) 324 325class MediumConfig(n: Int = 1) extends Config( 326 new WithNKBL3(4096, inclusive = false, banks = 4) 327 ++ new WithNKBL2(512, inclusive = false) 328 ++ new WithNKBL1D(128) 329 ++ new BaseConfig(n) 330) 331 332class DefaultConfig(n: Int = 1) extends Config( 333 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 334 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 335 ++ new WithNKBL1D(128) 336 ++ new BaseConfig(n) 337) 338