1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RobSize = 32, 66 FtqSize = 8, 67 IBufSize = 16, 68 StoreBufferSize = 4, 69 StoreBufferThreshold = 3, 70 dpParams = DispatchParameters( 71 IntDqSize = 12, 72 FpDqSize = 12, 73 LsDqSize = 12, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 2, 81 MulCnt = 0, 82 MduCnt = 1, 83 FmacCnt = 1, 84 FmiscCnt = 1, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 icacheParameters = ICacheParameters( 90 nSets = 64, // 16KB ICache 91 tagECC = Some("parity"), 92 dataECC = Some("parity"), 93 replacer = Some("setplru"), 94 nMissEntries = 2, 95 nReleaseEntries = 2 96 ), 97 dcacheParametersOpt = Some(DCacheParameters( 98 nSets = 64, // 32KB DCache 99 nWays = 8, 100 tagECC = Some("secded"), 101 dataECC = Some("secded"), 102 replacer = Some("setplru"), 103 nMissEntries = 4, 104 nProbeEntries = 4, 105 nReleaseEntries = 8, 106 )), 107 EnableBPD = false, // disable TAGE 108 EnableLoop = false, 109 itlbParameters = TLBParameters( 110 name = "itlb", 111 fetchi = true, 112 useDmode = false, 113 sameCycle = false, 114 missSameCycle = true, 115 normalReplacer = Some("plru"), 116 superReplacer = Some("plru"), 117 normalNWays = 4, 118 normalNSets = 1, 119 superNWays = 2, 120 shouldBlock = true 121 ), 122 ldtlbParameters = TLBParameters( 123 name = "ldtlb", 124 normalNSets = 4, // when da or sa 125 normalNWays = 1, // when fa or sa 126 normalAssociative = "sa", 127 normalReplacer = Some("setplru"), 128 superNWays = 4, 129 normalAsVictim = true, 130 partialStaticPMP = true, 131 outReplace = true 132 ), 133 sttlbParameters = TLBParameters( 134 name = "sttlb", 135 normalNSets = 4, // when da or sa 136 normalNWays = 1, // when fa or sa 137 normalAssociative = "sa", 138 normalReplacer = Some("setplru"), 139 normalAsVictim = true, 140 superNWays = 4, 141 partialStaticPMP = true, 142 outReplace = true 143 ), 144 btlbParameters = TLBParameters( 145 name = "btlb", 146 normalNSets = 1, 147 normalNWays = 8, 148 superNWays = 2 149 ), 150 l2tlbParameters = L2TLBParameters( 151 l1Size = 4, 152 l2nSets = 4, 153 l2nWays = 4, 154 l3nSets = 4, 155 l3nWays = 8, 156 spSize = 2, 157 ), 158 L2CacheParamsOpt = None // remove L2 Cache 159 ) 160 ) 161 case SoCParamsKey => up(SoCParamsKey).copy( 162 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 163 sets = 1024 164 )), 165 L3NBanks = 1 166 ) 167 }) 168) 169 170// Non-synthesizable MinimalConfig, for fast simulation only 171class MinimalSimConfig(n: Int = 1) extends Config( 172 new MinimalConfig(n).alter((site, here, up) => { 173 case XSTileKey => up(XSTileKey).map(_.copy( 174 dcacheParametersOpt = None, 175 softPTW = true 176 )) 177 case SoCParamsKey => up(SoCParamsKey).copy( 178 L3CacheParamsOpt = None 179 ) 180 }) 181) 182 183class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 184 case XSTileKey => 185 val sets = n * 1024 / ways / 64 186 up(XSTileKey).map(_.copy( 187 dcacheParametersOpt = Some(DCacheParameters( 188 nSets = sets, 189 nWays = ways, 190 tagECC = Some("secded"), 191 dataECC = Some("secded"), 192 replacer = Some("setplru"), 193 nMissEntries = 16, 194 nProbeEntries = 8, 195 nReleaseEntries = 18 196 )) 197 )) 198}) 199 200class WithNKBL2 201( 202 n: Int, 203 ways: Int = 8, 204 inclusive: Boolean = true, 205 banks: Int = 1, 206 alwaysReleaseData: Boolean = false 207) extends Config((site, here, up) => { 208 case XSTileKey => 209 val upParams = up(XSTileKey) 210 val l2sets = n * 1024 / banks / ways / 64 211 upParams.map(p => p.copy( 212 L2CacheParamsOpt = Some(HCCacheParameters( 213 name = "L2", 214 level = 2, 215 ways = ways, 216 sets = l2sets, 217 inclusive = inclusive, 218 alwaysReleaseData = alwaysReleaseData, 219 clientCaches = Seq(CacheParameters( 220 "dcache", 221 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 222 ways = p.dcacheParametersOpt.get.nWays + 2, 223 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 224 )), 225 reqField = Seq(PreferCacheField()), 226 echoField = Seq(DirtyField()), 227 prefetch = Some(huancun.prefetch.BOPParameters()), 228 enablePerf = true, 229 sramDepthDiv = 2, 230 tagECC = Some("secded"), 231 dataECC = Some("secded") 232 )), 233 L2NBanks = banks 234 )) 235}) 236 237class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 238 case SoCParamsKey => 239 val sets = n * 1024 / banks / ways / 64 240 val tiles = site(XSTileKey) 241 val clientDirBytes = tiles.map{ t => 242 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 243 }.sum 244 up(SoCParamsKey).copy( 245 L3NBanks = banks, 246 L3CacheParamsOpt = Some(HCCacheParameters( 247 name = "L3", 248 level = 3, 249 ways = ways, 250 sets = sets, 251 inclusive = inclusive, 252 clientCaches = tiles.map{ core => 253 val l2params = core.L2CacheParamsOpt.get.toCacheParams 254 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 255 }, 256 enablePerf = true, 257 ctrl = Some(CacheCtrl( 258 address = 0x39000000, 259 numCores = tiles.size 260 )), 261 sramClkDivBy2 = true, 262 sramDepthDiv = 4, 263 tagECC = Some("secded"), 264 dataECC = Some("secded") 265 )) 266 ) 267}) 268 269class WithL3DebugConfig extends Config( 270 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 271) 272 273class MinimalL3DebugConfig(n: Int = 1) extends Config( 274 new WithL3DebugConfig ++ new MinimalConfig(n) 275) 276 277class DefaultL3DebugConfig(n: Int = 1) extends Config( 278 new WithL3DebugConfig ++ new BaseConfig(n) 279) 280 281class MinimalAliasDebugConfig(n: Int = 1) extends Config( 282 new WithNKBL3(512, inclusive = false) ++ 283 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 284 new WithNKBL1D(128) ++ 285 new MinimalConfig(n) 286) 287 288class MediumConfig(n: Int = 1) extends Config( 289 new WithNKBL3(4096, inclusive = false, banks = 4) 290 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 291 ++ new WithNKBL1D(128) 292 ++ new BaseConfig(n) 293) 294 295class DefaultConfig(n: Int = 1) extends Config( 296 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 297 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 298 ++ new WithNKBL1D(128) 299 ++ new BaseConfig(n) 300) 301