1package utils 2 3import chisel3._ 4import chipsalliance.rocketchip.config.Parameters 5import chisel3.util.DecoupledIO 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import freechips.rocketchip.tilelink.{TLBundle, TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters} 8import xiangshan.HasXSLog 9 10class DebugIdentityNode()(implicit p: Parameters) extends LazyModule { 11 12 val node = TLIdentityNode() 13 14 val n = TLClientNode(Seq(TLMasterPortParameters.v1( 15 Seq( 16 TLMasterParameters.v1("debug node") 17 ) 18 ))) 19 20 lazy val module = new LazyModuleImp(this) with HasXSLog with HasTLDump{ 21 val (out, _) = node.out(0) 22 val (in, _) = node.in(0) 23 24 def debug(t: TLBundle, valid: Boolean = false): Unit ={ 25 def fire[T <: Data](x: DecoupledIO[T]) = if(valid) x.valid else x.fire() 26 val channels = Seq(t.a, t.b, t.c, t.d, t.e) 27 channels.foreach(c => 28 when(fire(c)){ 29 XSDebug(" isFire:%d ",c.fire()) 30 c.bits.dump 31 } 32 ) 33 } 34 debug(in, false) 35 } 36} 37 38object DebugIdentityNode { 39 def apply()(implicit p: Parameters): TLIdentityNode = { 40 val identityNode = LazyModule(new DebugIdentityNode()) 41 identityNode.node 42 } 43}