1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 32, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 256, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 256, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams("IEX0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 307 ExeUnitParams("IEX1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 311 ExeUnitParams("IDIV1", Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 315 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("IMISC0", Seq(I2fCfg, VSetRiWiCfg), Seq(VfWB(port = 3, Int.MaxValue), IntWB(port = 1, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 320 IssueBlockParams(Seq( 321 ExeUnitParams("IMISC1", Seq(VSetRiWvfCfg), Seq(VfWB(port = 3, Int.MaxValue)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 322 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 323 ), 324 numPregs = intPreg.numEntries, 325 numRfReadWrite = Some((numRfRead, numRfWrite)), 326 numDeqOutside = 0, 327 schdType = schdType, 328 rfDataWidth = intPreg.dataCfg.dataWidth, 329 numUopIn = dpParams.IntDqDeqWidth, 330 ) 331 } 332 def vfSchdParams = { 333 implicit val schdType: SchedulerType = VfScheduler() 334 val pregBits = vfPreg.addrWidth 335 val numRfRead = vfPreg.numRead 336 val numRfWrite = vfPreg.numWrite 337 SchdBlockParams(Seq( 338 IssueBlockParams(Seq( 339 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 340 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 341 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX2", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 344 ExeUnitParams("VEX3", Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 345 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 346 ), 347 numPregs = vfPreg.numEntries, 348 numRfReadWrite = Some((numRfRead, numRfWrite)), 349 numDeqOutside = 0, 350 schdType = schdType, 351 rfDataWidth = vfPreg.dataCfg.dataWidth, 352 numUopIn = dpParams.FpDqDeqWidth, 353 ) 354 } 355 def memSchdParams = { 356 implicit val schdType: SchedulerType = MemScheduler() 357 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 358 val rfDataWidth = 64 359 360 SchdBlockParams(Seq( 361 IssueBlockParams(Seq( 362 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 363 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 364 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 365 IssueBlockParams(Seq( 366 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 367 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 368 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 369 IssueBlockParams(Seq( 370 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 371 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 372 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 373 IssueBlockParams(Seq( 374 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 375 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 0)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 376 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 377 ), 378 numPregs = intPreg.numEntries max vfPreg.numEntries, 379 numRfReadWrite = None, 380 numDeqOutside = 0, 381 schdType = schdType, 382 rfDataWidth = rfDataWidth, 383 numUopIn = dpParams.LsDqDeqWidth, 384 ) 385 } 386 387 def backendParams: BackendParams = backend.BackendParams(Map( 388 IntScheduler() -> intSchdParams, 389 VfScheduler() -> vfSchdParams, 390 MemScheduler() -> memSchdParams, 391 ), Seq( 392 intPreg, 393 vfPreg, 394 )) 395} 396 397case object DebugOptionsKey extends Field[DebugOptions] 398 399case class DebugOptions 400( 401 FPGAPlatform: Boolean = false, 402 EnableDifftest: Boolean = false, 403 AlwaysBasicDiff: Boolean = true, 404 EnableDebug: Boolean = false, 405 EnablePerfDebug: Boolean = true, 406 UseDRAMSim: Boolean = false, 407 EnableConstantin: Boolean = false, 408 EnableTopDown: Boolean = false 409) 410 411trait HasXSParameter { 412 413 implicit val p: Parameters 414 415 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 416 417 val coreParams = p(XSCoreParamsKey) 418 val env = p(DebugOptionsKey) 419 420 val XLEN = coreParams.XLEN 421 val VLEN = coreParams.VLEN 422 val ELEN = coreParams.ELEN 423 val minFLen = 32 424 val fLen = 64 425 def xLen = XLEN 426 427 val HasMExtension = coreParams.HasMExtension 428 val HasCExtension = coreParams.HasCExtension 429 val HasDiv = coreParams.HasDiv 430 val HasIcache = coreParams.HasICache 431 val HasDcache = coreParams.HasDCache 432 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 433 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 434 val AsidLength = coreParams.AsidLength 435 val ReSelectLen = coreParams.ReSelectLen 436 val AddrBytes = AddrBits / 8 // unused 437 val DataBits = XLEN 438 val DataBytes = DataBits / 8 439 val HasFPU = coreParams.HasFPU 440 val HasVPU = coreParams.HasVPU 441 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 442 val FetchWidth = coreParams.FetchWidth 443 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 444 val EnableBPU = coreParams.EnableBPU 445 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 446 val EnableRAS = coreParams.EnableRAS 447 val EnableLB = coreParams.EnableLB 448 val EnableLoop = coreParams.EnableLoop 449 val EnableSC = coreParams.EnableSC 450 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 451 val HistoryLength = coreParams.HistoryLength 452 val EnableGHistDiff = coreParams.EnableGHistDiff 453 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 454 val UbtbGHRLength = coreParams.UbtbGHRLength 455 val UbtbSize = coreParams.UbtbSize 456 val EnableFauFTB = coreParams.EnableFauFTB 457 val FtbSize = coreParams.FtbSize 458 val FtbWays = coreParams.FtbWays 459 val RasSize = coreParams.RasSize 460 461 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 462 coreParams.branchPredictor(resp_in, p) 463 } 464 val numBr = coreParams.numBr 465 val TageTableInfos = coreParams.TageTableInfos 466 val TageBanks = coreParams.numBr 467 val SCNRows = coreParams.SCNRows 468 val SCCtrBits = coreParams.SCCtrBits 469 val SCHistLens = coreParams.SCHistLens 470 val SCNTables = coreParams.SCNTables 471 472 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 473 case ((n, cb), h) => (n, cb, h) 474 } 475 val ITTageTableInfos = coreParams.ITTageTableInfos 476 type FoldedHistoryInfo = Tuple2[Int, Int] 477 val foldedGHistInfos = 478 (TageTableInfos.map{ case (nRows, h, t) => 479 if (h > 0) 480 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 481 else 482 Set[FoldedHistoryInfo]() 483 }.reduce(_++_).toSet ++ 484 SCTableInfos.map{ case (nRows, _, h) => 485 if (h > 0) 486 Set((h, min(log2Ceil(nRows/TageBanks), h))) 487 else 488 Set[FoldedHistoryInfo]() 489 }.reduce(_++_).toSet ++ 490 ITTageTableInfos.map{ case (nRows, h, t) => 491 if (h > 0) 492 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 493 else 494 Set[FoldedHistoryInfo]() 495 }.reduce(_++_) ++ 496 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 497 ).toList 498 499 500 501 val CacheLineSize = coreParams.CacheLineSize 502 val CacheLineHalfWord = CacheLineSize / 16 503 val ExtHistoryLength = HistoryLength + 64 504 val IBufSize = coreParams.IBufSize 505 val DecodeWidth = coreParams.DecodeWidth 506 val RenameWidth = coreParams.RenameWidth 507 val CommitWidth = coreParams.CommitWidth 508 val MaxUopSize = coreParams.MaxUopSize 509 val FtqSize = coreParams.FtqSize 510 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 511 val IntLogicRegs = coreParams.IntLogicRegs 512 val FpLogicRegs = coreParams.FpLogicRegs 513 val VecLogicRegs = coreParams.VecLogicRegs 514 val VCONFIG_IDX = coreParams.VCONFIG_IDX 515 val NRPhyRegs = coreParams.NRPhyRegs 516 val PhyRegIdxWidth = log2Up(NRPhyRegs) 517 val IntPhyRegs = coreParams.IntPhyRegs 518 val VfPhyRegs = coreParams.VfPhyRegs 519 val IntPregIdxWidth = log2Up(IntPhyRegs) 520 val VfPregIdxWidth = log2Up(VfPhyRegs) 521 val RobSize = coreParams.RobSize 522 val RabSize = coreParams.RabSize 523 val IntRefCounterWidth = log2Ceil(RobSize) 524 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 525 val LoadQueueRARSize = coreParams.LoadQueueRARSize 526 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 527 val RollbackGroupSize = coreParams.RollbackGroupSize 528 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 529 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 530 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 531 val StoreQueueSize = coreParams.StoreQueueSize 532 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 533 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 534 val VlsQueueSize = coreParams.VlsQueueSize 535 val dpParams = coreParams.dpParams 536 537 def backendParams: BackendParams = coreParams.backendParams 538 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 539 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 540 val LoadPipelineWidth = coreParams.LoadPipelineWidth 541 val StorePipelineWidth = coreParams.StorePipelineWidth 542 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 543 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 544 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 545 val StoreBufferSize = coreParams.StoreBufferSize 546 val StoreBufferThreshold = coreParams.StoreBufferThreshold 547 val EnsbufferWidth = coreParams.EnsbufferWidth 548 val UncacheBufferSize = coreParams.UncacheBufferSize 549 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 550 val EnableFastForward = coreParams.EnableFastForward 551 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 552 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 553 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 554 val EnableDCacheWPU = coreParams.EnableDCacheWPU 555 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 556 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 557 val asidLen = coreParams.MMUAsidLen 558 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 559 val refillBothTlb = coreParams.refillBothTlb 560 val itlbParams = coreParams.itlbParameters 561 val ldtlbParams = coreParams.ldtlbParameters 562 val sttlbParams = coreParams.sttlbParameters 563 val pftlbParams = coreParams.pftlbParameters 564 val btlbParams = coreParams.btlbParameters 565 val l2tlbParams = coreParams.l2tlbParameters 566 val NumPerfCounters = coreParams.NumPerfCounters 567 568 val instBytes = if (HasCExtension) 2 else 4 569 val instOffsetBits = log2Ceil(instBytes) 570 571 val icacheParameters = coreParams.icacheParameters 572 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 573 574 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 575 // for constrained LR/SC loop 576 val LRSCCycles = 64 577 // for lr storm 578 val LRSCBackOff = 8 579 580 // cache hierarchy configurations 581 val l1BusDataWidth = 256 582 583 // load violation predict 584 val ResetTimeMax2Pow = 20 //1078576 585 val ResetTimeMin2Pow = 10 //1024 586 // wait table parameters 587 val WaitTableSize = 1024 588 val MemPredPCWidth = log2Up(WaitTableSize) 589 val LWTUse2BitCounter = true 590 // store set parameters 591 val SSITSize = WaitTableSize 592 val LFSTSize = 32 593 val SSIDWidth = log2Up(LFSTSize) 594 val LFSTWidth = 4 595 val StoreSetEnable = true // LWT will be disabled if SS is enabled 596 val LFSTEnable = false 597 598 val PCntIncrStep: Int = 6 599 val numPCntHc: Int = 25 600 val numPCntPtw: Int = 19 601 602 val numCSRPCntFrontend = 8 603 val numCSRPCntCtrl = 8 604 val numCSRPCntLsu = 8 605 val numCSRPCntHc = 5 606} 607