1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 1, 199 VecStorePipelineWidth: Int = 1, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 VecMemDispatchMaxNumber: Int = 16, 204 StoreBufferSize: Int = 16, 205 StoreBufferThreshold: Int = 7, 206 EnsbufferWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, 211 VLUopWritebackWidth: Int = 1, 212 VSUopWritebackWidth: Int = 1, 213 SplitBufferSize: Int = 8, 214 VSegmentBufferSize: Int = 8, 215 // ============================== 216 UncacheBufferSize: Int = 4, 217 EnableLoadToLoadForward: Boolean = false, 218 EnableFastForward: Boolean = true, 219 EnableLdVioCheckAfterReset: Boolean = true, 220 EnableSoftPrefetchAfterReset: Boolean = true, 221 EnableCacheErrorAfterReset: Boolean = true, 222 EnableAccurateLoadError: Boolean = true, 223 EnableUncacheWriteOutstanding: Boolean = false, 224 EnableStorePrefetchAtIssue: Boolean = false, 225 EnableStorePrefetchAtCommit: Boolean = false, 226 EnableAtCommitMissTrigger: Boolean = true, 227 EnableStorePrefetchSMS: Boolean = false, 228 EnableStorePrefetchSPB: Boolean = false, 229 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 230 ReSelectLen: Int = 7, // load replay queue replay select counter len 231 iwpuParameters: WPUParameters = WPUParameters( 232 enWPU = false, 233 algoName = "mmru", 234 isICache = true, 235 ), 236 dwpuParameters: WPUParameters = WPUParameters( 237 enWPU = false, 238 algoName = "mmru", 239 enCfPred = false, 240 isICache = false, 241 ), 242 itlbParameters: TLBParameters = TLBParameters( 243 name = "itlb", 244 fetchi = true, 245 useDmode = false, 246 NWays = 48, 247 ), 248 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 249 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 250 ldtlbParameters: TLBParameters = TLBParameters( 251 name = "ldtlb", 252 NWays = 48, 253 outReplace = false, 254 partialStaticPMP = true, 255 outsideRecvFlush = true, 256 saveLevel = true, 257 lgMaxSize = 4 258 ), 259 sttlbParameters: TLBParameters = TLBParameters( 260 name = "sttlb", 261 NWays = 48, 262 outReplace = false, 263 partialStaticPMP = true, 264 outsideRecvFlush = true, 265 saveLevel = true, 266 lgMaxSize = 4 267 ), 268 hytlbParameters: TLBParameters = TLBParameters( 269 name = "hytlb", 270 NWays = 48, 271 outReplace = false, 272 partialStaticPMP = true, 273 outsideRecvFlush = true, 274 saveLevel = true, 275 lgMaxSize = 4 276 ), 277 pftlbParameters: TLBParameters = TLBParameters( 278 name = "pftlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = true, 284 lgMaxSize = 4 285 ), 286 refillBothTlb: Boolean = false, 287 btlbParameters: TLBParameters = TLBParameters( 288 name = "btlb", 289 NWays = 48, 290 ), 291 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 292 NumPerfCounters: Int = 16, 293 icacheParameters: ICacheParameters = ICacheParameters( 294 tagECC = Some("parity"), 295 dataECC = Some("parity"), 296 replacer = Some("setplru"), 297 nMissEntries = 2, 298 nProbeEntries = 2, 299 nPrefetchEntries = 12, 300 nPrefBufferEntries = 32, 301 ), 302 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 303 tagECC = Some("secded"), 304 dataECC = Some("secded"), 305 replacer = Some("setplru"), 306 nMissEntries = 16, 307 nProbeEntries = 8, 308 nReleaseEntries = 18, 309 nMaxPrefetchEntry = 6, 310 )), 311 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 312 name = "l2", 313 ways = 8, 314 sets = 1024, // default 512KB L2 315 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 316 )), 317 L2NBanks: Int = 1, 318 usePTWRepeater: Boolean = false, 319 softTLB: Boolean = false, // dpi-c l1tlb debug only 320 softPTW: Boolean = false, // dpi-c l2tlb debug only 321 softPTWDelay: Int = 1 322){ 323 def vlWidth = log2Up(VLEN) + 1 324 325 /** 326 * the minimum element length of vector elements 327 */ 328 val minVecElen: Int = 8 329 330 /** 331 * the maximum number of elements in vector register 332 */ 333 val maxElemPerVreg: Int = VLEN / minVecElen 334 335 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 336 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 337 338 val intSchdParams = { 339 implicit val schdType: SchedulerType = IntScheduler() 340 SchdBlockParams(Seq( 341 IssueBlockParams(Seq( 342 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 343 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 344 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 345 IssueBlockParams(Seq( 346 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 347 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 348 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 349 IssueBlockParams(Seq( 350 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 351 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 352 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 353 IssueBlockParams(Seq( 354 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 355 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 356 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 357 ), 358 numPregs = intPreg.numEntries, 359 numDeqOutside = 0, 360 schdType = schdType, 361 rfDataWidth = intPreg.dataCfg.dataWidth, 362 numUopIn = dpParams.IntDqDeqWidth, 363 ) 364 } 365 val vfSchdParams = { 366 implicit val schdType: SchedulerType = VfScheduler() 367 SchdBlockParams(Seq( 368 IssueBlockParams(Seq( 369 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 370 ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))), 371 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 372 IssueBlockParams(Seq( 373 ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 374 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))), 375 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 376 ), 377 numPregs = vfPreg.numEntries, 378 numDeqOutside = 0, 379 schdType = schdType, 380 rfDataWidth = vfPreg.dataCfg.dataWidth, 381 numUopIn = dpParams.FpDqDeqWidth, 382 ) 383 } 384 385 val memSchdParams = { 386 implicit val schdType: SchedulerType = MemScheduler() 387 val rfDataWidth = 64 388 389 SchdBlockParams(Seq( 390 IssueBlockParams(Seq( 391 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 395 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 396 IssueBlockParams(Seq( 397 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 IssueBlockParams(Seq( 400 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 401 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 402 IssueBlockParams(Seq( 403 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 407 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 408 IssueBlockParams(Seq( 409 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 IssueBlockParams(Seq( 412 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 ), 415 numPregs = intPreg.numEntries max vfPreg.numEntries, 416 numDeqOutside = 0, 417 schdType = schdType, 418 rfDataWidth = rfDataWidth, 419 numUopIn = dpParams.LsDqDeqWidth, 420 ) 421 } 422 423 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 424 425 def iqWakeUpParams = { 426 Seq( 427 WakeUpConfig( 428 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 429 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 430 ), 431 WakeUpConfig( 432 Seq("VFEX0", "VFEX1", "VFEX2") -> 433 Seq("VFEX0", "VFEX1", "VFEX2") 434 ), 435 ).flatten 436 } 437 438 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 439 440 val backendParams: BackendParams = backend.BackendParams( 441 Map( 442 IntScheduler() -> intSchdParams, 443 VfScheduler() -> vfSchdParams, 444 MemScheduler() -> memSchdParams, 445 ), 446 Seq( 447 intPreg, 448 vfPreg, 449 fakeIntPreg 450 ), 451 iqWakeUpParams, 452 ) 453} 454 455case object DebugOptionsKey extends Field[DebugOptions] 456 457case class DebugOptions 458( 459 FPGAPlatform: Boolean = false, 460 EnableDifftest: Boolean = false, 461 AlwaysBasicDiff: Boolean = true, 462 EnableDebug: Boolean = false, 463 EnablePerfDebug: Boolean = true, 464 UseDRAMSim: Boolean = false, 465 EnableConstantin: Boolean = false, 466 EnableChiselDB: Boolean = false, 467 AlwaysBasicDB: Boolean = true, 468 EnableTopDown: Boolean = false, 469 EnableRollingDB: Boolean = false 470) 471 472trait HasXSParameter { 473 474 implicit val p: Parameters 475 476 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 477 478 val coreParams = p(XSCoreParamsKey) 479 val env = p(DebugOptionsKey) 480 481 val XLEN = coreParams.XLEN 482 val VLEN = coreParams.VLEN 483 val ELEN = coreParams.ELEN 484 val minFLen = 32 485 val fLen = 64 486 def xLen = XLEN 487 488 val HasMExtension = coreParams.HasMExtension 489 val HasCExtension = coreParams.HasCExtension 490 val HasDiv = coreParams.HasDiv 491 val HasIcache = coreParams.HasICache 492 val HasDcache = coreParams.HasDCache 493 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 494 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 495 val AsidLength = coreParams.AsidLength 496 val ReSelectLen = coreParams.ReSelectLen 497 val AddrBytes = AddrBits / 8 // unused 498 val DataBits = XLEN 499 val DataBytes = DataBits / 8 500 val VDataBytes = VLEN / 8 501 val HasFPU = coreParams.HasFPU 502 val HasVPU = coreParams.HasVPU 503 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 504 val FetchWidth = coreParams.FetchWidth 505 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 506 val EnableBPU = coreParams.EnableBPU 507 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 508 val EnableRAS = coreParams.EnableRAS 509 val EnableLB = coreParams.EnableLB 510 val EnableLoop = coreParams.EnableLoop 511 val EnableSC = coreParams.EnableSC 512 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 513 val HistoryLength = coreParams.HistoryLength 514 val EnableGHistDiff = coreParams.EnableGHistDiff 515 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 516 val EnableClockGate = coreParams.EnableClockGate 517 val UbtbGHRLength = coreParams.UbtbGHRLength 518 val UbtbSize = coreParams.UbtbSize 519 val EnableFauFTB = coreParams.EnableFauFTB 520 val FtbSize = coreParams.FtbSize 521 val FtbWays = coreParams.FtbWays 522 val RasSize = coreParams.RasSize 523 val RasSpecSize = coreParams.RasSpecSize 524 val RasCtrSize = coreParams.RasCtrSize 525 526 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 527 coreParams.branchPredictor(resp_in, p) 528 } 529 val numBr = coreParams.numBr 530 val TageTableInfos = coreParams.TageTableInfos 531 val TageBanks = coreParams.numBr 532 val SCNRows = coreParams.SCNRows 533 val SCCtrBits = coreParams.SCCtrBits 534 val SCHistLens = coreParams.SCHistLens 535 val SCNTables = coreParams.SCNTables 536 537 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 538 case ((n, cb), h) => (n, cb, h) 539 } 540 val ITTageTableInfos = coreParams.ITTageTableInfos 541 type FoldedHistoryInfo = Tuple2[Int, Int] 542 val foldedGHistInfos = 543 (TageTableInfos.map{ case (nRows, h, t) => 544 if (h > 0) 545 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 546 else 547 Set[FoldedHistoryInfo]() 548 }.reduce(_++_).toSet ++ 549 SCTableInfos.map{ case (nRows, _, h) => 550 if (h > 0) 551 Set((h, min(log2Ceil(nRows/TageBanks), h))) 552 else 553 Set[FoldedHistoryInfo]() 554 }.reduce(_++_).toSet ++ 555 ITTageTableInfos.map{ case (nRows, h, t) => 556 if (h > 0) 557 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 558 else 559 Set[FoldedHistoryInfo]() 560 }.reduce(_++_) ++ 561 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 562 ).toList 563 564 565 566 val CacheLineSize = coreParams.CacheLineSize 567 val CacheLineHalfWord = CacheLineSize / 16 568 val ExtHistoryLength = HistoryLength + 64 569 val ICacheECCForceError = coreParams.ICacheECCForceError 570 val IBufSize = coreParams.IBufSize 571 val IBufNBank = coreParams.IBufNBank 572 val backendParams: BackendParams = coreParams.backendParams 573 val DecodeWidth = coreParams.DecodeWidth 574 val RenameWidth = coreParams.RenameWidth 575 val CommitWidth = coreParams.CommitWidth 576 val MaxUopSize = coreParams.MaxUopSize 577 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 578 val RenameSnapshotNum = coreParams.RenameSnapshotNum 579 val FtqSize = coreParams.FtqSize 580 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 581 val IntLogicRegs = coreParams.IntLogicRegs 582 val FpLogicRegs = coreParams.FpLogicRegs 583 val VecLogicRegs = coreParams.VecLogicRegs 584 val VCONFIG_IDX = coreParams.VCONFIG_IDX 585 val IntPhyRegs = coreParams.intPreg.numEntries 586 val VfPhyRegs = coreParams.vfPreg.numEntries 587 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 588 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 589 val RobSize = coreParams.RobSize 590 val RabSize = coreParams.RabSize 591 val VTypeBufferSize = coreParams.VTypeBufferSize 592 /** 593 * the minimum element length of vector elements 594 */ 595 val minVecElen: Int = coreParams.minVecElen 596 597 /** 598 * the maximum number of elements in vector register 599 */ 600 val maxElemPerVreg: Int = coreParams.maxElemPerVreg 601 602 val IntRefCounterWidth = log2Ceil(RobSize) 603 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 604 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 605 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 606 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 607 val LoadQueueRARSize = coreParams.LoadQueueRARSize 608 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 609 val RollbackGroupSize = coreParams.RollbackGroupSize 610 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 611 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 612 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 613 val StoreQueueSize = coreParams.StoreQueueSize 614 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 615 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 616 val VlsQueueSize = coreParams.VlsQueueSize 617 val dpParams = coreParams.dpParams 618 619 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 620 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 621 622 val NumRedirect = backendParams.numRedirect 623 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 624 val FtqRedirectAheadNum = NumRedirect 625 val LoadPipelineWidth = coreParams.LoadPipelineWidth 626 val StorePipelineWidth = coreParams.StorePipelineWidth 627 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 628 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 629 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 630 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 631 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 632 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 633 val StoreBufferSize = coreParams.StoreBufferSize 634 val StoreBufferThreshold = coreParams.StoreBufferThreshold 635 val EnsbufferWidth = coreParams.EnsbufferWidth 636 val VlMergeBufferSize = coreParams.VlMergeBufferSize 637 val VsMergeBufferSize = coreParams.VsMergeBufferSize 638 val UopWritebackWidth = coreParams.UopWritebackWidth 639 val VLUopWritebackWidth = coreParams.VLUopWritebackWidth 640 val VSUopWritebackWidth = coreParams.VSUopWritebackWidth 641 val SplitBufferSize = coreParams.SplitBufferSize 642 val VSegmentBufferSize = coreParams.VSegmentBufferSize 643 val UncacheBufferSize = coreParams.UncacheBufferSize 644 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 645 val EnableFastForward = coreParams.EnableFastForward 646 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 647 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 648 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 649 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 650 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 651 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 652 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 653 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 654 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 655 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 656 val asidLen = coreParams.MMUAsidLen 657 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 658 val refillBothTlb = coreParams.refillBothTlb 659 val iwpuParam = coreParams.iwpuParameters 660 val dwpuParam = coreParams.dwpuParameters 661 val itlbParams = coreParams.itlbParameters 662 val ldtlbParams = coreParams.ldtlbParameters 663 val sttlbParams = coreParams.sttlbParameters 664 val hytlbParams = coreParams.hytlbParameters 665 val pftlbParams = coreParams.pftlbParameters 666 val btlbParams = coreParams.btlbParameters 667 val l2tlbParams = coreParams.l2tlbParameters 668 val NumPerfCounters = coreParams.NumPerfCounters 669 670 val instBytes = if (HasCExtension) 2 else 4 671 val instOffsetBits = log2Ceil(instBytes) 672 673 val icacheParameters = coreParams.icacheParameters 674 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 675 676 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 677 // for constrained LR/SC loop 678 val LRSCCycles = 64 679 // for lr storm 680 val LRSCBackOff = 8 681 682 // cache hierarchy configurations 683 val l1BusDataWidth = 256 684 685 // load violation predict 686 val ResetTimeMax2Pow = 20 //1078576 687 val ResetTimeMin2Pow = 10 //1024 688 // wait table parameters 689 val WaitTableSize = 1024 690 val MemPredPCWidth = log2Up(WaitTableSize) 691 val LWTUse2BitCounter = true 692 // store set parameters 693 val SSITSize = WaitTableSize 694 val LFSTSize = 32 695 val SSIDWidth = log2Up(LFSTSize) 696 val LFSTWidth = 4 697 val StoreSetEnable = true // LWT will be disabled if SS is enabled 698 val LFSTEnable = true 699 700 val PCntIncrStep: Int = 6 701 val numPCntHc: Int = 25 702 val numPCntPtw: Int = 19 703 704 val numCSRPCntFrontend = 8 705 val numCSRPCntCtrl = 8 706 val numCSRPCntLsu = 8 707 val numCSRPCntHc = 5 708 val printEventCoding = true 709 710 // Parameters for Sdtrig extension 711 protected val TriggerNum = 4 712 protected val TriggerChainMaxLength = 2 713} 714