1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import system.CVMParamskey 25import xiangshan.backend.datapath.RdConfig._ 26import xiangshan.backend.datapath.WbConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasBitmapCheck: Boolean = false, 65 HasBitmapCheckDefault: Boolean = false, 66 HasMExtension: Boolean = true, 67 HasCExtension: Boolean = true, 68 HasHExtension: Boolean = true, 69 HasDiv: Boolean = true, 70 HasICache: Boolean = true, 71 HasDCache: Boolean = true, 72 AddrBits: Int = 64, 73 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 74 VAddrBitsSv39: Int = 39, 75 GPAddrBitsSv39x4: Int = 41, 76 VAddrBitsSv48: Int = 48, 77 GPAddrBitsSv48x4: Int = 50, 78 HasFPU: Boolean = true, 79 HasVPU: Boolean = true, 80 HasCustomCSRCacheOp: Boolean = true, 81 FetchWidth: Int = 8, 82 AsidLength: Int = 16, 83 VmidLength: Int = 14, 84 EnableBPU: Boolean = true, 85 EnableBPD: Boolean = true, 86 EnableRAS: Boolean = true, 87 EnableLB: Boolean = false, 88 EnableLoop: Boolean = true, 89 EnableSC: Boolean = true, 90 EnbaleTlbDebug: Boolean = false, 91 EnableClockGate: Boolean = true, 92 EnableJal: Boolean = false, 93 EnableFauFTB: Boolean = true, 94 EnableSv48: Boolean = true, 95 UbtbGHRLength: Int = 4, 96 // HistoryLength: Int = 512, 97 EnableGHistDiff: Boolean = true, 98 EnableCommitGHistDiff: Boolean = true, 99 UbtbSize: Int = 256, 100 FtbSize: Int = 2048, 101 FtbWays: Int = 4, 102 FtbTagLength: Int = 20, 103 RasSize: Int = 16, 104 RasSpecSize: Int = 32, 105 RasCtrSize: Int = 3, 106 CacheLineSize: Int = 512, 107 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 108 // Sets Hist Tag 109 Seq(( 4096, 8, 8), 110 ( 4096, 13, 8), 111 ( 4096, 32, 8), 112 ( 4096, 119, 8)), 113 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 114 // Sets Hist Tag 115 Seq(( 256, 4, 9), 116 ( 256, 8, 9), 117 ( 512, 13, 9), 118 ( 512, 16, 9), 119 ( 512, 32, 9)), 120 SCNRows: Int = 512, 121 SCNTables: Int = 4, 122 SCCtrBits: Int = 6, 123 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 124 numBr: Int = 2, 125 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 126 (resp_in: BranchPredictionResp, p: Parameters) => { 127 val ftb = Module(new FTB()(p)) 128 val uftb = Module(new FauFTB()(p)) 129 val tage = Module(new Tage_SC()(p)) 130 val ras = Module(new RAS()(p)) 131 val ittage = Module(new ITTage()(p)) 132 val preds = Seq(uftb, tage, ftb, ittage, ras) 133 preds.map(_.io := DontCare) 134 135 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 136 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 137 138 uftb.io.in.bits.resp_in(0) := resp_in 139 tage.io.in.bits.resp_in(0) := uftb.io.out 140 ftb.io.in.bits.resp_in(0) := tage.io.out 141 ittage.io.in.bits.resp_in(0) := ftb.io.out 142 ras.io.in.bits.resp_in(0) := ittage.io.out 143 144 (preds, ras.io.out) 145 }, 146 ICacheForceMetaECCError: Boolean = false, 147 ICacheForceDataECCError: Boolean = false, 148 IBufSize: Int = 48, 149 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 150 DecodeWidth: Int = 6, 151 RenameWidth: Int = 6, 152 CommitWidth: Int = 8, 153 RobCommitWidth: Int = 8, 154 RabCommitWidth: Int = 6, 155 MaxUopSize: Int = 65, 156 EnableRenameSnapshot: Boolean = true, 157 RenameSnapshotNum: Int = 4, 158 FtqSize: Int = 64, 159 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 160 IntLogicRegs: Int = 32, 161 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 162 VecLogicRegs: Int = 32 + 15, // 15: tmp 163 V0LogicRegs: Int = 1, // V0 164 VlLogicRegs: Int = 1, // Vl 165 V0_IDX: Int = 0, 166 Vl_IDX: Int = 0, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 4, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 56, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 intPreg: PregParams = IntPregParams( 185 numEntries = 224, 186 numRead = None, 187 numWrite = None, 188 ), 189 fpPreg: PregParams = FpPregParams( 190 numEntries = 192, 191 numRead = None, 192 numWrite = None, 193 ), 194 vfPreg: VfPregParams = VfPregParams( 195 numEntries = 128, 196 numRead = None, 197 numWrite = None, 198 ), 199 v0Preg: V0PregParams = V0PregParams( 200 numEntries = 22, 201 numRead = None, 202 numWrite = None, 203 ), 204 vlPreg: VlPregParams = VlPregParams( 205 numEntries = 32, 206 numRead = None, 207 numWrite = None, 208 ), 209 IntRegCacheSize: Int = 16, 210 MemRegCacheSize: Int = 12, 211 intSchdVlWbPort: Int = 0, 212 vfSchdVlWbPort: Int = 1, 213 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 214 IfuRedirectNum: Int = 1, 215 LoadPipelineWidth: Int = 3, 216 StorePipelineWidth: Int = 2, 217 VecLoadPipelineWidth: Int = 2, 218 VecStorePipelineWidth: Int = 2, 219 VecMemSrcInWidth: Int = 2, 220 VecMemInstWbWidth: Int = 1, 221 VecMemDispatchWidth: Int = 1, 222 VecMemDispatchMaxNumber: Int = 16, 223 VecMemUnitStrideMaxFlowNum: Int = 2, 224 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 225 StoreBufferSize: Int = 16, 226 StoreBufferThreshold: Int = 7, 227 EnsbufferWidth: Int = 2, 228 LoadDependencyWidth: Int = 2, 229 // ============ VLSU ============ 230 VlMergeBufferSize: Int = 16, 231 VsMergeBufferSize: Int = 16, 232 UopWritebackWidth: Int = 2, 233 VLUopWritebackWidth: Int = 2, 234 VSUopWritebackWidth: Int = 1, 235 VSegmentBufferSize: Int = 8, 236 VFOFBufferSize: Int = 8, 237 VLFOFWritebackWidth: Int = 1, 238 // ============================== 239 UncacheBufferSize: Int = 4, 240 EnableLoadToLoadForward: Boolean = false, 241 EnableFastForward: Boolean = true, 242 EnableLdVioCheckAfterReset: Boolean = true, 243 EnableSoftPrefetchAfterReset: Boolean = true, 244 EnableCacheErrorAfterReset: Boolean = true, 245 EnableAccurateLoadError: Boolean = true, 246 EnableUncacheWriteOutstanding: Boolean = false, 247 EnableHardwareStoreMisalign: Boolean = true, 248 EnableHardwareLoadMisalign: Boolean = true, 249 EnableStorePrefetchAtIssue: Boolean = false, 250 EnableStorePrefetchAtCommit: Boolean = false, 251 EnableAtCommitMissTrigger: Boolean = true, 252 EnableStorePrefetchSMS: Boolean = false, 253 EnableStorePrefetchSPB: Boolean = false, 254 HasCMO: Boolean = true, 255 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 256 MMUVmidLen: Int = 14, 257 ReSelectLen: Int = 7, // load replay queue replay select counter len 258 iwpuParameters: WPUParameters = WPUParameters( 259 enWPU = false, 260 algoName = "mmru", 261 isICache = true, 262 ), 263 dwpuParameters: WPUParameters = WPUParameters( 264 enWPU = false, 265 algoName = "mmru", 266 enCfPred = false, 267 isICache = false, 268 ), 269 itlbParameters: TLBParameters = TLBParameters( 270 name = "itlb", 271 fetchi = true, 272 useDmode = false, 273 NWays = 48, 274 ), 275 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 276 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 277 ldtlbParameters: TLBParameters = TLBParameters( 278 name = "ldtlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = false, 284 lgMaxSize = 4 285 ), 286 sttlbParameters: TLBParameters = TLBParameters( 287 name = "sttlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = false, 293 lgMaxSize = 4 294 ), 295 hytlbParameters: TLBParameters = TLBParameters( 296 name = "hytlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = false, 302 lgMaxSize = 4 303 ), 304 pftlbParameters: TLBParameters = TLBParameters( 305 name = "pftlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = false, 311 lgMaxSize = 4 312 ), 313 l2ToL1tlbParameters: TLBParameters = TLBParameters( 314 name = "l2tlb", 315 NWays = 48, 316 outReplace = false, 317 partialStaticPMP = true, 318 outsideRecvFlush = true, 319 saveLevel = false 320 ), 321 refillBothTlb: Boolean = false, 322 btlbParameters: TLBParameters = TLBParameters( 323 name = "btlb", 324 NWays = 48, 325 ), 326 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 327 NumPerfCounters: Int = 16, 328 icacheParameters: ICacheParameters = ICacheParameters( 329 tagECC = Some("parity"), 330 dataECC = Some("parity"), 331 replacer = Some("setplru"), 332 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 333 ), 334 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 replacer = Some("setplru"), 338 nMissEntries = 16, 339 nProbeEntries = 8, 340 nReleaseEntries = 18, 341 nMaxPrefetchEntry = 6, 342 enableTagEcc = true, 343 enableDataEcc = true, 344 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 345 )), 346 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 347 name = "l2", 348 ways = 8, 349 sets = 1024, // default 512KB L2 350 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 351 coupledL2.prefetch.TPParameters()), 352 )), 353 L2NBanks: Int = 1, 354 usePTWRepeater: Boolean = false, 355 softTLB: Boolean = false, // dpi-c l1tlb debug only 356 softPTW: Boolean = false, // dpi-c l2tlb debug only 357 softPTWDelay: Int = 1, 358 hasMbist: Boolean = false, 359 wfiResume: Boolean = true, 360 hasSramCtl: Boolean = false, 361){ 362 def ISABase = "rv64i" 363 def ISAExtensions = Seq( 364 // single letter extensions, in canonical order 365 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 366 // multi-letter extensions, sorted alphanumerically 367 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 368 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 369 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 370 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 371 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 372 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 373 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 374 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 375 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 376 ) 377 378 def vlWidth = log2Up(VLEN) + 1 379 380 /** 381 * the minimum element length of vector elements 382 */ 383 val minVecElen: Int = 8 384 385 /** 386 * the maximum number of elements in vector register 387 */ 388 val maxElemPerVreg: Int = VLEN / minVecElen 389 390 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 391 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 392 393 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 394 val RegCacheIdxWidth = log2Up(RegCacheSize) 395 396 val intSchdParams = { 397 implicit val schdType: SchedulerType = IntScheduler() 398 SchdBlockParams(Seq( 399 IssueBlockParams(Seq( 400 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 401 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 402 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 403 IssueBlockParams(Seq( 404 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 405 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 406 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 407 IssueBlockParams(Seq( 408 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 409 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 IssueBlockParams(Seq( 412 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 413 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 414 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 415 ), 416 numPregs = intPreg.numEntries, 417 numDeqOutside = 0, 418 schdType = schdType, 419 rfDataWidth = intPreg.dataCfg.dataWidth, 420 ) 421 } 422 423 val fpSchdParams = { 424 implicit val schdType: SchedulerType = FpScheduler() 425 SchdBlockParams(Seq( 426 IssueBlockParams(Seq( 427 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 428 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 429 ), numEntries = 18, numEnq = 2, numComp = 14), 430 IssueBlockParams(Seq( 431 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 432 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 433 ), numEntries = 18, numEnq = 2, numComp = 14), 434 IssueBlockParams(Seq( 435 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 436 ), numEntries = 18, numEnq = 2, numComp = 14), 437 ), 438 numPregs = fpPreg.numEntries, 439 numDeqOutside = 0, 440 schdType = schdType, 441 rfDataWidth = fpPreg.dataCfg.dataWidth, 442 ) 443 } 444 445 val vfSchdParams = { 446 implicit val schdType: SchedulerType = VfScheduler() 447 SchdBlockParams(Seq( 448 IssueBlockParams(Seq( 449 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 450 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 451 ), numEntries = 16, numEnq = 2, numComp = 12), 452 IssueBlockParams(Seq( 453 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 454 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 455 ), numEntries = 16, numEnq = 2, numComp = 12), 456 IssueBlockParams(Seq( 457 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 458 ), numEntries = 10, numEnq = 2, numComp = 6), 459 ), 460 numPregs = vfPreg.numEntries, 461 numDeqOutside = 0, 462 schdType = schdType, 463 rfDataWidth = vfPreg.dataCfg.dataWidth, 464 ) 465 } 466 467 val memSchdParams = { 468 implicit val schdType: SchedulerType = MemScheduler() 469 val rfDataWidth = 64 470 471 SchdBlockParams(Seq( 472 IssueBlockParams(Seq( 473 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 474 ), numEntries = 16, numEnq = 2, numComp = 12), 475 IssueBlockParams(Seq( 476 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 477 ), numEntries = 16, numEnq = 2, numComp = 12), 478 IssueBlockParams(Seq( 479 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 480 ), numEntries = 16, numEnq = 2, numComp = 12), 481 IssueBlockParams(Seq( 482 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 483 ), numEntries = 16, numEnq = 2, numComp = 12), 484 IssueBlockParams(Seq( 485 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 486 ), numEntries = 16, numEnq = 2, numComp = 12), 487 IssueBlockParams(Seq( 488 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 489 ), numEntries = 16, numEnq = 2, numComp = 12), 490 IssueBlockParams(Seq( 491 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 492 ), numEntries = 16, numEnq = 2, numComp = 12), 493 IssueBlockParams(Seq( 494 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 495 ), numEntries = 16, numEnq = 2, numComp = 12), 496 IssueBlockParams(Seq( 497 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 498 ), numEntries = 16, numEnq = 2, numComp = 12), 499 ), 500 numPregs = intPreg.numEntries max vfPreg.numEntries, 501 numDeqOutside = 0, 502 schdType = schdType, 503 rfDataWidth = rfDataWidth, 504 ) 505 } 506 507 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 508 509 def iqWakeUpParams = { 510 Seq( 511 WakeUpConfig( 512 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 513 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 514 ), 515 // TODO: add load -> fp slow wakeup 516 WakeUpConfig( 517 Seq("FEX0", "FEX2", "FEX4") -> 518 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 519 ), 520 ).flatten 521 } 522 523 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 524 525 val backendParams: BackendParams = backend.BackendParams( 526 Map( 527 IntScheduler() -> intSchdParams, 528 FpScheduler() -> fpSchdParams, 529 VfScheduler() -> vfSchdParams, 530 MemScheduler() -> memSchdParams, 531 ), 532 Seq( 533 intPreg, 534 fpPreg, 535 vfPreg, 536 v0Preg, 537 vlPreg, 538 fakeIntPreg 539 ), 540 iqWakeUpParams, 541 ) 542 543 // Parameters for trace extension. 544 // Trace parameters is useful for XSTOP. 545 val traceParams: TraceParams = new TraceParams( 546 TraceGroupNum = 3, 547 IaddrWidth = GPAddrBitsSv48x4, 548 PrivWidth = 3, 549 ItypeWidth = 4, 550 IlastsizeWidth = 1, 551 ) 552} 553 554case object DebugOptionsKey extends Field[DebugOptions] 555 556case class DebugOptions 557( 558 FPGAPlatform: Boolean = false, 559 ResetGen: Boolean = false, 560 EnableDifftest: Boolean = false, 561 AlwaysBasicDiff: Boolean = true, 562 EnableDebug: Boolean = false, 563 EnablePerfDebug: Boolean = true, 564 PerfLevel: String = "VERBOSE", 565 UseDRAMSim: Boolean = false, 566 EnableConstantin: Boolean = false, 567 EnableChiselDB: Boolean = false, 568 AlwaysBasicDB: Boolean = true, 569 EnableRollingDB: Boolean = false 570) 571 572trait HasXSParameter { 573 574 implicit val p: Parameters 575 576 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 577 def PmemRanges = p(SoCParamsKey).PmemRanges 578 def KeyIDBits = p(CVMParamskey).KeyIDBits 579 final val PageOffsetWidth = 12 580 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 581 582 def coreParams = p(XSCoreParamsKey) 583 def env = p(DebugOptionsKey) 584 585 def ISABase = coreParams.ISABase 586 def ISAExtensions = coreParams.ISAExtensions 587 def XLEN = coreParams.XLEN 588 def VLEN = coreParams.VLEN 589 def ELEN = coreParams.ELEN 590 def HSXLEN = coreParams.HSXLEN 591 val minFLen = 32 592 val fLen = 64 593 def hartIdLen = p(MaxHartIdBits) 594 val xLen = XLEN 595 596 def HasBitmapCheck = coreParams.HasBitmapCheck 597 def HasBitmapCheckDefault = coreParams.HasBitmapCheckDefault 598 def HasMExtension = coreParams.HasMExtension 599 def HasCExtension = coreParams.HasCExtension 600 def HasHExtension = coreParams.HasHExtension 601 def EnableSv48 = coreParams.EnableSv48 602 def HasDiv = coreParams.HasDiv 603 def HasIcache = coreParams.HasICache 604 def HasDcache = coreParams.HasDCache 605 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 606 def PAddrBitsMax = coreParams.PAddrBitsMax 607 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 608 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 609 def GPAddrBits = { 610 if (EnableSv48) 611 coreParams.GPAddrBitsSv48x4 612 else 613 coreParams.GPAddrBitsSv39x4 614 } 615 def VAddrBits = { 616 if (HasHExtension) { 617 if (EnableSv48) 618 coreParams.GPAddrBitsSv48x4 619 else 620 coreParams.GPAddrBitsSv39x4 621 } else { 622 if (EnableSv48) 623 coreParams.VAddrBitsSv48 624 else 625 coreParams.VAddrBitsSv39 626 } 627 } // VAddrBits is Virtual Memory addr bits 628 629 def VAddrMaxBits = { 630 if(EnableSv48) { 631 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 632 } else { 633 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 634 } 635 } 636 637 def AsidLength = coreParams.AsidLength 638 def VmidLength = coreParams.VmidLength 639 def ReSelectLen = coreParams.ReSelectLen 640 def AddrBytes = AddrBits / 8 // unused 641 def DataBits = XLEN 642 def DataBytes = DataBits / 8 643 def QuadWordBits = DataBits * 2 644 def QuadWordBytes = QuadWordBits / 8 645 def VDataBytes = VLEN / 8 646 def HasFPU = coreParams.HasFPU 647 def HasVPU = coreParams.HasVPU 648 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 649 def FetchWidth = coreParams.FetchWidth 650 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 651 def EnableBPU = coreParams.EnableBPU 652 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 653 def EnableRAS = coreParams.EnableRAS 654 def EnableLB = coreParams.EnableLB 655 def EnableLoop = coreParams.EnableLoop 656 def EnableSC = coreParams.EnableSC 657 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 658 def HistoryLength = coreParams.HistoryLength 659 def EnableGHistDiff = coreParams.EnableGHistDiff 660 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 661 def EnableClockGate = coreParams.EnableClockGate 662 def UbtbGHRLength = coreParams.UbtbGHRLength 663 def UbtbSize = coreParams.UbtbSize 664 def EnableFauFTB = coreParams.EnableFauFTB 665 def FtbSize = coreParams.FtbSize 666 def FtbWays = coreParams.FtbWays 667 def FtbTagLength = coreParams.FtbTagLength 668 def RasSize = coreParams.RasSize 669 def RasSpecSize = coreParams.RasSpecSize 670 def RasCtrSize = coreParams.RasCtrSize 671 672 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 673 coreParams.branchPredictor(resp_in, p) 674 } 675 def numBr = coreParams.numBr 676 def TageTableInfos = coreParams.TageTableInfos 677 def TageBanks = coreParams.numBr 678 def SCNRows = coreParams.SCNRows 679 def SCCtrBits = coreParams.SCCtrBits 680 def SCHistLens = coreParams.SCHistLens 681 def SCNTables = coreParams.SCNTables 682 683 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 684 case ((n, cb), h) => (n, cb, h) 685 } 686 def ITTageTableInfos = coreParams.ITTageTableInfos 687 type FoldedHistoryInfo = Tuple2[Int, Int] 688 def foldedGHistInfos = 689 (TageTableInfos.map{ case (nRows, h, t) => 690 if (h > 0) 691 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 692 else 693 Set[FoldedHistoryInfo]() 694 }.reduce(_++_).toSet ++ 695 SCTableInfos.map{ case (nRows, _, h) => 696 if (h > 0) 697 Set((h, min(log2Ceil(nRows/TageBanks), h))) 698 else 699 Set[FoldedHistoryInfo]() 700 }.reduce(_++_).toSet ++ 701 ITTageTableInfos.map{ case (nRows, h, t) => 702 if (h > 0) 703 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 704 else 705 Set[FoldedHistoryInfo]() 706 }.reduce(_++_) ++ 707 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 708 ).toList 709 710 711 712 def CacheLineSize = coreParams.CacheLineSize 713 def CacheLineHalfWord = CacheLineSize / 16 714 def ExtHistoryLength = HistoryLength + 64 715 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 716 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 717 def IBufSize = coreParams.IBufSize 718 def IBufNBank = coreParams.IBufNBank 719 def backendParams: BackendParams = coreParams.backendParams 720 def DecodeWidth = coreParams.DecodeWidth 721 def RenameWidth = coreParams.RenameWidth 722 def CommitWidth = coreParams.CommitWidth 723 def RobCommitWidth = coreParams.RobCommitWidth 724 def RabCommitWidth = coreParams.RabCommitWidth 725 def MaxUopSize = coreParams.MaxUopSize 726 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 727 def RenameSnapshotNum = coreParams.RenameSnapshotNum 728 def FtqSize = coreParams.FtqSize 729 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 730 def IntLogicRegs = coreParams.IntLogicRegs 731 def FpLogicRegs = coreParams.FpLogicRegs 732 def VecLogicRegs = coreParams.VecLogicRegs 733 def V0LogicRegs = coreParams.V0LogicRegs 734 def VlLogicRegs = coreParams.VlLogicRegs 735 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 736 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 737 def V0_IDX = coreParams.V0_IDX 738 def Vl_IDX = coreParams.Vl_IDX 739 def IntPhyRegs = coreParams.intPreg.numEntries 740 def FpPhyRegs = coreParams.fpPreg.numEntries 741 def VfPhyRegs = coreParams.vfPreg.numEntries 742 def V0PhyRegs = coreParams.v0Preg.numEntries 743 def VlPhyRegs = coreParams.vlPreg.numEntries 744 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 745 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 746 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 747 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 748 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 749 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 750 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 751 def RobSize = coreParams.RobSize 752 def RabSize = coreParams.RabSize 753 def VTypeBufferSize = coreParams.VTypeBufferSize 754 def IntRegCacheSize = coreParams.IntRegCacheSize 755 def MemRegCacheSize = coreParams.MemRegCacheSize 756 def RegCacheSize = coreParams.RegCacheSize 757 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 758 /** 759 * the minimum element length of vector elements 760 */ 761 def minVecElen: Int = coreParams.minVecElen 762 763 /** 764 * the maximum number of elements in vector register 765 */ 766 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 767 768 def IntRefCounterWidth = log2Ceil(RobSize) 769 def LSQEnqWidth = RenameWidth 770 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 771 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 772 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 773 def LoadQueueRARSize = coreParams.LoadQueueRARSize 774 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 775 def RollbackGroupSize = coreParams.RollbackGroupSize 776 val RAWlgSelectGroupSize = log2Ceil(RollbackGroupSize) 777 val RAWTotalDelayCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / RAWlgSelectGroupSize).toInt + 1 - 2 778 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 779 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 780 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 781 def StoreQueueSize = coreParams.StoreQueueSize 782 def StoreQueueForceWriteSbufferUpper = coreParams.StoreQueueSize - 4 783 def StoreQueueForceWriteSbufferLower = StoreQueueForceWriteSbufferUpper - 5 784 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 785 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 786 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 787 def VlsQueueSize = coreParams.VlsQueueSize 788 789 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 790 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 791 792 def NumRedirect = backendParams.numRedirect 793 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 794 def FtqRedirectAheadNum = NumRedirect 795 def IfuRedirectNum = coreParams.IfuRedirectNum 796 def LoadPipelineWidth = coreParams.LoadPipelineWidth 797 def StorePipelineWidth = coreParams.StorePipelineWidth 798 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 799 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 800 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 801 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 802 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 803 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 804 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 805 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 806 def StoreBufferSize = coreParams.StoreBufferSize 807 def StoreBufferThreshold = coreParams.StoreBufferThreshold 808 def EnsbufferWidth = coreParams.EnsbufferWidth 809 def LoadDependencyWidth = coreParams.LoadDependencyWidth 810 def VlMergeBufferSize = coreParams.VlMergeBufferSize 811 def VsMergeBufferSize = coreParams.VsMergeBufferSize 812 def UopWritebackWidth = coreParams.UopWritebackWidth 813 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 814 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 815 def VSegmentBufferSize = coreParams.VSegmentBufferSize 816 def VFOFBufferSize = coreParams.VFOFBufferSize 817 def UncacheBufferSize = coreParams.UncacheBufferSize 818 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 819 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 820 def EnableFastForward = coreParams.EnableFastForward 821 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 822 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 823 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 824 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 825 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 826 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 827 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 828 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 829 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 830 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 831 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 832 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 833 def HasCMO = coreParams.HasCMO && p(EnableCHI) 834 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 835 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 836 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 837 def asidLen = coreParams.MMUAsidLen 838 def vmidLen = coreParams.MMUVmidLen 839 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 840 def refillBothTlb = coreParams.refillBothTlb 841 def iwpuParam = coreParams.iwpuParameters 842 def dwpuParam = coreParams.dwpuParameters 843 def itlbParams = coreParams.itlbParameters 844 def ldtlbParams = coreParams.ldtlbParameters 845 def sttlbParams = coreParams.sttlbParameters 846 def hytlbParams = coreParams.hytlbParameters 847 def pftlbParams = coreParams.pftlbParameters 848 def l2ToL1Params = coreParams.l2ToL1tlbParameters 849 def btlbParams = coreParams.btlbParameters 850 def l2tlbParams = coreParams.l2tlbParameters 851 def NumPerfCounters = coreParams.NumPerfCounters 852 853 def instBytes = if (HasCExtension) 2 else 4 854 def instOffsetBits = log2Ceil(instBytes) 855 856 def icacheParameters = coreParams.icacheParameters 857 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 858 859 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 860 // for constrained LR/SC loop 861 def LRSCCycles = 64 862 // for lr storm 863 def LRSCBackOff = 8 864 865 // cache hierarchy configurations 866 def l1BusDataWidth = 256 867 868 // load violation predict 869 def ResetTimeMax2Pow = 20 //1078576 870 def ResetTimeMin2Pow = 10 //1024 871 // wait table parameters 872 def WaitTableSize = 1024 873 def MemPredPCWidth = log2Up(WaitTableSize) 874 def LWTUse2BitCounter = true 875 // store set parameters 876 def SSITSize = WaitTableSize 877 def LFSTSize = 32 878 def SSIDWidth = log2Up(LFSTSize) 879 def LFSTWidth = 4 880 def StoreSetEnable = true // LWT will be disabled if SS is enabled 881 def LFSTEnable = true 882 883 def PCntIncrStep: Int = 6 884 def numPCntHc: Int = 12 885 def numPCntPtw: Int = 19 886 887 def numCSRPCntFrontend = 8 888 def numCSRPCntCtrl = 8 889 def numCSRPCntLsu = 8 890 def numCSRPCntHc = 5 891 def printEventCoding = true 892 def printCriticalError = false 893 def maxCommitStuck = pow(2, 21).toInt 894 895 // Vector load exception 896 def maxMergeNumPerCycle = 4 897 898 // Parameters for Sdtrig extension 899 protected def TriggerNum = 4 900 protected def TriggerChainMaxLength = 2 901 902 // Parameters for Trace extension 903 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 904 def CauseWidth = XLEN 905 def TvalWidth = coreParams.traceParams.IaddrWidth 906 def PrivWidth = coreParams.traceParams.PrivWidth 907 def IaddrWidth = coreParams.traceParams.IaddrWidth 908 def ItypeWidth = coreParams.traceParams.ItypeWidth 909 def IretireWidthInPipe = log2Up(RenameWidth * 2 + 1) 910 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2 + 1) 911 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 912 913 def hasMbist = coreParams.hasMbist 914 915 def wfiResume = coreParams.wfiResume 916 def hasSramCtl = coreParams.hasSramCtl 917 def hasDFT = hasMbist || hasSramCtl 918} 919