1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.WbArbiterParams 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.exu.ExeUnitParams 27import xiangshan.backend.fu.{FuConfig, FuType} 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30 31case class BackendParams( 32 schdParams : Map[SchedulerType, SchdBlockParams], 33 pregParams : Seq[PregParams], 34) { 35 def intSchdParams = schdParams.get(IntScheduler()) 36 def vfSchdParams = schdParams.get(VfScheduler()) 37 def memSchdParams = schdParams.get(MemScheduler()) 38 def allSchdParams: Seq[SchdBlockParams] = 39 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 40 .filter(_.nonEmpty) 41 .map(_.get) 42 def allIssueParams: Seq[IssueBlockParams] = 43 allSchdParams.map(_.issueBlockParams).flatten 44 def allExuParams: Seq[ExeUnitParams] = 45 allIssueParams.map(_.exuBlockParams).flatten 46 47 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 48 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 49 50 def AluCnt = allSchdParams.map(_.AluCnt).sum 51 def StaCnt = allSchdParams.map(_.StaCnt).sum 52 def StdCnt = allSchdParams.map(_.StdCnt).sum 53 def LduCnt = allSchdParams.map(_.LduCnt).sum 54 def LsExuCnt = StaCnt + LduCnt 55 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 56 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 57 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 58 59 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 60 61 def numIntWb = intPregParams.numWrite 62 def numVfWb = vfPregParams.numWrite 63 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 64 def numExu = allSchdParams.map(_.numExu).sum 65 def numRfRead = 14 66 def numRfWrite = 8 67 68 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 69 70 def numRedirect = allSchdParams.map(_.numRedirect).sum 71 72 def genIntWriteBackBundle(implicit p: Parameters) = { 73 // Todo: limit write port 74 Seq.tabulate(numIntWb)(x => new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 75 } 76 77 def genVfWriteBackBundle(implicit p: Parameters) = { 78 // Todo: limit write port 79 Seq.tabulate(numVfWb)(x => new RfWritePortWithConfig(VecData(), intPregParams.addrWidth)) 80 } 81 82 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 83 genIntWriteBackBundle ++ genVfWriteBackBundle 84 } 85 86 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 87 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).reduce(_ ++ _)) 88 } 89 90 def getIntWbArbiterParams: WbArbiterParams = { 91 val intWbCfgs: Seq[WbConfig] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)) 92 datapath.WbArbiterParams(intWbCfgs, intPregParams) 93 } 94 95 def getVfWbArbiterParams: WbArbiterParams = { 96 val vfWbCfgs = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)) 97 datapath.WbArbiterParams(vfWbCfgs, vfPregParams) 98 } 99} 100 101 102 103 104