1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.brq.{Brq, BrqPcRead} 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24} 25 26class CtrlToFpBlockIO extends XSBundle { 27 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 28 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 29 // fp block uses port 0~11 30 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 31 val redirect = ValidIO(new Redirect) 32} 33 34class CtrlToLsBlockIO extends XSBundle { 35 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 36 val enqLsq = Flipped(new LsqEnqIO) 37 val redirect = ValidIO(new Redirect) 38} 39 40class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 41 val io = IO(new Bundle { 42 val frontend = Flipped(new FrontendToBackendIO) 43 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 44 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 45 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 46 val toIntBlock = new CtrlToIntBlockIO 47 val toFpBlock = new CtrlToFpBlockIO 48 val toLsBlock = new CtrlToLsBlockIO 49 val roqio = new Bundle { 50 // to int block 51 val toCSR = new RoqCSRIO 52 val exception = ValidIO(new MicroOp) 53 val isInterrupt = Output(Bool()) 54 // to mem block 55 val commits = new RoqCommitIO 56 val roqDeqPtr = Output(new RoqPtr) 57 } 58 }) 59 60 val difftestIO = IO(new Bundle() { 61 val fromRoq = new Bundle() { 62 val commit = Output(UInt(32.W)) 63 val thisPC = Output(UInt(XLEN.W)) 64 val thisINST = Output(UInt(32.W)) 65 val skip = Output(UInt(32.W)) 66 val wen = Output(UInt(32.W)) 67 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 68 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 69 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 70 val isRVC = Output(UInt(32.W)) 71 val scFailed = Output(Bool()) 72 val lpaddr = Output(Vec(CommitWidth, UInt(64.W))) 73 val ltype = Output(Vec(CommitWidth, UInt(32.W))) 74 val lfu = Output(Vec(CommitWidth, UInt(4.W))) 75 } 76 }) 77 difftestIO <> DontCare 78 79 val decode = Module(new DecodeStage) 80 val brq = Module(new Brq) 81 val rename = Module(new Rename) 82 val dispatch = Module(new Dispatch) 83 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 84 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 85 86 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 87 88 val roq = Module(new Roq(roqWbSize)) 89 90 // When replay and mis-prediction have the same roqIdx, 91 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 92 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 93 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 94 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 95 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 96 val redirectValid = roq.io.redirectOut.valid || brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 97 val redirect = Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits, redirectArb) 98 99 io.frontend.redirect.valid := RegNext(redirectValid) 100 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits.target, redirectArb.target)) 101 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 102 103 decode.io.in <> io.frontend.cfVec 104 decode.io.enqBrq <> brq.io.enq 105 106 brq.io.redirect.valid <> redirectValid 107 brq.io.redirect.bits <> redirect 108 brq.io.bcommit <> roq.io.bcommit 109 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 110 brq.io.pcReadReq.brqIdx := dispatch.io.enqIQCtrl(0).bits.brTag // jump 111 io.toIntBlock.jumpPc := brq.io.pcReadReq.pc 112 113 // pipeline between decode and dispatch 114 val lastCycleRedirect = RegNext(redirectValid) 115 for (i <- 0 until RenameWidth) { 116 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 117 } 118 119 rename.io.redirect.valid <> redirectValid 120 rename.io.redirect.bits <> redirect 121 rename.io.roqCommits <> roq.io.commits 122 rename.io.out <> dispatch.io.fromRename 123 rename.io.renameBypass <> dispatch.io.renameBypass 124 125 dispatch.io.redirect.valid <> redirectValid 126 dispatch.io.redirect.bits <> redirect 127 dispatch.io.enqRoq <> roq.io.enq 128 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 129 dispatch.io.readIntRf <> io.toIntBlock.readRf 130 dispatch.io.readFpRf <> io.toFpBlock.readRf 131 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 132 intBusyTable.io.allocPregs(i).valid := preg.isInt 133 fpBusyTable.io.allocPregs(i).valid := preg.isFp 134 intBusyTable.io.allocPregs(i).bits := preg.preg 135 fpBusyTable.io.allocPregs(i).bits := preg.preg 136 } 137 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 138 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 139// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 140 141 142 val flush = redirectValid && RedirectLevel.isUnconditional(redirect.level) 143 fpBusyTable.io.flush := flush 144 intBusyTable.io.flush := flush 145 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 146 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 147 setPhyRegRdy.bits := wb.bits.uop.pdest 148 } 149 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 150 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 151 setPhyRegRdy.bits := wb.bits.uop.pdest 152 } 153 intBusyTable.io.read <> dispatch.io.readIntState 154 fpBusyTable.io.read <> dispatch.io.readFpState 155 156 roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 157 roq.io.redirect.bits <> redirectArb 158 roq.io.exeWbResults.take(roqWbSize-1).zip( 159 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 160 ).foreach{ 161 case(x, y) => 162 x.bits := y.bits 163 x.valid := y.valid && !y.bits.redirectValid 164 } 165 roq.io.exeWbResults.last := brq.io.out 166 167 if (env.DualCoreDifftest) { 168 difftestIO.fromRoq <> roq.difftestIO 169 } 170 171 io.toIntBlock.redirect.valid := redirectValid 172 io.toIntBlock.redirect.bits := redirect 173 io.toFpBlock.redirect.valid := redirectValid 174 io.toFpBlock.redirect.bits := redirect 175 io.toLsBlock.redirect.valid := redirectValid 176 io.toLsBlock.redirect.bits := redirect 177 178 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 179 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 180 181 // roq to int block 182 io.roqio.toCSR <> roq.io.csr 183 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 184 io.roqio.exception.bits := roq.io.exception 185 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 186 // roq to mem block 187 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 188 io.roqio.commits := roq.io.commits 189} 190