1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25} 26 27class CtrlToFpBlockIO extends XSBundle { 28 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 29 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 30 // fp block uses port 0~11 31 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 32 val redirect = ValidIO(new Redirect) 33} 34 35class CtrlToLsBlockIO extends XSBundle { 36 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 37 val enqLsq = Flipped(new LsqEnqIO) 38 val redirect = ValidIO(new Redirect) 39} 40 41class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle() { 43 val loadRelay = Flipped(ValidIO(new Redirect)) 44 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 45 val roqRedirect = Flipped(ValidIO(new Redirect)) 46 val stage2FtqRead = new FtqRead 47 val stage2Redirect = ValidIO(new Redirect) 48 val stage3Redirect = ValidIO(new Redirect) 49 }) 50 /* 51 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 52 | | | | | | | 53 |============= reg & compare =====| | ======== 54 | | 55 | | 56 | | Stage2 57 | | 58 redirect (flush backend) | 59 | | 60 === reg === | ======== 61 | | 62 |----- mux (exception first) -----| Stage3 63 | 64 redirect (send to frontend) 65 */ 66 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 67 Mux(x.valid, 68 Mux(y.valid, 69 Mux(isAfter(x.bits.roqIdx, y.bits.roqIdx), y, x), 70 x 71 ), 72 y 73 ) 74 } 75 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 76 Mux(x.valid, 77 Mux(y.valid, 78 Mux(isAfter(x.bits.redirect.roqIdx, y.bits.redirect.roqIdx), y, x), 79 x 80 ), 81 y 82 ) 83 } 84 val jumpOut = io.exuMispredict.head 85 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 86 val oldestExuOut = selectOlderExuOut(oldestAluOut, jumpOut) // select between jump and alu 87 88 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 89 val redirect = Wire(Valid(new Redirect)) 90 redirect.valid := oldestExuOut.valid 91 redirect.bits := oldestExuOut.bits.redirect 92 redirect 93 }) 94 95 val s1_isJump = RegNext(jumpOut.valid && !oldestAluOut.valid, init = false.B) 96 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 97 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 98 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 99 val s1_redirect_bits_reg = Reg(new Redirect) 100 val s1_redirect_valid_reg = RegInit(false.B) 101 102 // stage1 -> stage2 103 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect)){ 104 s1_redirect_bits_reg := oldestMispredict.bits 105 s1_redirect_valid_reg := true.B 106 }.otherwise({ 107 s1_redirect_valid_reg := false.B 108 }) 109 io.stage2Redirect.valid := s1_redirect_valid_reg 110 io.stage2Redirect.bits := s1_redirect_bits_reg 111 io.stage2Redirect.bits.cfiUpdate := DontCare 112 // at stage2, we read ftq to get pc 113 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 114 115 // stage3, calculate redirect target 116 val s2_isJump = RegNext(s1_isJump) 117 val s2_jumpTarget = RegEnable(s1_jumpTarget, s1_redirect_valid_reg) 118 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 119 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 120 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 121 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg, init = false.B) 122 123 val ftqRead = io.stage2FtqRead.entry 124 val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset) 125 val brTarget = pc + SignExt(s2_imm12_reg, XLEN) 126 val snpc = pc + Mux(s2_pd.isRVC, 2.U, 4.U) 127 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 128 val target = Mux(isReplay, 129 pc, // repaly from itself 130 Mux(s2_redirect_bits_reg.cfiUpdate.taken, 131 Mux(s2_isJump, s2_jumpTarget, brTarget), 132 snpc 133 ) 134 ) 135 io.stage3Redirect.valid := s2_redirect_valid_reg 136 io.stage3Redirect.bits := s2_redirect_bits_reg 137 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 138 stage3CfiUpdate.pc := pc 139 stage3CfiUpdate.pd := s2_pd 140 stage3CfiUpdate.rasSp := ftqRead.rasSp 141 stage3CfiUpdate.rasEntry := ftqRead.rasTop 142 stage3CfiUpdate.hist := ftqRead.hist 143 stage3CfiUpdate.predHist := ftqRead.predHist 144 stage3CfiUpdate.specCnt := ftqRead.specCnt(s2_redirect_bits_reg.ftqOffset) 145 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 146 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 147 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 148 })(s2_redirect_bits_reg.ftqOffset) 149 stage3CfiUpdate.target := target 150 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 151 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 152} 153 154class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 155 val io = IO(new Bundle { 156 val frontend = Flipped(new FrontendToBackendIO) 157 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 158 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 159 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 160 val toIntBlock = new CtrlToIntBlockIO 161 val toFpBlock = new CtrlToFpBlockIO 162 val toLsBlock = new CtrlToLsBlockIO 163 val roqio = new Bundle { 164 // to int block 165 val toCSR = new RoqCSRIO 166 val exception = ValidIO(new MicroOp) 167 val isInterrupt = Output(Bool()) 168 // to mem block 169 val commits = new RoqCommitIO 170 val roqDeqPtr = Output(new RoqPtr) 171 } 172 }) 173 174 val ftq = Module(new Ftq) 175 val decode = Module(new DecodeStage) 176 val rename = Module(new Rename) 177 val dispatch = Module(new Dispatch) 178 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 179 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 180 val redirectGen = Module(new RedirectGenerator) 181 182 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 183 184 val roq = Module(new Roq(roqWbSize)) 185 186 val backendRedirect = redirectGen.io.stage2Redirect 187 val frontendRedirect = redirectGen.io.stage3Redirect 188 189 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 190 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 191 x.bits := y.bits 192 }) 193 redirectGen.io.loadRelay := io.fromLsBlock.replay 194 redirectGen.io.roqRedirect := roq.io.redirectOut 195 196 ftq.io.enq <> io.frontend.fetchInfo 197 for(i <- 0 until CommitWidth){ 198 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 199 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 200 } 201 ftq.io.redirect <> backendRedirect 202 ftq.io.frontendRedirect <> frontendRedirect 203 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 204 205 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 206 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 207 208 io.frontend.redirect_cfiUpdate := frontendRedirect 209 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 210 io.frontend.ftqEnqPtr := ftq.io.enqPtr 211 io.frontend.ftqLeftOne := ftq.io.leftOne 212 213 decode.io.in <> io.frontend.cfVec 214 215 val jumpInst = dispatch.io.enqIQCtrl(0).bits 216 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 217 ftqOffsetReg := jumpInst.cf.ftqOffset 218 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 219 io.toIntBlock.jumpPc := GetPcByFtq(ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg) 220 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 221 222 // pipeline between decode and dispatch 223 for (i <- 0 until RenameWidth) { 224 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 225 backendRedirect.valid || frontendRedirect.valid) 226 } 227 228 rename.io.redirect <> backendRedirect 229 rename.io.roqCommits <> roq.io.commits 230 rename.io.out <> dispatch.io.fromRename 231 rename.io.renameBypass <> dispatch.io.renameBypass 232 233 dispatch.io.redirect <> backendRedirect 234 dispatch.io.enqRoq <> roq.io.enq 235 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 236 dispatch.io.readIntRf <> io.toIntBlock.readRf 237 dispatch.io.readFpRf <> io.toFpBlock.readRf 238 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 239 intBusyTable.io.allocPregs(i).valid := preg.isInt 240 fpBusyTable.io.allocPregs(i).valid := preg.isFp 241 intBusyTable.io.allocPregs(i).bits := preg.preg 242 fpBusyTable.io.allocPregs(i).bits := preg.preg 243 } 244 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 245 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 246// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 247 248 249 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 250 fpBusyTable.io.flush := flush 251 intBusyTable.io.flush := flush 252 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 253 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 254 setPhyRegRdy.bits := wb.bits.uop.pdest 255 } 256 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 257 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 258 setPhyRegRdy.bits := wb.bits.uop.pdest 259 } 260 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 261 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 262 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 263 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 264 265 roq.io.redirect <> backendRedirect 266 roq.io.exeWbResults.zip( 267 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 268 ).foreach{ 269 case(x, y) => 270 x.bits := y.bits 271 x.valid := y.valid 272 } 273 274 // TODO: is 'backendRedirect' necesscary? 275 io.toIntBlock.redirect <> backendRedirect 276 io.toFpBlock.redirect <> backendRedirect 277 io.toLsBlock.redirect <> backendRedirect 278 279 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 280 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 281 282 // roq to int block 283 io.roqio.toCSR <> roq.io.csr 284 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 285 io.roqio.exception.bits := roq.io.exception 286 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 287 // roq to mem block 288 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 289 io.roqio.commits := roq.io.commits 290} 291