1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21 val redirect = ValidIO(new Redirect) 22 val roqToCSR = new RoqCSRIO 23} 24 25class CtrlToFpBlockIO extends XSBundle { 26 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 27 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 28 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 29 val redirect = ValidIO(new Redirect) 30} 31 32class CtrlToLsBlockIO extends XSBundle { 33 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 34 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 35 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 36 val redirect = ValidIO(new Redirect) 37 // from roq: send commits info to lsq 38 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 39 // from roq: the newest roqDeqPtr 40 val roqDeqPtr = Input(new RoqPtr) 41} 42 43class CtrlBlock 44( 45 jmpCfg: ExuConfig, 46 aluCfg: ExuConfig, 47 mduCfg: ExuConfig, 48 fmacCfg: ExuConfig, 49 fmiscCfg: ExuConfig, 50 ldCfg: ExuConfig, 51 stCfg: ExuConfig 52) extends XSModule { 53 val io = IO(new Bundle { 54 val frontend = Flipped(new FrontendToBackendIO) 55 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 56 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 57 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 58 val toIntBlock = new CtrlToIntBlockIO 59 val toFpBlock = new CtrlToFpBlockIO 60 val toLsBlock = new CtrlToLsBlockIO 61 }) 62 63 val decode = Module(new DecodeStage) 64 val brq = Module(new Brq) 65 val decBuf = Module(new DecodeBuffer) 66 val rename = Module(new Rename) 67 val dispatch = Module(new Dispatch( 68 jmpCfg, aluCfg, mduCfg, 69 fmacCfg, fmiscCfg, 70 ldCfg, stCfg 71 )) 72 // TODO: move busyTable to dispatch1 73 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 74 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 75 val roq = Module(new Roq) 76 77 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 78 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 79 80 val redirect = Mux( 81 roq.io.redirect.valid, 82 roq.io.redirect, 83 Mux( 84 brq.io.redirect.valid, 85 brq.io.redirect, 86 io.fromLsBlock.replay 87 ) 88 ) 89 90 io.frontend.redirect := redirect 91 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 92 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 93 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 94 io.frontend.sfence <> io.fromIntBlock.sfence 95 io.frontend.tlbCsrIO <> io.fromIntBlock.tlbCsrIO 96 97 decode.io.in <> io.frontend.cfVec 98 decode.io.toBrq <> brq.io.enqReqs 99 decode.io.brTags <> brq.io.brTags 100 decode.io.out <> decBuf.io.in 101 102 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 103 decBuf.io.redirect <> redirect 104 decBuf.io.out <> rename.io.in 105 106 rename.io.redirect <> redirect 107 rename.io.roqCommits <> roq.io.commits 108 // they should be moved to busytables 109 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 110 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 111 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 112 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 113 rename.io.intPregRdy <> dispatch.io.intPregRdy 114 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 115 rename.io.replayPregReq <> dispatch.io.replayPregReq 116 rename.io.out <> dispatch.io.fromRename 117 118 dispatch.io.redirect <> redirect 119 dispatch.io.toRoq <> roq.io.dp1Req 120 dispatch.io.roqIdxs <> roq.io.roqIdxs 121 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 122 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 123 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 124 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 125 dispatch.io.readIntRf <> io.toIntBlock.readRf 126 dispatch.io.readFpRf <> io.toFpBlock.readRf 127 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 128 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 129 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 130 131 io.toIntBlock.roqToCSR <> roq.io.csr 132 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 133 // fpBusyTable.flush := flush 134 // intBusyTable.flush := flush 135 // busytable io 136 // maybe update busytable in dispatch1? 137 138} 139