1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.brq.{Brq, BrqPcRead} 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr, RoqExceptionInfo} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24 val flush = Output(Bool()) 25} 26 27class CtrlToFpBlockIO extends XSBundle { 28 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 29 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 30 // fp block uses port 0~11 31 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 32 val redirect = ValidIO(new Redirect) 33 val flush = Output(Bool()) 34} 35 36class CtrlToLsBlockIO extends XSBundle { 37 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 38 val enqLsq = Flipped(new LsqEnqIO) 39 val redirect = ValidIO(new Redirect) 40 val flush = Output(Bool()) 41} 42 43class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 44 val io = IO(new Bundle { 45 val frontend = Flipped(new FrontendToBackendIO) 46 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 47 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 48 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 49 val toIntBlock = new CtrlToIntBlockIO 50 val toFpBlock = new CtrlToFpBlockIO 51 val toLsBlock = new CtrlToLsBlockIO 52 val roqio = new Bundle { 53 // to int block 54 val toCSR = new RoqCSRIO 55 val exception = ValidIO(new RoqExceptionInfo) 56 // to mem block 57 val lsq = new RoqLsqIO 58 } 59 }) 60 61 val difftestIO = IO(new Bundle() { 62 val fromRoq = new Bundle() { 63 val commit = Output(UInt(32.W)) 64 val thisPC = Output(UInt(XLEN.W)) 65 val thisINST = Output(UInt(32.W)) 66 val skip = Output(UInt(32.W)) 67 val wen = Output(UInt(32.W)) 68 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 69 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 70 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 71 val isRVC = Output(UInt(32.W)) 72 val scFailed = Output(Bool()) 73 } 74 }) 75 difftestIO <> DontCare 76 77 val decode = Module(new DecodeStage) 78 val brq = Module(new Brq) 79 val rename = Module(new Rename) 80 val dispatch = Module(new Dispatch) 81 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 82 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 83 84 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 85 86 val roq = Module(new Roq(roqWbSize)) 87 88 // When replay and mis-prediction have the same roqIdx, 89 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 90 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 91 val redirect = Wire(Valid(new Redirect)) 92 val flush = roq.io.flushOut.valid 93 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 94 redirect.bits := Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 95 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 96 redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 97 98 io.frontend.redirect.valid := RegNext(redirect.valid || roq.io.flushOut.valid) 99 io.frontend.redirect.bits := RegNext(Mux(roq.io.flushOut.valid, roq.io.flushOut.bits, redirect.bits.target)) 100 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 101 102 decode.io.in <> io.frontend.cfVec 103 decode.io.enqBrq <> brq.io.enq 104 105 brq.io.redirect <> redirect 106 brq.io.flush <> flush 107 brq.io.bcommit <> roq.io.bcommit 108 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 109 brq.io.pcReadReq.brqIdx := dispatch.io.enqIQCtrl(0).bits.brTag // jump 110 io.toIntBlock.jumpPc := brq.io.pcReadReq.pc 111 112 // pipeline between decode and dispatch 113 val lastCycleRedirect = RegNext(redirect.valid || roq.io.flushOut.valid) 114 for (i <- 0 until RenameWidth) { 115 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirect.valid || flush || lastCycleRedirect) 116 } 117 118 rename.io.redirect <> redirect 119 rename.io.flush := flush 120 rename.io.roqCommits <> roq.io.commits 121 rename.io.out <> dispatch.io.fromRename 122 rename.io.renameBypass <> dispatch.io.renameBypass 123 124 dispatch.io.redirect <> redirect 125 dispatch.io.flush := flush 126 dispatch.io.enqRoq <> roq.io.enq 127 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 128 dispatch.io.readIntRf <> io.toIntBlock.readRf 129 dispatch.io.readFpRf <> io.toFpBlock.readRf 130 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 131 intBusyTable.io.allocPregs(i).valid := preg.isInt 132 fpBusyTable.io.allocPregs(i).valid := preg.isFp 133 intBusyTable.io.allocPregs(i).bits := preg.preg 134 fpBusyTable.io.allocPregs(i).bits := preg.preg 135 } 136 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 137 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 138// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 139 140 141 fpBusyTable.io.flush := flush 142 intBusyTable.io.flush := flush 143 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 144 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 145 setPhyRegRdy.bits := wb.bits.uop.pdest 146 } 147 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 148 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 149 setPhyRegRdy.bits := wb.bits.uop.pdest 150 } 151 intBusyTable.io.read <> dispatch.io.readIntState 152 fpBusyTable.io.read <> dispatch.io.readFpState 153 154 roq.io.redirect <> redirect 155 roq.io.exeWbResults.take(roqWbSize-1).zip( 156 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 157 ).foreach{ 158 case(x, y) => 159 x.bits := y.bits 160 x.valid := y.valid && !y.bits.redirectValid 161 } 162 roq.io.exeWbResults.last := brq.io.out 163 164 if (env.DualCoreDifftest) { 165 difftestIO.fromRoq <> roq.difftestIO 166 } 167 168 io.toIntBlock.redirect <> redirect 169 io.toIntBlock.flush <> flush 170 io.toFpBlock.redirect <> redirect 171 io.toFpBlock.flush <> flush 172 io.toLsBlock.redirect <> redirect 173 io.toLsBlock.flush <> flush 174 175 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 176 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 177 178 // roq to int block 179 io.roqio.toCSR <> roq.io.csr 180 io.roqio.exception := roq.io.exception 181 // roq to mem block 182 io.roqio.lsq <> roq.io.lsq 183} 184