1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25} 26 27class CtrlToFpBlockIO extends XSBundle { 28 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 29 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 30 // fp block uses port 0~11 31 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 32 val redirect = ValidIO(new Redirect) 33} 34 35class CtrlToLsBlockIO extends XSBundle { 36 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 37 val enqLsq = Flipped(new LsqEnqIO) 38 val redirect = ValidIO(new Redirect) 39} 40 41class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle() { 43 val loadRelay = Flipped(ValidIO(new Redirect)) 44 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 45 val roqRedirect = Flipped(ValidIO(new Redirect)) 46 val stage2FtqRead = new FtqRead 47 val stage2Redirect = ValidIO(new Redirect) 48 val stage3Redirect = ValidIO(new Redirect) 49 }) 50 /* 51 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 52 | | | | | | | 53 |============= reg & compare =====| | ======== 54 | | 55 | | 56 | | Stage2 57 | | 58 redirect (flush backend) | 59 | | 60 === reg === | ======== 61 | | 62 |----- mux (exception first) -----| Stage3 63 | 64 redirect (send to frontend) 65 */ 66 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 67 Mux(x.valid, 68 Mux(y.valid, 69 Mux(isAfter(x.bits.roqIdx, y.bits.roqIdx), y, x), 70 x 71 ), 72 y 73 ) 74 } 75 def selectOlderExuOutWithFlag(x: Valid[ExuOutput], y: Valid[ExuOutput]): (Valid[ExuOutput], Bool) = { 76 val yIsOlder = Mux(x.valid, 77 Mux(y.valid, 78 Mux(isAfter(x.bits.redirect.roqIdx, y.bits.redirect.roqIdx), true.B, false.B), 79 false.B 80 ), 81 true.B 82 ) 83 val sel = Mux(yIsOlder, y, x) 84 (sel, yIsOlder) 85 } 86 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 87 selectOlderExuOutWithFlag(x, y)._1 88 } 89 val jumpOut = io.exuMispredict.head 90 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 91 val (oldestExuOut, jumpIsOlder) = selectOlderExuOutWithFlag(oldestAluOut, jumpOut) // select between jump and alu 92 93 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 94 val redirect = Wire(Valid(new Redirect)) 95 redirect.valid := oldestExuOut.valid 96 redirect.bits := oldestExuOut.bits.redirect 97 redirect 98 }) 99 100 val s1_isJump = RegNext(jumpIsOlder, init = false.B) 101 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 102 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 103 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 104 val s1_redirect_bits_reg = Reg(new Redirect) 105 val s1_redirect_valid_reg = RegInit(false.B) 106 107 // stage1 -> stage2 108 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect)){ 109 s1_redirect_bits_reg := oldestMispredict.bits 110 s1_redirect_valid_reg := true.B 111 }.otherwise({ 112 s1_redirect_valid_reg := false.B 113 }) 114 io.stage2Redirect.valid := s1_redirect_valid_reg 115 io.stage2Redirect.bits := s1_redirect_bits_reg 116 io.stage2Redirect.bits.cfiUpdate := DontCare 117 // at stage2, we read ftq to get pc 118 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 119 120 // stage3, calculate redirect target 121 val s2_isJump = RegNext(s1_isJump) 122 val s2_jumpTarget = RegEnable(s1_jumpTarget, s1_redirect_valid_reg) 123 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 124 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 125 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 126 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg, init = false.B) 127 128 val ftqRead = io.stage2FtqRead.entry 129 val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset, ftqRead.hasLastPrev) 130 val brTarget = pc + SignExt(ImmUnion.B.toImm32(s2_imm12_reg), XLEN) 131 val snpc = pc + Mux(s2_pd.isRVC, 2.U, 4.U) 132 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 133 val target = Mux(isReplay, 134 pc, // repaly from itself 135 Mux(s2_redirect_bits_reg.cfiUpdate.taken, 136 Mux(s2_isJump, s2_jumpTarget, brTarget), 137 snpc 138 ) 139 ) 140 io.stage3Redirect.valid := s2_redirect_valid_reg 141 io.stage3Redirect.bits := s2_redirect_bits_reg 142 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 143 stage3CfiUpdate.pc := pc 144 stage3CfiUpdate.pd := s2_pd 145 stage3CfiUpdate.rasSp := ftqRead.rasSp 146 stage3CfiUpdate.rasEntry := ftqRead.rasTop 147 stage3CfiUpdate.hist := ftqRead.hist 148 stage3CfiUpdate.predHist := ftqRead.predHist 149 stage3CfiUpdate.specCnt := ftqRead.specCnt(s2_redirect_bits_reg.ftqOffset) 150 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 151 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 152 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 153 })(s2_redirect_bits_reg.ftqOffset) 154 stage3CfiUpdate.target := target 155 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 156 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 157} 158 159class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 160 val io = IO(new Bundle { 161 val frontend = Flipped(new FrontendToBackendIO) 162 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 163 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 164 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 165 val toIntBlock = new CtrlToIntBlockIO 166 val toFpBlock = new CtrlToFpBlockIO 167 val toLsBlock = new CtrlToLsBlockIO 168 val roqio = new Bundle { 169 // to int block 170 val toCSR = new RoqCSRIO 171 val exception = ValidIO(new MicroOp) 172 val isInterrupt = Output(Bool()) 173 // to mem block 174 val commits = new RoqCommitIO 175 val roqDeqPtr = Output(new RoqPtr) 176 } 177 }) 178 179 val ftq = Module(new Ftq) 180 val decode = Module(new DecodeStage) 181 val rename = Module(new Rename) 182 val dispatch = Module(new Dispatch) 183 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 184 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 185 val redirectGen = Module(new RedirectGenerator) 186 187 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 188 189 val roq = Module(new Roq(roqWbSize)) 190 191 val backendRedirect = redirectGen.io.stage2Redirect 192 val frontendRedirect = redirectGen.io.stage3Redirect 193 194 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 195 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 196 x.bits := y.bits 197 }) 198 redirectGen.io.loadRelay := io.fromLsBlock.replay 199 redirectGen.io.roqRedirect := roq.io.redirectOut 200 201 ftq.io.enq <> io.frontend.fetchInfo 202 for(i <- 0 until CommitWidth){ 203 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 204 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 205 } 206 ftq.io.redirect <> backendRedirect 207 ftq.io.frontendRedirect <> frontendRedirect 208 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 209 210 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 211 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 212 213 io.frontend.redirect_cfiUpdate := frontendRedirect 214 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 215 io.frontend.ftqEnqPtr := ftq.io.enqPtr 216 io.frontend.ftqLeftOne := ftq.io.leftOne 217 218 decode.io.in <> io.frontend.cfVec 219 220 val jumpInst = dispatch.io.enqIQCtrl(0).bits 221 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 222 ftqOffsetReg := jumpInst.cf.ftqOffset 223 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 224 io.toIntBlock.jumpPc := GetPcByFtq( 225 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, ftq.io.ftqRead(0).entry.hasLastPrev 226 ) 227 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 228 229 // pipeline between decode and dispatch 230 for (i <- 0 until RenameWidth) { 231 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 232 backendRedirect.valid || frontendRedirect.valid) 233 } 234 235 rename.io.redirect <> backendRedirect 236 rename.io.roqCommits <> roq.io.commits 237 rename.io.out <> dispatch.io.fromRename 238 rename.io.renameBypass <> dispatch.io.renameBypass 239 240 dispatch.io.redirect <> backendRedirect 241 dispatch.io.enqRoq <> roq.io.enq 242 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 243 dispatch.io.readIntRf <> io.toIntBlock.readRf 244 dispatch.io.readFpRf <> io.toFpBlock.readRf 245 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 246 intBusyTable.io.allocPregs(i).valid := preg.isInt 247 fpBusyTable.io.allocPregs(i).valid := preg.isFp 248 intBusyTable.io.allocPregs(i).bits := preg.preg 249 fpBusyTable.io.allocPregs(i).bits := preg.preg 250 } 251 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 252 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 253// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 254 255 256 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 257 fpBusyTable.io.flush := flush 258 intBusyTable.io.flush := flush 259 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 260 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 261 setPhyRegRdy.bits := wb.bits.uop.pdest 262 } 263 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 264 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 265 setPhyRegRdy.bits := wb.bits.uop.pdest 266 } 267 intBusyTable.io.read <> dispatch.io.readIntState 268 fpBusyTable.io.read <> dispatch.io.readFpState 269 270 roq.io.redirect <> backendRedirect 271 roq.io.exeWbResults.zip( 272 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 273 ).foreach{ 274 case(x, y) => 275 x.bits := y.bits 276 x.valid := y.valid 277 } 278 279 // TODO: is 'backendRedirect' necesscary? 280 io.toIntBlock.redirect <> backendRedirect 281 io.toFpBlock.redirect <> backendRedirect 282 io.toLsBlock.redirect <> backendRedirect 283 284 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 285 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 286 287 // roq to int block 288 io.roqio.toCSR <> roq.io.csr 289 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 290 io.roqio.exception.bits := roq.io.exception 291 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 292 // roq to mem block 293 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 294 io.roqio.commits := roq.io.commits 295} 296