1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.{DecodeStage, ImmUnion} 25import xiangshan.backend.rename.{BusyTable, Rename} 26import xiangshan.backend.dispatch.Dispatch 27import xiangshan.backend.exu._ 28import xiangshan.backend.ftq.{Ftq, FtqRead, HasFtqHelper} 29import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 30import xiangshan.mem.LsqEnqIO 31 32class RedirectGenerator(implicit p: Parameters) extends XSModule 33 with HasCircularQueuePtrHelper with HasFtqHelper { 34 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 35 val io = IO(new Bundle() { 36 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 37 val loadReplay = Flipped(ValidIO(new Redirect)) 38 val flush = Input(Bool()) 39 val stage1FtqRead = Vec(numRedirect + 1, new FtqRead) 40 val stage2FtqRead = new FtqRead 41 val stage2Redirect = ValidIO(new Redirect) 42 val stage3Redirect = ValidIO(new Redirect) 43 val memPredUpdate = Output(new MemPredUpdateReq) 44 val memPredFtqRead = new FtqRead // read req send form stage 2 45 }) 46 /* 47 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 48 | | | | | | | 49 |============= reg & compare =====| | ======== 50 | | 51 | | 52 | | Stage2 53 | | 54 redirect (flush backend) | 55 | | 56 === reg === | ======== 57 | | 58 |----- mux (exception first) -----| Stage3 59 | 60 redirect (send to frontend) 61 */ 62 private class Wrapper(val n: Int) extends Bundle { 63 val redirect = new Redirect 64 val valid = Bool() 65 val idx = UInt(log2Up(n).W) 66 } 67 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 68 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 69 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 70 (if (j < i) !xs(j).valid || compareVec(i)(j) 71 else if (j == i) xs(i).valid 72 else !xs(j).valid || !compareVec(j)(i)) 73 )).andR)) 74 resultOnehot 75 } 76 77 for((ptr, redirect) <- io.stage1FtqRead.map(_.ptr).zip( 78 io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 79 )){ ptr := redirect.ftqIdx } 80 81 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 82 val redirect = Wire(Valid(new Redirect)) 83 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 84 redirect.bits := exuOut.bits.redirect 85 redirect 86 } 87 88 val jumpOut = io.exuMispredict.head 89 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 90 val oldestOneHot = selectOldestRedirect(allRedirect) 91 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 92 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 93 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 94 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 95 96 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 97 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 98 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 99 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 100 val s1_redirect_valid_reg = RegNext(oldestValid) 101 val s1_redirect_onehot = RegNext(oldestOneHot) 102 103 // stage1 -> stage2 104 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 105 io.stage2Redirect.bits := s1_redirect_bits_reg 106 io.stage2Redirect.bits.cfiUpdate := DontCare 107 // at stage2, we read ftq to get pc 108 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 109 110 val s1_isReplay = s1_redirect_onehot.last 111 val s1_isJump = s1_redirect_onehot.head 112 val ftqRead = Mux1H(s1_redirect_onehot, io.stage1FtqRead).entry 113 val cfiUpdate_pc = Cat( 114 ftqRead.ftqPC.head(VAddrBits - s1_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 115 s1_redirect_bits_reg.ftqOffset, 116 0.U(instOffsetBits.W) 117 ) 118 val real_pc = GetPcByFtq( 119 ftqRead.ftqPC, s1_redirect_bits_reg.ftqOffset, 120 ftqRead.lastPacketPC.valid, 121 ftqRead.lastPacketPC.bits 122 ) 123 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 124 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 125 val target = Mux(s1_isReplay, 126 real_pc, // repaly from itself 127 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 128 Mux(s1_isJump, s1_jumpTarget, brTarget), 129 snpc 130 ) 131 ) 132 133 // get pc from ftq 134 io.memPredFtqRead.ptr := s1_redirect_bits_reg.stFtqIdx 135 // valid only if redirect is caused by load violation 136 // store_pc is used to update store set 137 val memPredFtqRead = io.memPredFtqRead.entry 138 val store_pc = GetPcByFtq(memPredFtqRead.ftqPC, RegNext(s1_redirect_bits_reg).stFtqOffset, 139 memPredFtqRead.lastPacketPC.valid, 140 memPredFtqRead.lastPacketPC.bits 141 ) 142 143 // update load violation predictor if load violation redirect triggered 144 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 145 // update wait table 146 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 147 io.memPredUpdate.wdata := true.B 148 // update store set 149 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 150 // store pc is ready 1 cycle after s1_isReplay is judged 151 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 152 153 154 val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) 155 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 156 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 157 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 158 val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) 159 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 160 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 161 val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) 162 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 163 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 164 val s2_ftqRead = io.stage2FtqRead.entry 165 166 io.stage3Redirect.valid := s2_redirect_valid_reg 167 io.stage3Redirect.bits := s2_redirect_bits_reg 168 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 169 stage3CfiUpdate.pc := s2_cfiUpdata_pc 170 stage3CfiUpdate.pd := s2_pd 171 stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 172 stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 173 stage3CfiUpdate.predHist := s2_ftqRead.predHist 174 stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 175 stage3CfiUpdate.hist := s2_hist 176 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 177 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 178 stage3CfiUpdate.target := s2_target 179 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 180 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 181} 182 183class CtrlBlock(implicit p: Parameters) extends XSModule 184 with HasCircularQueuePtrHelper with HasFtqHelper { 185 val io = IO(new Bundle { 186 val frontend = Flipped(new FrontendToBackendIO) 187 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 188 // from int block 189 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 190 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 191 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 192 val memoryViolation = Flipped(ValidIO(new Redirect)) 193 val enqLsq = Flipped(new LsqEnqIO) 194 val jumpPc = Output(UInt(VAddrBits.W)) 195 val jalr_target = Output(UInt(VAddrBits.W)) 196 val roqio = new Bundle { 197 // to int block 198 val toCSR = new RoqCSRIO 199 val exception = ValidIO(new ExceptionInfo) 200 // to mem block 201 val lsq = new RoqLsqIO 202 } 203 val csrCtrl = Input(new CustomCSRCtrlIO) 204 val perfInfo = Output(new Bundle{ 205 val ctrlInfo = new Bundle { 206 val roqFull = Input(Bool()) 207 val intdqFull = Input(Bool()) 208 val fpdqFull = Input(Bool()) 209 val lsdqFull = Input(Bool()) 210 } 211 val bpuInfo = new Bundle { 212 val bpRight = Output(UInt(XLEN.W)) 213 val bpWrong = Output(UInt(XLEN.W)) 214 } 215 }) 216 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 217 // redirect out 218 val redirect = ValidIO(new Redirect) 219 val flush = Output(Bool()) 220 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 221 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 222 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 223 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 224 }) 225 226 val ftq = Module(new Ftq) 227 228 val decode = Module(new DecodeStage) 229 val rename = Module(new Rename) 230 val dispatch = Module(new Dispatch) 231 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 232 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 233 val redirectGen = Module(new RedirectGenerator) 234 235 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 236 val roq = Module(new Roq(roqWbSize)) 237 238 val backendRedirect = redirectGen.io.stage2Redirect 239 val frontendRedirect = redirectGen.io.stage3Redirect 240 val flush = roq.io.flushOut.valid 241 val flushReg = RegNext(flush) 242 243 val exuRedirect = io.exuRedirect.map(x => { 244 val valid = x.valid && x.bits.redirectValid 245 val killedByOlder = x.bits.uop.roqIdx.needFlush(backendRedirect, flushReg) 246 val delayed = Wire(Valid(new ExuOutput)) 247 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 248 delayed.bits := RegEnable(x.bits, x.valid) 249 delayed 250 }) 251 val loadReplay = Wire(Valid(new Redirect)) 252 loadReplay.valid := RegNext(io.memoryViolation.valid && 253 !io.memoryViolation.bits.roqIdx.needFlush(backendRedirect, flushReg), 254 init = false.B 255 ) 256 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 257 VecInit(ftq.io.ftqRead.tail.dropRight(2)) <> redirectGen.io.stage1FtqRead 258 ftq.io.ftqRead.dropRight(1).last <> redirectGen.io.memPredFtqRead 259 ftq.io.cfiRead <> redirectGen.io.stage2FtqRead 260 redirectGen.io.exuMispredict <> exuRedirect 261 redirectGen.io.loadReplay <> loadReplay 262 redirectGen.io.flush := flushReg 263 264 ftq.io.enq <> io.frontend.fetchInfo 265 for(i <- 0 until CommitWidth){ 266 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 267 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 268 } 269 ftq.io.redirect <> backendRedirect 270 ftq.io.flush := flushReg 271 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 272 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 273 ftq.io.frontendRedirect <> frontendRedirect 274 ftq.io.exuWriteback <> exuRedirect 275 276 ftq.io.ftqRead.last.ptr := roq.io.flushOut.bits.ftqIdx 277 val flushPC = GetPcByFtq( 278 ftq.io.ftqRead.last.entry.ftqPC, 279 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 280 ftq.io.ftqRead.last.entry.lastPacketPC.valid, 281 ftq.io.ftqRead.last.entry.lastPacketPC.bits 282 ) 283 284 val flushRedirect = Wire(Valid(new Redirect)) 285 flushRedirect.valid := flushReg 286 flushRedirect.bits := DontCare 287 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 288 flushRedirect.bits.interrupt := true.B 289 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 290 io.roqio.toCSR.trapTarget, 291 flushPC + 4.U // flush pipe 292 ) 293 val flushRedirectReg = Wire(Valid(new Redirect)) 294 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 295 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 296 297 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, frontendRedirect) 298 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 299 io.frontend.ftqEnqPtr := ftq.io.enqPtr 300 io.frontend.ftqLeftOne := ftq.io.leftOne 301 302 decode.io.in <> io.frontend.cfVec 303 // currently, we only update wait table when isReplay 304 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 305 decode.io.memPredUpdate(1) := DontCare 306 decode.io.memPredUpdate(1).valid := false.B 307 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 308 decode.io.csrCtrl := RegNext(io.csrCtrl) 309 310 311 val jumpInst = dispatch.io.enqIQCtrl(0).bits 312 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 313 ftqOffsetReg := jumpInst.cf.ftqOffset 314 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 315 io.jumpPc := GetPcByFtq( 316 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 317 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 318 ftq.io.ftqRead(0).entry.lastPacketPC.bits 319 ) 320 io.jalr_target := ftq.io.ftqRead(0).entry.target 321 322 // pipeline between decode and dispatch 323 for (i <- 0 until RenameWidth) { 324 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 325 flushReg || io.frontend.redirect_cfiUpdate.valid) 326 } 327 328 rename.io.redirect <> backendRedirect 329 rename.io.flush := flushReg 330 rename.io.roqCommits <> roq.io.commits 331 rename.io.out <> dispatch.io.fromRename 332 rename.io.renameBypass <> dispatch.io.renameBypass 333 rename.io.dispatchInfo <> dispatch.io.preDpInfo 334 rename.io.csrCtrl <> RegNext(io.csrCtrl) 335 336 dispatch.io.redirect <> backendRedirect 337 dispatch.io.flush := flushReg 338 dispatch.io.enqRoq <> roq.io.enq 339 dispatch.io.enqLsq <> io.enqLsq 340 dispatch.io.singleStep := false.B 341 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 342 intBusyTable.io.allocPregs(i).valid := preg.isInt 343 fpBusyTable.io.allocPregs(i).valid := preg.isFp 344 intBusyTable.io.allocPregs(i).bits := preg.preg 345 fpBusyTable.io.allocPregs(i).bits := preg.preg 346 } 347 dispatch.io.enqIQCtrl := DontCare 348 io.enqIQ <> dispatch.io.enqIQCtrl 349 dispatch.io.csrCtrl <> io.csrCtrl 350 dispatch.io.storeIssue <> io.stIn 351 dispatch.io.readIntRf <> io.readIntRf 352 dispatch.io.readFpRf <> io.readFpRf 353 354 fpBusyTable.io.flush := flushReg 355 intBusyTable.io.flush := flushReg 356 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 357 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 358 setPhyRegRdy.bits := wb.bits.uop.pdest 359 } 360 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 361 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 362 setPhyRegRdy.bits := wb.bits.uop.pdest 363 } 364 intBusyTable.io.read <> dispatch.io.readIntState 365 fpBusyTable.io.read <> dispatch.io.readFpState 366 367 roq.io.redirect <> backendRedirect 368 val exeWbResults = VecInit(io.writeback ++ io.stOut) 369 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 370 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(backendRedirect, flushReg)) 371 roq_wb.bits := RegNext(wb.bits) 372 } 373 374 // TODO: is 'backendRedirect' necesscary? 375 io.redirect <> backendRedirect 376 io.flush <> flushReg 377 io.debug_int_rat <> rename.io.debug_int_rat 378 io.debug_fp_rat <> rename.io.debug_fp_rat 379 380// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 381// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 382 383 // roq to int block 384 io.roqio.toCSR <> roq.io.csr 385 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 386 io.roqio.exception := roq.io.exception 387 io.roqio.exception.bits.uop.cf.pc := flushPC 388 // roq to mem block 389 io.roqio.lsq <> roq.io.lsq 390 391 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 392 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 393 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 394 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 395 io.perfInfo.bpuInfo <> RegNext(ftq.io.bpuInfo) 396} 397