1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils.{XSPerfAccumulate, XSPerfHistogram} 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21 22class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 23 override def shouldBeInlined: Boolean = false 24 25 private implicit val dpParams: BackendParams = params 26 lazy val module = new DataPathImp(this) 27 28 println(s"[DataPath] Preg Params: ") 29 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 30 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 31} 32 33class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 34 extends LazyModuleImp(wrapper) with HasXSParameter { 35 36 private val VCONFIG_PORT = params.vconfigPort 37 private val VLD_PORT = params.vldPort 38 39 val io = IO(new DataPathIO()) 40 41 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 42 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 43 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 44 45 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 46 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 47 48 // just refences for convience 49 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromVfIQ ++ fromMemIQ).toSeq 50 51 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 52 53 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toVfExu ++ toMemExu).toSeq 54 55 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 56 57 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 58 59 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 60 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 61 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 62 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 63 64 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 65 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 66 67 // port -> win 68 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 69 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 70 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 71 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 72 73 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 74 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 75 76 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq 77 private val intDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 78 private val intNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 79 80 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 81 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 82 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 83 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 84 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 85 if (intNumRegSrcs(iqIdx)(exuIdx) == 2) { 86 val src0Req = inRFReadReqSeq(0).valid && intDataSources(iqIdx)(exuIdx)(0).readReg 87 val src1Req = inRFReadReqSeq(1).valid && intDataSources(iqIdx)(exuIdx)(1).readReg 88 if (srcIdx == 0) { 89 arbInSeq(srcIdx).valid := src0Req || src1Req 90 arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr) 91 } else { 92 arbInSeq(srcIdx).valid := src0Req && src1Req 93 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 94 } 95 } else { 96 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && intDataSources(iqIdx)(exuIdx)(srcIdx).readReg 97 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 98 } 99 } else { 100 arbInSeq(srcIdx).valid := false.B 101 arbInSeq(srcIdx).bits.addr := 0.U 102 } 103 } 104 } 105 } 106 107 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq 108 109 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 110 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 111 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 112 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 113 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 114 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 115 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 116 } else { 117 arbInSeq(srcIdx).valid := false.B 118 arbInSeq(srcIdx).bits.addr := 0.U 119 } 120 } 121 } 122 } 123 124 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 125 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq 126 127 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 128 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 129 arbIn.valid := inRFWriteReq 130 } 131 } 132 133 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 134 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 135 arbIn.valid := inRFWriteReq 136 } 137 } 138 139 private val intSchdParams = params.schdParams(IntScheduler()) 140 private val vfSchdParams = params.schdParams(VfScheduler()) 141 private val memSchdParams = params.schdParams(MemScheduler()) 142 143 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 144 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 145 // Todo: limit read port 146 private val numIntR = numIntRfReadByExu 147 private val numVfR = numVfRfReadByExu 148 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 149 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 150 151 private val schdParams = params.allSchdParams 152 153 private val pcReadFtqVld = Wire(chiselTypeOf(io.pcFromPcTargetMem.fromDataPathFtqVld)) 154 private val pcReadFtqPtr = Wire(chiselTypeOf(io.pcFromPcTargetMem.fromDataPathFtqPtr)) 155 private val pcReadFtqOffset = Wire(chiselTypeOf(io.pcFromPcTargetMem.fromDataPathFtqOffset)) 156 private val pcRdata = io.pcFromPcTargetMem.toDataPathPC 157 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 158 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 159 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 160 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 161 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 162 163 private val vfRfSplitNum = VLEN / XLEN 164 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 165 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 166 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 167 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 168 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 169 170 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 171 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 172 pcReadFtqVld.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 173 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 174 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 175 io.pcFromPcTargetMem.fromDataPathFtqVld := pcReadFtqVld 176 io.pcFromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 177 io.pcFromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 178 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 179 if (env.AlwaysBasicDiff || env.EnableDifftest) { 180 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 181 } else { None } 182 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 183 if (env.AlwaysBasicDiff || env.EnableDifftest) { 184 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 185 } else { None } 186 187 private val fpDebugReadData: Option[Vec[UInt]] = 188 if (env.AlwaysBasicDiff || env.EnableDifftest) { 189 Some(Wire(Vec(32, UInt(XLEN.W)))) 190 } else { None } 191 private val vecDebugReadData: Option[Vec[UInt]] = 192 if (env.AlwaysBasicDiff || env.EnableDifftest) { 193 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 194 } else { None } 195 private val vconfigDebugReadData: Option[UInt] = 196 if (env.AlwaysBasicDiff || env.EnableDifftest) { 197 Some(Wire(UInt(64.W))) 198 } else { None } 199 200 201 fpDebugReadData.foreach(_ := vfDebugRead 202 .get._2 203 .slice(0, 32) 204 .map(_(63, 0)) 205 ) // fp only used [63, 0] 206 vecDebugReadData.foreach(_ := vfDebugRead 207 .get._2 208 .slice(32, 64) 209 .map(x => Seq(x(63, 0), x(127, 64))).flatten 210 ) 211 vconfigDebugReadData.foreach(_ := vfDebugRead 212 .get._2(64)(63, 0) 213 ) 214 215 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 216 217 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 218 bankNum = 1, 219 debugReadAddr = intDebugRead.map(_._1), 220 debugReadData = intDebugRead.map(_._2)) 221 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 222 debugReadAddr = vfDebugRead.map(_._1), 223 debugReadData = vfDebugRead.map(_._2)) 224 225 intRfWaddr := io.fromIntWb.map(_.addr).toSeq 226 intRfWdata := io.fromIntWb.map(_.data).toSeq 227 intRfWen := io.fromIntWb.map(_.wen).toSeq 228 229 for (portIdx <- intRfRaddr.indices) { 230 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 231 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 232 else 233 intRfRaddr(portIdx) := 0.U 234 } 235 236 vfRfWaddr := io.fromVfWb.map(_.addr).toSeq 237 vfRfWdata := io.fromVfWb.map(_.data).toSeq 238 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 239 240 for (portIdx <- vfRfRaddr.indices) { 241 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 242 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 243 else 244 vfRfRaddr(portIdx) := 0.U 245 } 246 247 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 248 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 249 // vfRfRaddr(VLD_PORT) := io.vldReadPort.addr 250 io.vldReadPort.data := DontCare 251 252 intDebugRead.foreach { case (addr, _) => 253 addr := io.debugIntRat.get 254 } 255 256 vfDebugRead.foreach { case (addr, _) => 257 addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get 258 } 259 println(s"[DataPath] " + 260 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 261 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 262 263 val s1_addrOHs = Reg(MixedVec( 264 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 265 )) 266 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 267 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 268 )) 269 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 270 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 271 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 272 s1Vec.zip(s0Vec).map { case (s1, s0) => 273 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 274 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 275 } 276 } 277 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 278 out := reg 279 } 280 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 281 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 282 283 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 284 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 285 286 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 287 288 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 289 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 290 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 291 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 292 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 293 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 294 iuRdata.zip(realIuCfg) 295 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 296 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 297 } 298 } 299 300 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 301 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 302 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 303 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 304 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 305 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 306 iuRdata.zip(realIuCfg) 307 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 308 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 309 } 310 } 311 312 val og0_cancel_no_load = og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1) 313 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.toSeq)) 314 for (i <- fromIQ.indices) { 315 for (j <- fromIQ(i).indices) { 316 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 317 // refs 318 val s1_valid = s1_toExuValid(i)(j) 319 val s1_ready = s1_toExuReady(i)(j) 320 val s1_data = s1_toExuData(i)(j) 321 val s1_addrOH = s1_addrOHs(i)(j) 322 val s0 = fromIQ(i)(j) // s0 323 324 val srcNotBlock = Wire(Bool()) 325 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) => 326 !source.readReg || win._1 && win._2 327 }.fold(true.B)(_ && _) 328 if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 329 val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0) 330 val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1) 331 val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1) 332 val src0IntBlock = (s0.bits.common.dataSources(0).readReg || s0.bits.common.dataSources(1).readReg) && !intRdArbWinner(i)(j)(0) 333 srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock && !src0IntBlock 334 } 335 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j) 336 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 337 val s1_cancel = og1FailedVec2(i)(j) 338 val s0_cancel = Wire(Bool()) 339 if (s0.bits.exuParams.isIQWakeUpSink) { 340 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 341 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 342 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay.asUInt).orR && dataSource.readForward 343 }.reduce(_ || _) && s0.valid 344 } else s0_cancel := false.B 345 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 346 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 347 s1_valid := s0.valid 348 s1_data.fromIssueBundle(s0.bits) // no src data here 349 if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 350 s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value) 351 } 352 s1_addrOH := s0.bits.addrOH 353 }.otherwise { 354 s1_valid := false.B 355 } 356 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 357 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 358 } 359 } 360 361 private val fromIQFire = fromIQ.map(_.map(_.fire)) 362 private val toExuFire = toExu.map(_.map(_.fire)) 363 toIQs.zipWithIndex.foreach { 364 case(toIQ, iqIdx) => 365 toIQ.zipWithIndex.foreach { 366 case (toIU, iuIdx) => 367 // IU: issue unit 368 val og0resp = toIU.og0resp 369 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 370 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 371 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 372 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 373 og0resp.bits.resp := RespType.block 374 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 375 376 val og1resp = toIU.og1resp 377 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 378 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 379 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 380 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 381 // respType: fuIdle ->IQ entry clear 382 // fuUncertain ->IQ entry no action 383 // fuBusy ->IQ entry issued set false, then re-issue 384 // Only hyu, lda and sta are fuUncertain at OG1 stage 385 og1resp.bits.resp := Mux(!og1FailedVec2(iqIdx)(iuIdx), 386 if (toIU.issueQueueParams match { case x => x.isMemAddrIQ && !x.isVecMemIQ }) RespType.uncertain else RespType.success, 387 RespType.block 388 ) 389 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 390 } 391 } 392 393 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 394 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 395 396 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 397 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 398 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 399 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 400 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 401 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 402 } 403 404 for (i <- toExu.indices) { 405 for (j <- toExu(i).indices) { 406 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 407 // refs 408 val sinkData = toExu(i)(j).bits 409 // assign 410 toExu(i)(j).valid := s1_toExuValid(i)(j) 411 s1_toExuReady(i)(j) := toExu(i)(j).ready 412 sinkData := s1_toExuData(i)(j) 413 // s1Reg --[Ctrl]--> exu(s1) ---------- end 414 415 // s1Reg --[Data]--> exu(s1) ---------- begin 416 // data source1: preg read data 417 for (k <- sinkData.src.indices) { 418 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 419 420 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 421 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 422 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 423 else None) :+ 424 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 425 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 426 else None) 427 ).filter(_.nonEmpty).map(_.get) 428 if (readRfMap.nonEmpty) 429 sinkData.src(k) := Mux1H(readRfMap) 430 } 431 if (sinkData.params.hasJmpFu) { 432 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 433 sinkData.pc.get := pcRdata(index) 434 } 435 } 436 } 437 438 if (env.AlwaysBasicDiff || env.EnableDifftest) { 439 val delayedCnt = 2 440 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 441 difftestArchIntRegState.coreid := io.hartId 442 difftestArchIntRegState.value := intDebugRead.get._2 443 444 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 445 difftestArchFpRegState.coreid := io.hartId 446 difftestArchFpRegState.value := fpDebugReadData.get 447 448 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 449 difftestArchVecRegState.coreid := io.hartId 450 difftestArchVecRegState.value := vecDebugReadData.get 451 } 452 453 val int_regcache_size = 48 454 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 455 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 456 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 457 for (i <- intRfWen.indices) { 458 when (intRfWen(i)) { 459 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 460 } 461 } 462 463 val vf_regcache_size = 48 464 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 465 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 466 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 467 for (i <- vfRfWen.indices) { 468 when (vfRfWen.head(i)) { 469 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 470 } 471 } 472 473 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 474 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 475 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 476 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 477 478 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 479 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 480 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 481 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 482 483 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 484 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 485 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 486 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 487 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 488 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 489 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 490 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 491 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 492 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 493 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 494 495 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 496 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 497 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 498 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 499 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 500 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 501 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 502 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 503 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 504 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 505 506 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 507 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 508 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 509 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 510 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 511 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 512 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 513 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 514 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 515 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 516} 517 518class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 519 // params 520 private val intSchdParams = params.schdParams(IntScheduler()) 521 private val vfSchdParams = params.schdParams(VfScheduler()) 522 private val memSchdParams = params.schdParams(MemScheduler()) 523 // bundles 524 val hartId = Input(UInt(8.W)) 525 526 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 527 528 // Todo: check if this can be removed 529 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 530 531 val vldReadPort = new RfReadPort(VLEN, PhyRegIdxWidth) 532 533 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 534 535 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 536 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 537 538 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 539 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 540 541 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 542 543 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 544 545 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 546 547 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 548 549 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 550 551 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 552 553 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 554 555 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 556 557 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 558 559 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 560 561 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 562 563 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 564 565 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 566 567 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 568 569 val pcFromPcTargetMem = Flipped(new PcToDataPathIO(params)) 570 571 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 572 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 573 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 574 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 575 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 576} 577