1package xiangshan.backend.datapath 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DifftestArchFpRegState, DifftestArchIntRegState, DifftestArchVecRegState} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import xiangshan._ 11import xiangshan.backend.BackendParams 12import xiangshan.backend.Bundles._ 13import xiangshan.backend.decode.ImmUnion 14import xiangshan.backend.datapath.DataConfig._ 15import xiangshan.backend.datapath.RdConfig._ 16import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.regfile._ 18 19class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 20 private implicit val dpParams: BackendParams = params 21 lazy val module = new DataPathImp(this) 22 23 println(s"[DataPath] Preg Params: ") 24 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 25 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 26} 27 28class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 29 extends LazyModuleImp(wrapper) with HasXSParameter { 30 31 private val VCONFIG_PORT = params.vconfigPort 32 33 val io = IO(new DataPathIO()) 34 35 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 36 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 37 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 38 private val (fromIntExus, fromVfExus) = (io.fromIntExus, io.fromVfExus) 39 40 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 41 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 42 43 // just refences for convience 44 private val fromIQ = fromIntIQ ++ fromVfIQ ++ fromMemIQ 45 46 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 47 48 private val toExu = toIntExu ++ toVfExu ++ toMemExu 49 50 private val fromExus = fromIntExus ++ fromVfExus 51 52 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 53 54 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 55 56 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 57 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 58 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 59 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 60 61 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())))) 62 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())))) 63 64 // port -> win 65 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready)))) 66 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready)))) 67 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready))) 68 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready))) 69 70 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 71 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 72 73 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid))) 74 75 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 76 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 77 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 78 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 79 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 80 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 81 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 82 } else { 83 arbInSeq(srcIdx).valid := false.B 84 arbInSeq(srcIdx).bits.addr := 0.U 85 } 86 } 87 } 88 } 89 90 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid))) 91 92 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 93 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 94 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 95 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 96 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 97 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 98 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 99 } else { 100 arbInSeq(srcIdx).valid := false.B 101 arbInSeq(srcIdx).bits.addr := 0.U 102 } 103 } 104 } 105 } 106 107 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B))) 108 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B))) 109 110 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 111 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 112 arbIn.valid := inRFWriteReq 113 } 114 } 115 116 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 117 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 118 arbIn.valid := inRFWriteReq 119 } 120 } 121 122 private val intSchdParams = params.schdParams(IntScheduler()) 123 private val vfSchdParams = params.schdParams(VfScheduler()) 124 private val memSchdParams = params.schdParams(MemScheduler()) 125 126 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 127 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 128 // Todo: limit read port 129 private val numIntR = numIntRfReadByExu 130 private val numVfR = numVfRfReadByExu 131 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 132 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 133 134 private val schdParams = params.allSchdParams 135 136 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 137 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 138 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 139 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 140 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 141 142 private val vfRfSplitNum = VLEN / XLEN 143 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 144 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 145 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 146 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 147 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 148 149 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 150 if (env.AlwaysBasicDiff || env.EnableDifftest) { 151 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 152 } else { None } 153 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 154 if (env.AlwaysBasicDiff || env.EnableDifftest) { 155 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 156 } else { None } 157 158 private val fpDebugReadData: Option[Vec[UInt]] = 159 if (env.AlwaysBasicDiff || env.EnableDifftest) { 160 Some(Wire(Vec(32, UInt(XLEN.W)))) 161 } else { None } 162 private val vecDebugReadData: Option[Vec[UInt]] = 163 if (env.AlwaysBasicDiff || env.EnableDifftest) { 164 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 165 } else { None } 166 private val vconfigDebugReadData: Option[UInt] = 167 if (env.AlwaysBasicDiff || env.EnableDifftest) { 168 Some(Wire(UInt(64.W))) 169 } else { None } 170 171 172 fpDebugReadData.foreach(_ := vfDebugRead 173 .get._2 174 .slice(0, 32) 175 .map(_(63, 0)) 176 ) // fp only used [63, 0] 177 vecDebugReadData.foreach(_ := vfDebugRead 178 .get._2 179 .slice(32, 64) 180 .map(x => Seq(x(63, 0), x(127, 64))).flatten 181 ) 182 vconfigDebugReadData.foreach(_ := vfDebugRead 183 .get._2(64)(63, 0) 184 ) 185 186 io.debugVconfig := vconfigDebugReadData.get 187 188 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 189 debugReadAddr = intDebugRead.map(_._1), 190 debugReadData = intDebugRead.map(_._2)) 191 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 192 debugReadAddr = vfDebugRead.map(_._1), 193 debugReadData = vfDebugRead.map(_._2)) 194 195 intRfWaddr := io.fromIntWb.map(_.addr) 196 intRfWdata := io.fromIntWb.map(_.data) 197 intRfWen := io.fromIntWb.map(_.wen) 198 199 for (portIdx <- intRfRaddr.indices) { 200 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 201 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 202 else 203 intRfRaddr(portIdx) := 0.U 204 } 205 206 vfRfWaddr := io.fromVfWb.map(_.addr) 207 vfRfWdata := io.fromVfWb.map(_.data) 208 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 209 210 for (portIdx <- vfRfRaddr.indices) { 211 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 212 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 213 else 214 vfRfRaddr(portIdx) := 0.U 215 } 216 217 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 218 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 219 220 intDebugRead.foreach { case (addr, _) => 221 addr := io.debugIntRat 222 } 223 224 vfDebugRead.foreach { case (addr, _) => 225 addr := io.debugFpRat ++ io.debugVecRat :+ io.debugVconfigRat 226 } 227 println(s"[DataPath] " + 228 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 229 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 230 231 val s1_addrOHs = Reg(MixedVec( 232 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType))) 233 )) 234 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 235 toExu.map(x => MixedVec(x.map(_.valid.cloneType))) 236 )) 237 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType))))) 238 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo 239 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire))))) 240 241 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 242 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 243 244 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 245 246 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 247 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 248 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 249 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 250 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 251 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 252 iuRdata.zip(realIuCfg) 253 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 254 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 255 } 256 } 257 258 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 259 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 260 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 261 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 262 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 263 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 264 iuRdata.zip(realIuCfg) 265 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 266 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 267 } 268 } 269 270 for (i <- fromIQ.indices) { 271 for (j <- fromIQ(i).indices) { 272 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 273 // refs 274 val s1_valid = s1_toExuValid(i)(j) 275 val s1_ready = s1_toExuReady(i)(j) 276 val s1_data = s1_toExuData(i)(j) 277 val s1_addrOH = s1_addrOHs(i)(j) 278 val s0 = fromIQ(i)(j) // s0 279 val notBlock = intRdNotBlock(i)(j) && intWbNotBlock(i)(j) && vfRdNotBlock(i)(j) && vfWbNotBlock(i)(j) 280 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 281 val s1_cancel = og1FailedVec2(i)(j) 282 when (s0.fire && !s1_flush && notBlock && !s1_cancel) { 283 s1_valid := s0.valid 284 s1_data.fromIssueBundle(s0.bits) // no src data here 285 s1_addrOH := s0.bits.addrOH 286 }.otherwise { 287 s1_valid := false.B 288 } 289 s0.ready := (s1_ready || !s1_valid) && notBlock 290 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 291 292 // IQ(s0) --[Data]--> s1Reg ---------- begin 293 // imm extract 294 when (s0.fire && !s1_flush && notBlock) { 295 if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) { 296 // rs1 is always int reg, rs2 may be imm 297 when(SrcType.isImm(s0.bits.srcType(1))) { 298 s1_data.src(1) := ImmExtractor( 299 s0.bits.common.imm, 300 s0.bits.immType, 301 s1_data.params.dataBitsMax, 302 s1_data.params.immType.map(_.litValue) 303 ) 304 } 305 } 306 if (s1_data.params.hasJmpFu) { 307 when(SrcType.isPc(s0.bits.srcType(0))) { 308 s1_data.src(0) := SignExt(s0.bits.jmp.get.pc, XLEN) 309 } 310 } else if (s1_data.params.hasVecFu) { 311 // Fuck off riscv vector imm!!! Why not src1??? 312 when(SrcType.isImm(s0.bits.srcType(0))) { 313 s1_data.src(0) := ImmExtractor( 314 s0.bits.common.imm, 315 s0.bits.immType, 316 s1_data.params.dataBitsMax, 317 s1_data.params.immType.map(_.litValue) 318 ) 319 } 320 } else if (s1_data.params.hasLoadFu) { 321 // dirty code for fused_lui_load 322 when(SrcType.isImm(s0.bits.srcType(0))) { 323 s1_data.src(0) := SignExt(ImmUnion.U.toImm32(s0.bits.common.imm(s0.bits.common.imm.getWidth - 1, ImmUnion.I.len)), XLEN) 324 } 325 } 326 } 327 // IQ(s0) --[Data]--> s1Reg ---------- end 328 } 329 } 330 331 private val fromIQFire = fromIQ.map(_.map(_.fire)) 332 private val toExuFire = toExu.map(_.map(_.fire)) 333 toIQs.zipWithIndex.foreach { 334 case(toIQ, iqIdx) => 335 toIQ.zipWithIndex.foreach { 336 case (toIU, iuIdx) => 337 // IU: issue unit 338 val og0resp = toIU.og0resp 339 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 340 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 341 og0resp.bits.respType := RSFeedbackType.rfArbitFail 342 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 343 og0resp.bits.rfWen := fromIQ(iqIdx)(iuIdx).bits.common.rfWen.getOrElse(false.B) 344 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 345 346 val og1resp = toIU.og1resp 347 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 348 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 349 og1resp.bits.respType := Mux(!og1FailedVec2(iqIdx)(iuIdx), 350 if (toIU.issueQueueParams.isMemAddrIQ) RSFeedbackType.fuUncertain else RSFeedbackType.fuIdle, 351 RSFeedbackType.fuBusy) 352 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 353 og1resp.bits.rfWen := s1_toExuData(iqIdx)(iuIdx).rfWen.getOrElse(false.B) 354 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 355 } 356 } 357 358 io.og0CancelVec.zip(io.og1CancelVec).zipWithIndex.foreach { case ((og0Cancel, og1Cancel), i) => 359 og0Cancel := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 360 og1Cancel := toFlattenExu(i).valid && !toFlattenExu(i).fire 361 } 362 363 for (i <- toExu.indices) { 364 for (j <- toExu(i).indices) { 365 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 366 // refs 367 val sinkData = toExu(i)(j).bits 368 // assign 369 toExu(i)(j).valid := s1_toExuValid(i)(j) 370 s1_toExuReady(i)(j) := toExu(i)(j).ready 371 sinkData := s1_toExuData(i)(j) 372 // s1Reg --[Ctrl]--> exu(s1) ---------- end 373 374 // s1Reg --[Data]--> exu(s1) ---------- begin 375 // data source1: preg read data 376 for (k <- sinkData.src.indices) { 377 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 378 379 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 380 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 381 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 382 else None) :+ 383 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 384 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 385 else None) 386 ).filter(_.nonEmpty).map(_.get) 387 if (readRfMap.nonEmpty) 388 sinkData.src(k) := Mux1H(readRfMap) 389 } 390 391 // data source2: extracted imm and pc saved in s1Reg 392 if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) { 393 when(SrcType.isImm(s1_srcType(i)(j)(1))) { 394 sinkData.src(1) := s1_toExuData(i)(j).src(1) 395 } 396 } 397 if (sinkData.params.hasJmpFu) { 398 when(SrcType.isPc(s1_srcType(i)(j)(0))) { 399 sinkData.src(0) := s1_toExuData(i)(j).src(0) 400 } 401 } else if (sinkData.params.hasVecFu) { 402 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 403 sinkData.src(0) := s1_toExuData(i)(j).src(0) 404 } 405 } else if (sinkData.params.hasLoadFu) { 406 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 407 sinkData.src(0) := s1_toExuData(i)(j).src(0) 408 } 409 } 410 // s1Reg --[Data]--> exu(s1) ---------- end 411 } 412 } 413 414 if (env.AlwaysBasicDiff || env.EnableDifftest) { 415 val delayedCnt = 2 416 val difftestArchIntRegState = Module(new DifftestArchIntRegState) 417 difftestArchIntRegState.io.clock := clock 418 difftestArchIntRegState.io.coreid := io.hartId 419 difftestArchIntRegState.io.gpr := DelayN(intDebugRead.get._2, delayedCnt) 420 421 val difftestArchFpRegState = Module(new DifftestArchFpRegState) 422 difftestArchFpRegState.io.clock := clock 423 difftestArchFpRegState.io.coreid := io.hartId 424 difftestArchFpRegState.io.fpr := DelayN(fpDebugReadData.get, delayedCnt) 425 426 val difftestArchVecRegState = Module(new DifftestArchVecRegState) 427 difftestArchVecRegState.io.clock := clock 428 difftestArchVecRegState.io.coreid := io.hartId 429 difftestArchVecRegState.io.vpr := DelayN(vecDebugReadData.get, delayedCnt) 430 } 431} 432 433class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 434 // params 435 private val intSchdParams = params.schdParams(IntScheduler()) 436 private val vfSchdParams = params.schdParams(VfScheduler()) 437 private val memSchdParams = params.schdParams(MemScheduler()) 438 private val exuParams = params.allExuParams 439 // bundles 440 val hartId = Input(UInt(8.W)) 441 442 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 443 444 // Todo: check if this can be removed 445 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 446 447 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 448 449 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 450 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 451 452 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 453 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 454 455 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 456 457 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 458 459 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 460 461 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 462 463 val og0CancelVec = Output(ExuVec(backendParams.numExu)) 464 465 val og1CancelVec = Output(ExuVec(backendParams.numExu)) 466 467 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 468 469 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 470 471 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 472 473 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 474 475 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 476 477 val fromIntExus = Flipped(intSchdParams.genExuOutputValidBundle) 478 479 val fromVfExus = Flipped(intSchdParams.genExuOutputValidBundle) 480 481 val debugIntRat = Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W))) 482 val debugFpRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 483 val debugVecRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 484 val debugVconfigRat = Input(UInt(vfSchdParams.pregIdxWidth.W)) 485 val debugVconfig = Output(UInt(XLEN.W)) 486 487} 488