1package xiangshan.backend.datapath 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DifftestArchFpRegState, DifftestArchIntRegState, DifftestArchVecRegState} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import xiangshan._ 10import xiangshan.backend.BackendParams 11import xiangshan.backend.datapath.DataConfig._ 12import xiangshan.backend.datapath.RdConfig._ 13import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 14import xiangshan.backend.Bundles._ 15import xiangshan.backend.regfile._ 16 17class RFArbiterBundle(addrWidth: Int)(implicit p: Parameters) extends XSBundle { 18 val addr = UInt(addrWidth.W) 19} 20 21class RFReadArbiterIO(inPortSize: Int, outPortSize: Int, pregWidth: Int)(implicit p: Parameters) extends XSBundle { 22 val in = Vec(inPortSize, Flipped(DecoupledIO(new RFArbiterBundle(pregWidth)))) 23 val out = Vec(outPortSize, Valid(new RFArbiterBundle(pregWidth))) 24 val flush = Flipped(ValidIO(new Redirect)) 25} 26 27class RFReadArbiter(isInt: Boolean)(implicit p: Parameters) extends XSModule { 28 val allExuParams = backendParams.allExuParams 29 30 val portConfigs = allExuParams.map(_.rfrPortConfigs.flatten).flatten.filter{ 31 rfrPortConfigs => 32 if(isInt){ 33 rfrPortConfigs.isInstanceOf[IntRD] 34 } 35 else{ 36 rfrPortConfigs.isInstanceOf[VfRD] 37 } 38 } 39 40 val pregParams = if(isInt) backendParams.intPregParams else backendParams.vfPregParams 41 42 val io = IO(new RFReadArbiterIO(portConfigs.size, backendParams.numRfRead, pregParams.addrWidth)) 43 // inGroup[port -> Bundle] 44 val inGroup: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = io.in.zip(portConfigs).groupBy{ case(port, config) => config.port} 45 // sort by priority 46 val inGroupSorted: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = inGroup.map{ 47 case(key, value) => (key -> value.sortBy{ case(port, config) => config.priority}) 48 } 49 50 private val arbiters: Seq[Option[Arbiter[RFArbiterBundle]]] = Seq.tabulate(backendParams.numRfRead) { x => { 51 if (inGroupSorted.contains(x)) { 52 Some(Module(new Arbiter(new RFArbiterBundle(pregParams.addrWidth), inGroupSorted(x).length))) 53 } else { 54 None 55 } 56 }} 57 58 arbiters.zipWithIndex.foreach { case (arb, i) => 59 if (arb.nonEmpty) { 60 arb.get.io.in.zip(inGroupSorted(i).map(_._1)).foreach { case (arbIn, addrIn) => 61 arbIn <> addrIn 62 } 63 } 64 } 65 66 io.out.zip(arbiters).foreach { case (addrOut, arb) => 67 if (arb.nonEmpty) { 68 val arbOut = arb.get.io.out 69 arbOut.ready := true.B 70 addrOut.valid := arbOut.valid 71 addrOut.bits := arbOut.bits 72 } else { 73 addrOut := 0.U.asTypeOf(addrOut) 74 } 75 } 76} 77 78class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 79 private implicit val dpParams: BackendParams = params 80 lazy val module = new DataPathImp(this) 81} 82 83class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 84 extends LazyModuleImp(wrapper) with HasXSParameter { 85 86 private val VCONFIG_PORT = params.vconfigPort 87 88 val io = IO(new DataPathIO()) 89 90 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 91 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 92 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 93 94 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 95 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 96 97 // just refences for convience 98 private val fromIQ = fromIntIQ ++ fromVfIQ ++ fromMemIQ 99 100 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 101 102 private val toExu = toIntExu ++ toVfExu ++ toMemExu 103 104 private val intRFReadArbiter = Module(new RFReadArbiter(true)) 105 private val vfRFReadArbiter = Module(new RFReadArbiter(false)) 106 107 private val issuePortsIn = fromIQ.flatten 108 private val intBlocks = fromIQ.map{ case iq => Wire(Vec(iq.size, Bool())) } 109 private val intBlocksSeq = intBlocks.flatten 110 private val vfBlocks = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) } 111 private val vfBlocksSeq = vfBlocks.flatten 112 113 val intReadPortInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntRfReadBundle.size).scan(0)(_ + _) 114 issuePortsIn.zipWithIndex.foreach{ 115 case (issuePortIn, idx) => 116 val readPortIn = issuePortIn.bits.getIntRfReadBundle 117 val l = intReadPortInSize(idx) 118 val r = intReadPortInSize(idx + 1) 119 val arbiterIn = intRFReadArbiter.io.in.slice(l, r) 120 arbiterIn.zip(readPortIn).foreach{ 121 case(sink, source) => 122 sink.bits.addr := source.addr 123 sink.valid := issuePortIn.valid && SrcType.isXp(source.srcType) 124 } 125 if(r > l){ 126 intBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map { 127 case (sink, source) => Mux(SrcType.isXp(source.srcType), sink.ready, true.B) 128 }.reduce(_ & _) 129 } 130 else{ 131 intBlocksSeq(idx) := false.B 132 } 133 } 134 intRFReadArbiter.io.flush := io.flush 135 136 val vfReadPortInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getFpRfReadBundle.size).scan(0)(_ + _) 137 issuePortsIn.zipWithIndex.foreach { 138 case (issuePortIn, idx) => 139 val readPortIn = issuePortIn.bits.getFpRfReadBundle 140 val l = vfReadPortInSize(idx) 141 val r = vfReadPortInSize(idx + 1) 142 val arbiterIn = vfRFReadArbiter.io.in.slice(l, r) 143 arbiterIn.zip(readPortIn).foreach { 144 case (sink, source) => 145 sink.bits.addr := source.addr 146 sink.valid := issuePortIn.valid && SrcType.isVfp(source.srcType) 147 } 148 if (r > l) { 149 vfBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map { 150 case (sink, source) => Mux(SrcType.isVfp(source.srcType), sink.ready, true.B) 151 }.reduce(_ & _) 152 } 153 else { 154 vfBlocksSeq(idx) := false.B 155 } 156 } 157 vfRFReadArbiter.io.flush := io.flush 158 159 private val intSchdParams = params.schdParams(IntScheduler()) 160 private val vfSchdParams = params.schdParams(VfScheduler()) 161 private val memSchdParams = params.schdParams(MemScheduler()) 162 163 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 164 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 165 // Todo: limit read port 166 private val numIntR = numIntRfReadByExu 167 private val numVfR = numVfRfReadByExu 168 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 169 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 170 171 private val schdParams = params.allSchdParams 172 173 private val intRfRaddr = Wire(Vec(params.numRfRead, UInt(intSchdParams.pregIdxWidth.W))) 174 private val intRfRdata = Wire(Vec(params.numRfRead, UInt(intSchdParams.rfDataWidth.W))) 175 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 176 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 177 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 178 179 private val vfRfSplitNum = VLEN / XLEN 180 private val vfRfRaddr = Wire(Vec(params.numRfRead, UInt(vfSchdParams.pregIdxWidth.W))) 181 private val vfRfRdata = Wire(Vec(params.numRfRead, UInt(vfSchdParams.rfDataWidth.W))) 182 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 183 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 184 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 185 186 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 187 if (env.AlwaysBasicDiff || env.EnableDifftest) { 188 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 189 } else { None } 190 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 191 if (env.AlwaysBasicDiff || env.EnableDifftest) { 192 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 193 } else { None } 194 195 private val fpDebugReadData: Option[Vec[UInt]] = 196 if (env.AlwaysBasicDiff || env.EnableDifftest) { 197 Some(Wire(Vec(32, UInt(XLEN.W)))) 198 } else { None } 199 private val vecDebugReadData: Option[Vec[UInt]] = 200 if (env.AlwaysBasicDiff || env.EnableDifftest) { 201 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 202 } else { None } 203 204 fpDebugReadData.foreach(_ := vfDebugRead 205 .get._2 206 .slice(0, 32) 207 .map(_(63, 0)) 208 ) // fp only used [63, 0] 209 vecDebugReadData.foreach(_ := vfDebugRead 210 .get._2 211 .slice(32, 64) 212 .map(x => Seq(x(63, 0), x(127, 64))).flatten 213 ) 214 215 io.debugVconfig := vfDebugRead.get._2(64)(63, 0) 216 217 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 218 debugReadAddr = intDebugRead.map(_._1), 219 debugReadData = intDebugRead.map(_._2)) 220 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 221 debugReadAddr = vfDebugRead.map(_._1), 222 debugReadData = vfDebugRead.map(_._2)) 223 224 intRfWaddr := io.fromIntWb.map(_.addr) 225 intRfWdata := io.fromIntWb.map(_.data) 226 intRfWen := io.fromIntWb.map(_.wen) 227 228 intRFReadArbiter.io.out.map(_.bits.addr).zip(intRfRaddr).foreach{ case(source, sink) => sink := source } 229 230 vfRfWaddr := io.fromVfWb.map(_.addr) 231 vfRfWdata := io.fromVfWb.map(_.data) 232 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 233 234 vfRFReadArbiter.io.out.map(_.bits.addr).zip(vfRfRaddr).foreach{ case(source, sink) => sink := source } 235 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 236 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 237 238 intDebugRead.foreach { case (addr, _) => 239 addr := io.debugIntRat 240 } 241 242 vfDebugRead.foreach { case (addr, _) => 243 addr := io.debugFpRat ++ io.debugVecRat :+ io.debugVconfigRat 244 } 245 println(s"[DataPath] " + 246 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 247 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 248 249 val s1_addrOHs = Reg(MixedVec( 250 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType))) 251 )) 252 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 253 toExu.map(x => MixedVec(x.map(_.valid.cloneType))) 254 )) 255 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType))))) 256 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo 257 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire))))) 258 259 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 260 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 261 262 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 263 264 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 265 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 266 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 267 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 268 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 269 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 270 iuRdata.zip(realIuCfg) 271 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 272 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 273 } 274 } 275 276 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 277 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 278 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 279 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 280 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 281 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 282 iuRdata.zip(realIuCfg) 283 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 284 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 285 } 286 } 287 288 // var intRfRdataIdx = 0 289// var vfRfRdataIdx = 0 290// for (iqIdx <- toExu.indices) { 291// for (exuIdx <- toExu(iqIdx).indices) { 292// for (srcIdx <- toExu(iqIdx)(exuIdx).bits.src.indices) { 293// val readDataCfgSet = toExu(iqIdx)(exuIdx).bits.params.getSrcDataType(srcIdx) 294// // need read int reg 295// if (readDataCfgSet.intersect(IntRegSrcDataSet).nonEmpty) { 296// println(s"[DataPath] (iqIdx, exuIdx, srcIdx): ($iqIdx, $exuIdx, $srcIdx)") 297// s1_intPregRData(iqIdx)(exuIdx)(srcIdx) := intRfRdata(intRfRdataIdx) 298// } else { 299// // better for debug, should never assigned to other bundles 300// s1_intPregRData(iqIdx)(exuIdx)(srcIdx) := "hdead_beef_dead_beef".U 301// } 302// // need read vf reg 303// if (readDataCfgSet.intersect(VfRegSrcDataSet).nonEmpty) { 304// s1_vfPregRData(iqIdx)(exuIdx)(srcIdx) := vfRfRdata(vfRfRdataIdx) 305// vfRfRdataIdx += 1 306// } else { 307// // better for debug, should never assigned to other bundles 308// s1_vfPregRData(iqIdx)(exuIdx)(srcIdx) := "hdead_beef_dead_beef_dead_beef_dead_beef".U 309// } 310// } 311// } 312// } 313// 314// println(s"[DataPath] assigned RegFile Rdata: int(${intRfRdataIdx}), vf(${vfRfRdataIdx})") 315 316 for (i <- fromIQ.indices) { 317 for (j <- fromIQ(i).indices) { 318 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 319 // refs 320 val s1_valid = s1_toExuValid(i)(j) 321 val s1_ready = s1_toExuReady(i)(j) 322 val s1_data = s1_toExuData(i)(j) 323 val s1_addrOH = s1_addrOHs(i)(j) 324 val s0 = fromIQ(i)(j) // s0 325 val block = intBlocks(i)(j) || vfBlocks(i)(j) 326 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 327 when (s0.fire && !s1_flush && !block) { 328 s1_valid := s0.valid 329 s1_data.fromIssueBundle(s0.bits) // no src data here 330 s1_addrOH := s0.bits.addrOH 331 }.otherwise { 332 s1_valid := false.B 333 } 334 335 s0.ready := (s1_ready || !s1_valid) && !block 336 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 337 338 // IQ(s0) --[Data]--> s1Reg ---------- begin 339 // imm extract 340 when (s0.fire && !s1_flush && !block) { 341 if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) { 342 // rs1 is always int reg, rs2 may be imm 343 when(SrcType.isImm(s0.bits.srcType(1))) { 344 s1_data.src(1) := ImmExtractor( 345 s0.bits.common.imm, 346 s0.bits.immType, 347 s1_data.DataBits, 348 s1_data.params.immType.map(_.litValue) 349 ) 350 } 351 } 352 if (s1_data.params.hasJmpFu) { 353 when(SrcType.isPc(s0.bits.srcType(0))) { 354 s1_data.src(0) := SignExt(s0.bits.jmp.get.pc, XLEN) 355 } 356 } 357 } 358 // IQ(s0) --[Data]--> s1Reg ---------- end 359 } 360 } 361 362 private val fromIQFire = fromIQ.map(_.map(_.fire)) 363 private val toExuFire = toExu.map(_.map(_.fire)) 364 toIQs.zipWithIndex.foreach { 365 case(toIQ, iqIdx) => 366 toIQ.zipWithIndex.foreach { 367 case (toIU, iuIdx) => 368 // IU: issue unit 369 val og0resp = toIU.og0resp 370 og0resp.valid := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 371 og0resp.bits.respType := RSFeedbackType.rfArbitFail 372 og0resp.bits.success := false.B 373 og0resp.bits.addrOH := fromIQ(iqIdx)(iuIdx).bits.addrOH 374 375 val og1resp = toIU.og1resp 376 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 377 og1resp.bits.respType := Mux(toExuFire(iqIdx)(iuIdx), RSFeedbackType.fuIdle, RSFeedbackType.fuBusy) 378 og1resp.bits.success := false.B 379 og1resp.bits.addrOH := s1_addrOHs(iqIdx)(iuIdx) 380 } 381 } 382 383 for (i <- toExu.indices) { 384 for (j <- toExu(i).indices) { 385 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 386 // refs 387 val sinkData = toExu(i)(j).bits 388 // assign 389 toExu(i)(j).valid := s1_toExuValid(i)(j) 390 s1_toExuReady(i)(j) := toExu(i)(j).ready 391 sinkData := s1_toExuData(i)(j) 392 // s1Reg --[Ctrl]--> exu(s1) ---------- end 393 394 // s1Reg --[Data]--> exu(s1) ---------- begin 395 // data source1: preg read data 396 for (k <- sinkData.src.indices) { 397 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 398 399 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 400 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 401 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 402 else None) :+ 403 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 404 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 405 else None) 406 ).filter(_.nonEmpty).map(_.get) 407 if (readRfMap.nonEmpty) 408 sinkData.src(k) := Mux1H(readRfMap) 409 } 410 411 // data source2: extracted imm and pc saved in s1Reg 412 if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) { 413 when(SrcType.isImm(s1_srcType(i)(j)(1))) { 414 sinkData.src(1) := s1_toExuData(i)(j).src(1) 415 } 416 } 417 if (sinkData.params.hasJmpFu) { 418 when(SrcType.isPc(s1_srcType(i)(j)(0))) { 419 sinkData.src(0) := s1_toExuData(i)(j).src(0) 420 } 421 } 422 // s1Reg --[Data]--> exu(s1) ---------- end 423 } 424 } 425 426 if (env.AlwaysBasicDiff || env.EnableDifftest) { 427 val delayedCnt = 2 428 val difftestArchIntRegState = Module(new DifftestArchIntRegState) 429 difftestArchIntRegState.io.clock := clock 430 difftestArchIntRegState.io.coreid := io.hartId 431 difftestArchIntRegState.io.gpr := DelayN(intDebugRead.get._2, delayedCnt) 432 433 val difftestArchFpRegState = Module(new DifftestArchFpRegState) 434 difftestArchFpRegState.io.clock := clock 435 difftestArchFpRegState.io.coreid := io.hartId 436 difftestArchFpRegState.io.fpr := DelayN(fpDebugReadData.get, delayedCnt) 437 438 val difftestArchVecRegState = Module(new DifftestArchVecRegState) 439 difftestArchVecRegState.io.clock := clock 440 difftestArchVecRegState.io.coreid := io.hartId 441 difftestArchVecRegState.io.vpr := DelayN(vecDebugReadData.get, delayedCnt) 442 } 443} 444 445class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 446 // params 447 private val intSchdParams = params.schdParams(IntScheduler()) 448 private val vfSchdParams = params.schdParams(VfScheduler()) 449 private val memSchdParams = params.schdParams(MemScheduler()) 450 // bundles 451 val hartId = Input(UInt(8.W)) 452 453 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 454 455 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 456 457 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 458 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 459 460 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 461 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 462 463 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 464 465 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 466 467 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 468 469 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 470 471 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 472 473 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 474 475 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 476 477 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 478 479 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 480 481 val debugIntRat = Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W))) 482 val debugFpRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 483 val debugVecRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 484 val debugVconfigRat = Input(UInt(vfSchdParams.pregIdxWidth.W)) 485 val debugVconfig = Output(UInt(XLEN.W)) 486 487} 488