1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils.{XSPerfAccumulate, XSPerfHistogram} 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21 22class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 23 override def shouldBeInlined: Boolean = false 24 25 private implicit val dpParams: BackendParams = params 26 lazy val module = new DataPathImp(this) 27 28 println(s"[DataPath] Preg Params: ") 29 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 30 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 31} 32 33class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 34 extends LazyModuleImp(wrapper) with HasXSParameter { 35 36 private val VCONFIG_PORT = params.vconfigPort 37 private val VLD_PORT = params.vldPort 38 39 val io = IO(new DataPathIO()) 40 41 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 42 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 43 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 44 45 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 46 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 47 48 // just refences for convience 49 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromVfIQ ++ fromMemIQ).toSeq 50 51 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 52 53 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toVfExu ++ toMemExu).toSeq 54 55 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 56 57 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 58 59 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 60 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 61 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 62 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 63 64 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 65 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 66 67 // port -> win 68 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 69 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 70 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 71 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 72 73 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 74 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 75 76 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq 77 private val intDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 78 private val intNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 79 80 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 81 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 82 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 83 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 84 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 85 if (intNumRegSrcs(iqIdx)(exuIdx) == 2) { 86 val src0Req = inRFReadReqSeq(0).valid && intDataSources(iqIdx)(exuIdx)(0).readReg 87 val src1Req = inRFReadReqSeq(1).valid && intDataSources(iqIdx)(exuIdx)(1).readReg 88 if (srcIdx == 0) { 89 arbInSeq(srcIdx).valid := src0Req || src1Req 90 arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr) 91 } else { 92 arbInSeq(srcIdx).valid := src0Req && src1Req 93 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 94 } 95 } else { 96 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && intDataSources(iqIdx)(exuIdx)(srcIdx).readReg 97 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 98 } 99 } else { 100 arbInSeq(srcIdx).valid := false.B 101 arbInSeq(srcIdx).bits.addr := 0.U 102 } 103 } 104 } 105 } 106 107 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq 108 109 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 110 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 111 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 112 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 113 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 114 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 115 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 116 } else { 117 arbInSeq(srcIdx).valid := false.B 118 arbInSeq(srcIdx).bits.addr := 0.U 119 } 120 } 121 } 122 } 123 124 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 125 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq 126 127 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 128 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 129 arbIn.valid := inRFWriteReq 130 } 131 } 132 133 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 134 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 135 arbIn.valid := inRFWriteReq 136 } 137 } 138 139 private val intSchdParams = params.schdParams(IntScheduler()) 140 private val vfSchdParams = params.schdParams(VfScheduler()) 141 private val memSchdParams = params.schdParams(MemScheduler()) 142 143 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 144 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 145 // Todo: limit read port 146 private val numIntR = numIntRfReadByExu 147 private val numVfR = numVfRfReadByExu 148 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 149 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 150 151 private val schdParams = params.allSchdParams 152 153 private val pcReadFtqPtr = Wire(chiselTypeOf(io.pcFromPcTargetMem.fromDataPathFtqPtr)) 154 private val pcReadFtqOffset = Wire(chiselTypeOf(io.pcFromPcTargetMem.fromDataPathFtqOffset)) 155 private val pcRdata = io.pcFromPcTargetMem.toDataPathPC 156 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 157 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 158 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 159 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 160 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 161 162 private val vfRfSplitNum = VLEN / XLEN 163 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 164 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 165 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 166 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 167 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 168 169 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 170 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 171 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 172 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 173 io.pcFromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 174 io.pcFromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 175 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 176 if (env.AlwaysBasicDiff || env.EnableDifftest) { 177 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 178 } else { None } 179 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 180 if (env.AlwaysBasicDiff || env.EnableDifftest) { 181 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 182 } else { None } 183 184 private val fpDebugReadData: Option[Vec[UInt]] = 185 if (env.AlwaysBasicDiff || env.EnableDifftest) { 186 Some(Wire(Vec(32, UInt(XLEN.W)))) 187 } else { None } 188 private val vecDebugReadData: Option[Vec[UInt]] = 189 if (env.AlwaysBasicDiff || env.EnableDifftest) { 190 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 191 } else { None } 192 private val vconfigDebugReadData: Option[UInt] = 193 if (env.AlwaysBasicDiff || env.EnableDifftest) { 194 Some(Wire(UInt(64.W))) 195 } else { None } 196 197 198 fpDebugReadData.foreach(_ := vfDebugRead 199 .get._2 200 .slice(0, 32) 201 .map(_(63, 0)) 202 ) // fp only used [63, 0] 203 vecDebugReadData.foreach(_ := vfDebugRead 204 .get._2 205 .slice(32, 64) 206 .map(x => Seq(x(63, 0), x(127, 64))).flatten 207 ) 208 vconfigDebugReadData.foreach(_ := vfDebugRead 209 .get._2(64)(63, 0) 210 ) 211 212 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 213 214 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 215 bankNum = 1, 216 debugReadAddr = intDebugRead.map(_._1), 217 debugReadData = intDebugRead.map(_._2)) 218 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 219 debugReadAddr = vfDebugRead.map(_._1), 220 debugReadData = vfDebugRead.map(_._2)) 221 222 intRfWaddr := io.fromIntWb.map(_.addr).toSeq 223 intRfWdata := io.fromIntWb.map(_.data).toSeq 224 intRfWen := io.fromIntWb.map(_.wen).toSeq 225 226 for (portIdx <- intRfRaddr.indices) { 227 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 228 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 229 else 230 intRfRaddr(portIdx) := 0.U 231 } 232 233 vfRfWaddr := io.fromVfWb.map(_.addr).toSeq 234 vfRfWdata := io.fromVfWb.map(_.data).toSeq 235 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 236 237 for (portIdx <- vfRfRaddr.indices) { 238 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 239 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 240 else 241 vfRfRaddr(portIdx) := 0.U 242 } 243 244 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 245 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 246 // vfRfRaddr(VLD_PORT) := io.vldReadPort.addr 247 io.vldReadPort.data := DontCare 248 249 intDebugRead.foreach { case (addr, _) => 250 addr := io.debugIntRat.get 251 } 252 253 vfDebugRead.foreach { case (addr, _) => 254 addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get 255 } 256 println(s"[DataPath] " + 257 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 258 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 259 260 val s1_addrOHs = Reg(MixedVec( 261 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 262 )) 263 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 264 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 265 )) 266 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 267 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 268 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 269 s1Vec.zip(s0Vec).map { case (s1, s0) => 270 s1.imm := s0.bits.common.imm 271 s1.immType := s0.bits.immType 272 } 273 } 274 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 275 out := reg 276 } 277 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 278 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 279 280 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 281 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 282 283 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 284 285 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 286 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 287 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 288 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 289 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 290 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 291 iuRdata.zip(realIuCfg) 292 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 293 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 294 } 295 } 296 297 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 298 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 299 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 300 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 301 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 302 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 303 iuRdata.zip(realIuCfg) 304 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 305 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 306 } 307 } 308 309 for (i <- fromIQ.indices) { 310 for (j <- fromIQ(i).indices) { 311 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 312 // refs 313 val s1_valid = s1_toExuValid(i)(j) 314 val s1_ready = s1_toExuReady(i)(j) 315 val s1_data = s1_toExuData(i)(j) 316 val s1_addrOH = s1_addrOHs(i)(j) 317 val s0 = fromIQ(i)(j) // s0 318 319 val srcNotBlock = Wire(Bool()) 320 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) => 321 !source.readReg || win._1 && win._2 322 }.fold(true.B)(_ && _) 323 if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 324 val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0) 325 val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1) 326 val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1) 327 srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock 328 } 329 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j) 330 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 331 val s1_cancel = og1FailedVec2(i)(j) 332 val s1_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 333 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s1_ldCancel) { 334 s1_valid := s0.valid 335 s1_data.fromIssueBundle(s0.bits) // no src data here 336 if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 337 s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value) 338 } 339 s1_addrOH := s0.bits.addrOH 340 }.otherwise { 341 s1_valid := false.B 342 } 343 s0.ready := (s1_ready || !s1_valid) && notBlock 344 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 345 } 346 } 347 348 private val fromIQFire = fromIQ.map(_.map(_.fire)) 349 private val toExuFire = toExu.map(_.map(_.fire)) 350 toIQs.zipWithIndex.foreach { 351 case(toIQ, iqIdx) => 352 toIQ.zipWithIndex.foreach { 353 case (toIU, iuIdx) => 354 // IU: issue unit 355 val og0resp = toIU.og0resp 356 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 357 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 358 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 359 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 360 og0resp.bits.resp := RespType.block 361 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 362 363 val og1resp = toIU.og1resp 364 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 365 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 366 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 367 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 368 // respType: fuIdle ->IQ entry clear 369 // fuUncertain ->IQ entry no action 370 // fuBusy ->IQ entry issued set false, then re-issue 371 // Only hyu, lda and sta are fuUncertain at OG1 stage 372 og1resp.bits.resp := Mux(!og1FailedVec2(iqIdx)(iuIdx), 373 if (toIU.issueQueueParams.isMemAddrIQ) RespType.uncertain else RespType.success, 374 RespType.block 375 ) 376 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 377 } 378 } 379 380 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 381 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 382 383 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 384 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire && { 385 if (fromFlattenIQ(i).bits.common.rfWen.isDefined) 386 fromFlattenIQ(i).bits.common.rfWen.get && fromFlattenIQ(i).bits.common.pdest =/= 0.U 387 else 388 true.B 389 } 390 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 391 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 392 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 393 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 394 } 395 396 for (i <- toExu.indices) { 397 for (j <- toExu(i).indices) { 398 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 399 // refs 400 val sinkData = toExu(i)(j).bits 401 // assign 402 toExu(i)(j).valid := s1_toExuValid(i)(j) 403 s1_toExuReady(i)(j) := toExu(i)(j).ready 404 sinkData := s1_toExuData(i)(j) 405 // s1Reg --[Ctrl]--> exu(s1) ---------- end 406 407 // s1Reg --[Data]--> exu(s1) ---------- begin 408 // data source1: preg read data 409 for (k <- sinkData.src.indices) { 410 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 411 412 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 413 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 414 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 415 else None) :+ 416 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 417 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 418 else None) 419 ).filter(_.nonEmpty).map(_.get) 420 if (readRfMap.nonEmpty) 421 sinkData.src(k) := Mux1H(readRfMap) 422 } 423 if (sinkData.params.hasJmpFu) { 424 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 425 sinkData.pc.get := pcRdata(index) 426 } 427 } 428 } 429 430 if (env.AlwaysBasicDiff || env.EnableDifftest) { 431 val delayedCnt = 2 432 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 433 difftestArchIntRegState.coreid := io.hartId 434 difftestArchIntRegState.value := intDebugRead.get._2 435 436 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 437 difftestArchFpRegState.coreid := io.hartId 438 difftestArchFpRegState.value := fpDebugReadData.get 439 440 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 441 difftestArchVecRegState.coreid := io.hartId 442 difftestArchVecRegState.value := vecDebugReadData.get 443 } 444 445 val int_regcache_size = 48 446 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 447 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 448 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 449 for (i <- intRfWen.indices) { 450 when (intRfWen(i)) { 451 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 452 } 453 } 454 455 val vf_regcache_size = 48 456 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 457 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 458 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 459 for (i <- vfRfWen.indices) { 460 when (vfRfWen.head(i)) { 461 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 462 } 463 } 464 465 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 466 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 467 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 468 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 469 470 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 471 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 472 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 473 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 474 475 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 476 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 477 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 478 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 479 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 480 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 481 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 482 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 483 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 484 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 485 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 486 487 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 488 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 489 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 490 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 491 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 492 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 493 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 494 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 495 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 496 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 497 498 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 499 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 500 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 501 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 502 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 503 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 504 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 505 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 506 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 507 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 508} 509 510class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 511 // params 512 private val intSchdParams = params.schdParams(IntScheduler()) 513 private val vfSchdParams = params.schdParams(VfScheduler()) 514 private val memSchdParams = params.schdParams(MemScheduler()) 515 // bundles 516 val hartId = Input(UInt(8.W)) 517 518 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 519 520 // Todo: check if this can be removed 521 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 522 523 val vldReadPort = new RfReadPort(VLEN, PhyRegIdxWidth) 524 525 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 526 527 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 528 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 529 530 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 531 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 532 533 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 534 535 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 536 537 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 538 539 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 540 541 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 542 543 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 544 545 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 546 547 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 548 549 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 550 551 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 552 553 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 554 555 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 556 557 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 558 559 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 560 561 val pcFromPcTargetMem = Flipped(new PcToDataPathIO(params)) 562 563 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 564 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 565 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 566 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 567 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 568} 569