1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 71 staticInst := io.enq.staticInst 72 private val inst: XSInstBitFields = staticInst.instr.asTypeOf(new XSInstBitFields) 73 74 val src1 = Cat(0.U(1.W), inst.RS1) 75 val src2 = Cat(0.U(1.W), inst.RS2) 76 val dest = Cat(0.U(1.W), inst.RD) 77 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 88 val lmul = Wire(UInt(4.W)) 89 val isVsetSimple = Wire(Bool()) 90 91 //pre decode 92 val simple = Module(new DecodeUnit) 93 simple.io.enq.ctrlFlow := staticInst 94 simple.io.enq.vtype := io.vtype 95 simple.io.csrCtrl := io.csrCtrl 96 decodedInstsSimple := simple.io.deq.decodedInst 97 lmul := simple.io.deq.uopInfo.lmul 98 isVsetSimple := simple.io.deq.decodedInst.isVset 99 when(isVsetSimple) { 100 when(dest === 0.U && src1 === 0.U) { 101 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 102 }.elsewhen(src1 === 0.U) { 103 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 104 } 105 when(io.vtype.illegal){ 106 decodedInstsSimple.flushPipe := true.B 107 } 108 } 109 //Type of uop Div 110 val typeOfSplit = decodedInstsSimple.uopSplitType 111 112 when(typeOfSplit === UopSplitType.DIR) { 113 numOfUop := Mux(dest =/= 0.U, 2.U, 114 Mux(src1 =/= 0.U, 1.U, 115 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 116 } .otherwise { 117 numOfUop := simple.io.deq.uopInfo.numOfUop 118 } 119 120 121 //uop div up to maxUopSize 122 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 123 csBundle.map { case dst => 124 dst := decodedInstsSimple 125 dst.firstUop := false.B 126 dst.lastUop := false.B 127 } 128 129 csBundle(0).numUops := numOfUop 130 csBundle(0).firstUop := true.B 131 csBundle(numOfUop - 1.U).lastUop := true.B 132 133 switch(typeOfSplit) { 134 is(UopSplitType.DIR) { 135 when(isVsetSimple) { 136 when(dest =/= 0.U) { 137 csBundle(0).fuType := FuType.vsetiwi.U 138 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 139 csBundle(0).flushPipe := false.B 140 csBundle(0).rfWen := true.B 141 csBundle(0).vecWen := false.B 142 csBundle(1).ldest := VCONFIG_IDX.U 143 csBundle(1).rfWen := false.B 144 csBundle(1).vecWen := true.B 145 }.elsewhen(src1 =/= 0.U) { 146 csBundle(0).ldest := VCONFIG_IDX.U 147 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 148 csBundle(0).fuType := FuType.vsetfwf.U 149 csBundle(0).srcType(0) := SrcType.vp 150 csBundle(0).lsrc(0) := VCONFIG_IDX.U 151 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 152 csBundle(0).srcType(0) := SrcType.reg 153 csBundle(0).srcType(1) := SrcType.imm 154 csBundle(0).lsrc(1) := 0.U 155 csBundle(0).ldest := FP_TMP_REG_MV.U 156 csBundle(0).fuType := FuType.i2f.U 157 csBundle(0).rfWen := false.B 158 csBundle(0).fpWen := true.B 159 csBundle(0).vecWen := false.B 160 csBundle(0).fpu.isAddSub := false.B 161 csBundle(0).fpu.typeTagIn := FPU.D 162 csBundle(0).fpu.typeTagOut := FPU.D 163 csBundle(0).fpu.fromInt := true.B 164 csBundle(0).fpu.wflags := false.B 165 csBundle(0).fpu.fpWen := true.B 166 csBundle(0).fpu.div := false.B 167 csBundle(0).fpu.sqrt := false.B 168 csBundle(0).fpu.fcvt := false.B 169 csBundle(0).flushPipe := false.B 170 csBundle(1).fuType := FuType.vsetfwf.U 171 csBundle(1).srcType(0) := SrcType.vp 172 csBundle(1).lsrc(0) := VCONFIG_IDX.U 173 csBundle(1).srcType(1) := SrcType.fp 174 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 175 csBundle(1).ldest := VCONFIG_IDX.U 176 } 177 } 178 } 179 is(UopSplitType.VEC_VVV) { 180 for (i <- 0 until MAX_VLMUL) { 181 csBundle(i).lsrc(0) := src1 + i.U 182 csBundle(i).lsrc(1) := src2 + i.U 183 csBundle(i).lsrc(2) := dest + i.U 184 csBundle(i).ldest := dest + i.U 185 csBundle(i).uopIdx := i.U 186 } 187 } 188 is(UopSplitType.VEC_VFV) { 189 for (i <- 0 until MAX_VLMUL) { 190 csBundle(i).lsrc(1) := src2 + i.U 191 csBundle(i).lsrc(2) := dest + i.U 192 csBundle(i).ldest := dest + i.U 193 csBundle(i).uopIdx := i.U 194 } 195 } 196 is(UopSplitType.VEC_EXT2) { 197 for (i <- 0 until MAX_VLMUL / 2) { 198 csBundle(2 * i).lsrc(1) := src2 + i.U 199 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 200 csBundle(2 * i).ldest := dest + (2 * i).U 201 csBundle(2 * i).uopIdx := (2 * i).U 202 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 203 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 204 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 205 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 206 } 207 } 208 is(UopSplitType.VEC_EXT4) { 209 for (i <- 0 until MAX_VLMUL / 4) { 210 csBundle(4 * i).lsrc(1) := src2 + i.U 211 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 212 csBundle(4 * i).ldest := dest + (4 * i).U 213 csBundle(4 * i).uopIdx := (4 * i).U 214 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 215 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 216 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 217 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 218 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 219 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 220 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 221 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 222 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 223 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 224 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 225 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 226 } 227 } 228 is(UopSplitType.VEC_EXT8) { 229 for (i <- 0 until MAX_VLMUL) { 230 csBundle(i).lsrc(1) := src2 231 csBundle(i).lsrc(2) := dest + i.U 232 csBundle(i).ldest := dest + i.U 233 csBundle(i).uopIdx := i.U 234 } 235 } 236 is(UopSplitType.VEC_0XV) { 237 /* 238 FMV.D.X 239 */ 240 csBundle(0).srcType(0) := SrcType.reg 241 csBundle(0).srcType(1) := SrcType.imm 242 csBundle(0).lsrc(1) := 0.U 243 csBundle(0).ldest := FP_TMP_REG_MV.U 244 csBundle(0).fuType := FuType.i2f.U 245 csBundle(0).rfWen := false.B 246 csBundle(0).fpWen := true.B 247 csBundle(0).vecWen := false.B 248 csBundle(0).fpu.isAddSub := false.B 249 csBundle(0).fpu.typeTagIn := FPU.D 250 csBundle(0).fpu.typeTagOut := FPU.D 251 csBundle(0).fpu.fromInt := true.B 252 csBundle(0).fpu.wflags := false.B 253 csBundle(0).fpu.fpWen := true.B 254 csBundle(0).fpu.div := false.B 255 csBundle(0).fpu.sqrt := false.B 256 csBundle(0).fpu.fcvt := false.B 257 /* 258 vfmv.s.f 259 */ 260 csBundle(1).srcType(0) := SrcType.fp 261 csBundle(1).srcType(1) := SrcType.vp 262 csBundle(1).srcType(2) := SrcType.vp 263 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 264 csBundle(1).lsrc(1) := 0.U 265 csBundle(1).lsrc(2) := dest 266 csBundle(1).ldest := dest 267 csBundle(1).fuType := FuType.vppu.U 268 csBundle(1).fuOpType := VpermType.dummy 269 csBundle(1).rfWen := false.B 270 csBundle(1).fpWen := false.B 271 csBundle(1).vecWen := true.B 272 } 273 is(UopSplitType.VEC_VXV) { 274 /* 275 FMV.D.X 276 */ 277 csBundle(0).srcType(0) := SrcType.reg 278 csBundle(0).srcType(1) := SrcType.imm 279 csBundle(0).lsrc(1) := 0.U 280 csBundle(0).ldest := FP_TMP_REG_MV.U 281 csBundle(0).fuType := FuType.i2f.U 282 csBundle(0).rfWen := false.B 283 csBundle(0).fpWen := true.B 284 csBundle(0).vecWen := false.B 285 csBundle(0).fpu.isAddSub := false.B 286 csBundle(0).fpu.typeTagIn := FPU.D 287 csBundle(0).fpu.typeTagOut := FPU.D 288 csBundle(0).fpu.fromInt := true.B 289 csBundle(0).fpu.wflags := false.B 290 csBundle(0).fpu.fpWen := true.B 291 csBundle(0).fpu.div := false.B 292 csBundle(0).fpu.sqrt := false.B 293 csBundle(0).fpu.fcvt := false.B 294 /* 295 LMUL 296 */ 297 for (i <- 0 until MAX_VLMUL) { 298 csBundle(i + 1).srcType(0) := SrcType.fp 299 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 300 csBundle(i + 1).lsrc(1) := src2 + i.U 301 csBundle(i + 1).lsrc(2) := dest + i.U 302 csBundle(i + 1).ldest := dest + i.U 303 csBundle(i + 1).uopIdx := i.U 304 } 305 } 306 is(UopSplitType.VEC_VVW) { 307 for (i <- 0 until MAX_VLMUL / 2) { 308 csBundle(2 * i).lsrc(0) := src1 + i.U 309 csBundle(2 * i).lsrc(1) := src2 + i.U 310 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 311 csBundle(2 * i).ldest := dest + (2 * i).U 312 csBundle(2 * i).uopIdx := (2 * i).U 313 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 314 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 315 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 316 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 317 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 318 } 319 } 320 is(UopSplitType.VEC_VFW) { 321 for (i <- 0 until MAX_VLMUL / 2) { 322 csBundle(2 * i).lsrc(0) := src1 323 csBundle(2 * i).lsrc(1) := src2 + i.U 324 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 325 csBundle(2 * i).ldest := dest + (2 * i).U 326 csBundle(2 * i).uopIdx := (2 * i).U 327 csBundle(2 * i + 1).lsrc(0) := src1 328 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 329 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 331 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 332 } 333 } 334 is(UopSplitType.VEC_WVW) { 335 for (i <- 0 until MAX_VLMUL / 2) { 336 csBundle(2 * i).lsrc(0) := src1 + i.U 337 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 338 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 339 csBundle(2 * i).ldest := dest + (2 * i).U 340 csBundle(2 * i).uopIdx := (2 * i).U 341 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 342 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 343 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 345 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 346 } 347 } 348 is(UopSplitType.VEC_VXW) { 349 /* 350 FMV.D.X 351 */ 352 csBundle(0).srcType(0) := SrcType.reg 353 csBundle(0).srcType(1) := SrcType.imm 354 csBundle(0).lsrc(1) := 0.U 355 csBundle(0).ldest := FP_TMP_REG_MV.U 356 csBundle(0).fuType := FuType.i2f.U 357 csBundle(0).rfWen := false.B 358 csBundle(0).fpWen := true.B 359 csBundle(0).vecWen := false.B 360 csBundle(0).fpu.isAddSub := false.B 361 csBundle(0).fpu.typeTagIn := FPU.D 362 csBundle(0).fpu.typeTagOut := FPU.D 363 csBundle(0).fpu.fromInt := true.B 364 csBundle(0).fpu.wflags := false.B 365 csBundle(0).fpu.fpWen := true.B 366 csBundle(0).fpu.div := false.B 367 csBundle(0).fpu.sqrt := false.B 368 csBundle(0).fpu.fcvt := false.B 369 370 for (i <- 0 until MAX_VLMUL / 2) { 371 csBundle(2 * i + 1).srcType(0) := SrcType.fp 372 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 373 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 374 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 375 csBundle(2 * i + 1).ldest := dest + (2 * i).U 376 csBundle(2 * i + 1).uopIdx := (2 * i).U 377 csBundle(2 * i + 2).srcType(0) := SrcType.fp 378 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 379 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 380 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 382 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopSplitType.VEC_WXW) { 386 /* 387 FMV.D.X 388 */ 389 csBundle(0).srcType(0) := SrcType.reg 390 csBundle(0).srcType(1) := SrcType.imm 391 csBundle(0).lsrc(1) := 0.U 392 csBundle(0).ldest := FP_TMP_REG_MV.U 393 csBundle(0).fuType := FuType.i2f.U 394 csBundle(0).rfWen := false.B 395 csBundle(0).fpWen := true.B 396 csBundle(0).vecWen := false.B 397 csBundle(0).fpu.isAddSub := false.B 398 csBundle(0).fpu.typeTagIn := FPU.D 399 csBundle(0).fpu.typeTagOut := FPU.D 400 csBundle(0).fpu.fromInt := true.B 401 csBundle(0).fpu.wflags := false.B 402 csBundle(0).fpu.fpWen := true.B 403 csBundle(0).fpu.div := false.B 404 csBundle(0).fpu.sqrt := false.B 405 csBundle(0).fpu.fcvt := false.B 406 407 for (i <- 0 until MAX_VLMUL / 2) { 408 csBundle(2 * i + 1).srcType(0) := SrcType.fp 409 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 410 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 411 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 412 csBundle(2 * i + 1).ldest := dest + (2 * i).U 413 csBundle(2 * i + 1).uopIdx := (2 * i).U 414 csBundle(2 * i + 2).srcType(0) := SrcType.fp 415 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 419 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopSplitType.VEC_WVV) { 423 for (i <- 0 until MAX_VLMUL / 2) { 424 425 csBundle(2 * i).lsrc(0) := src1 + i.U 426 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 427 csBundle(2 * i).lsrc(2) := dest + i.U 428 csBundle(2 * i).ldest := dest + i.U 429 csBundle(2 * i).uopIdx := (2 * i).U 430 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 431 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 432 csBundle(2 * i + 1).lsrc(2) := dest + i.U 433 csBundle(2 * i + 1).ldest := dest + i.U 434 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 435 } 436 } 437 is(UopSplitType.VEC_WFW) { 438 for (i <- 0 until MAX_VLMUL / 2) { 439 csBundle(2 * i).lsrc(0) := src1 440 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 441 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 442 csBundle(2 * i).ldest := dest + (2 * i).U 443 csBundle(2 * i).uopIdx := (2 * i).U 444 csBundle(2 * i + 1).lsrc(0) := src1 445 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 446 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 447 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 448 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 449 } 450 } 451 is(UopSplitType.VEC_WXV) { 452 /* 453 FMV.D.X 454 */ 455 csBundle(0).srcType(0) := SrcType.reg 456 csBundle(0).srcType(1) := SrcType.imm 457 csBundle(0).lsrc(1) := 0.U 458 csBundle(0).ldest := FP_TMP_REG_MV.U 459 csBundle(0).fuType := FuType.i2f.U 460 csBundle(0).rfWen := false.B 461 csBundle(0).fpWen := true.B 462 csBundle(0).vecWen := false.B 463 csBundle(0).fpu.isAddSub := false.B 464 csBundle(0).fpu.typeTagIn := FPU.D 465 csBundle(0).fpu.typeTagOut := FPU.D 466 csBundle(0).fpu.fromInt := true.B 467 csBundle(0).fpu.wflags := false.B 468 csBundle(0).fpu.fpWen := true.B 469 csBundle(0).fpu.div := false.B 470 csBundle(0).fpu.sqrt := false.B 471 csBundle(0).fpu.fcvt := false.B 472 473 for (i <- 0 until MAX_VLMUL / 2) { 474 csBundle(2 * i + 1).srcType(0) := SrcType.fp 475 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 476 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 477 csBundle(2 * i + 1).lsrc(2) := dest + i.U 478 csBundle(2 * i + 1).ldest := dest + i.U 479 csBundle(2 * i + 1).uopIdx := (2 * i).U 480 csBundle(2 * i + 2).srcType(0) := SrcType.fp 481 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 482 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 483 csBundle(2 * i + 2).lsrc(2) := dest + i.U 484 csBundle(2 * i + 2).ldest := dest + i.U 485 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 486 } 487 } 488 is(UopSplitType.VEC_VVM) { 489 csBundle(0).lsrc(2) := dest 490 csBundle(0).ldest := dest 491 csBundle(0).uopIdx := 0.U 492 for (i <- 1 until MAX_VLMUL) { 493 csBundle(i).lsrc(0) := src1 + i.U 494 csBundle(i).lsrc(1) := src2 + i.U 495 csBundle(i).lsrc(2) := dest 496 csBundle(i).ldest := dest 497 csBundle(i).uopIdx := i.U 498 } 499 csBundle(numOfUop - 1.U).ldest := dest 500 } 501 is(UopSplitType.VEC_VFM) { 502 csBundle(0).lsrc(2) := dest 503 csBundle(0).ldest := dest 504 csBundle(0).uopIdx := 0.U 505 for (i <- 1 until MAX_VLMUL) { 506 csBundle(i).lsrc(0) := src1 507 csBundle(i).lsrc(1) := src2 + i.U 508 csBundle(i).lsrc(2) := dest 509 csBundle(i).ldest := dest 510 csBundle(i).uopIdx := i.U 511 } 512 csBundle(numOfUop - 1.U).ldest := dest 513 } 514 is(UopSplitType.VEC_VXM) { 515 /* 516 FMV.D.X 517 */ 518 csBundle(0).srcType(0) := SrcType.reg 519 csBundle(0).srcType(1) := SrcType.imm 520 csBundle(0).lsrc(1) := 0.U 521 csBundle(0).ldest := FP_TMP_REG_MV.U 522 csBundle(0).fuType := FuType.i2f.U 523 csBundle(0).rfWen := false.B 524 csBundle(0).fpWen := true.B 525 csBundle(0).vecWen := false.B 526 csBundle(0).fpu.isAddSub := false.B 527 csBundle(0).fpu.typeTagIn := FPU.D 528 csBundle(0).fpu.typeTagOut := FPU.D 529 csBundle(0).fpu.fromInt := true.B 530 csBundle(0).fpu.wflags := false.B 531 csBundle(0).fpu.fpWen := true.B 532 csBundle(0).fpu.div := false.B 533 csBundle(0).fpu.sqrt := false.B 534 csBundle(0).fpu.fcvt := false.B 535 //LMUL 536 csBundle(1).srcType(0) := SrcType.fp 537 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 538 csBundle(1).lsrc(2) := dest 539 csBundle(1).ldest := dest 540 csBundle(1).uopIdx := 0.U 541 for (i <- 1 until MAX_VLMUL) { 542 csBundle(i + 1).srcType(0) := SrcType.fp 543 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 544 csBundle(i + 1).lsrc(1) := src2 + i.U 545 csBundle(i + 1).lsrc(2) := dest 546 csBundle(i + 1).ldest := dest 547 csBundle(i + 1).uopIdx := i.U 548 } 549 csBundle(numOfUop - 1.U).ldest := dest 550 } 551 is(UopSplitType.VEC_SLIDE1UP) { 552 /* 553 FMV.D.X 554 */ 555 csBundle(0).srcType(0) := SrcType.reg 556 csBundle(0).srcType(1) := SrcType.imm 557 csBundle(0).lsrc(1) := 0.U 558 csBundle(0).ldest := FP_TMP_REG_MV.U 559 csBundle(0).fuType := FuType.i2f.U 560 csBundle(0).rfWen := false.B 561 csBundle(0).fpWen := true.B 562 csBundle(0).vecWen := false.B 563 csBundle(0).fpu.isAddSub := false.B 564 csBundle(0).fpu.typeTagIn := FPU.D 565 csBundle(0).fpu.typeTagOut := FPU.D 566 csBundle(0).fpu.fromInt := true.B 567 csBundle(0).fpu.wflags := false.B 568 csBundle(0).fpu.fpWen := true.B 569 csBundle(0).fpu.div := false.B 570 csBundle(0).fpu.sqrt := false.B 571 csBundle(0).fpu.fcvt := false.B 572 //LMUL 573 csBundle(1).srcType(0) := SrcType.fp 574 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 575 csBundle(1).lsrc(2) := dest 576 csBundle(1).ldest := dest 577 csBundle(1).uopIdx := 0.U 578 for (i <- 1 until MAX_VLMUL) { 579 csBundle(i + 1).srcType(0) := SrcType.vp 580 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 581 csBundle(i + 1).lsrc(1) := src2 + i.U 582 csBundle(i + 1).lsrc(2) := dest + i.U 583 csBundle(i + 1).ldest := dest + i.U 584 csBundle(i + 1).uopIdx := i.U 585 } 586 } 587 is(UopSplitType.VEC_FSLIDE1UP) { 588 //LMUL 589 csBundle(0).srcType(0) := SrcType.fp 590 csBundle(0).lsrc(0) := src1 591 csBundle(0).lsrc(1) := src2 592 csBundle(0).lsrc(2) := dest 593 csBundle(0).ldest := dest 594 csBundle(0).uopIdx := 0.U 595 for (i <- 1 until MAX_VLMUL) { 596 csBundle(i).srcType(0) := SrcType.vp 597 csBundle(i).lsrc(0) := src2 + (i - 1).U 598 csBundle(i).lsrc(1) := src2 + i.U 599 csBundle(i).lsrc(2) := dest + i.U 600 csBundle(i).ldest := dest + i.U 601 csBundle(i).uopIdx := i.U 602 } 603 } 604 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 605 /* 606 FMV.D.X 607 */ 608 csBundle(0).srcType(0) := SrcType.reg 609 csBundle(0).srcType(1) := SrcType.imm 610 csBundle(0).lsrc(1) := 0.U 611 csBundle(0).ldest := FP_TMP_REG_MV.U 612 csBundle(0).fuType := FuType.i2f.U 613 csBundle(0).rfWen := false.B 614 csBundle(0).fpWen := true.B 615 csBundle(0).vecWen := false.B 616 csBundle(0).fpu.isAddSub := false.B 617 csBundle(0).fpu.typeTagIn := FPU.D 618 csBundle(0).fpu.typeTagOut := FPU.D 619 csBundle(0).fpu.fromInt := true.B 620 csBundle(0).fpu.wflags := false.B 621 csBundle(0).fpu.fpWen := true.B 622 csBundle(0).fpu.div := false.B 623 csBundle(0).fpu.sqrt := false.B 624 csBundle(0).fpu.fcvt := false.B 625 //LMUL 626 for (i <- 0 until MAX_VLMUL) { 627 csBundle(2 * i + 1).srcType(0) := SrcType.vp 628 csBundle(2 * i + 1).srcType(1) := SrcType.vp 629 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 630 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 631 csBundle(2 * i + 1).lsrc(2) := dest + i.U 632 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 633 csBundle(2 * i + 1).uopIdx := (2 * i).U 634 if (2 * i + 2 < MAX_VLMUL * 2) { 635 csBundle(2 * i + 2).srcType(0) := SrcType.fp 636 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 637 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 638 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 639 csBundle(2 * i + 2).ldest := dest + i.U 640 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 641 } 642 } 643 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 644 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 645 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 646 } 647 is(UopSplitType.VEC_FSLIDE1DOWN) { 648 //LMUL 649 for (i <- 0 until MAX_VLMUL) { 650 csBundle(2 * i).srcType(0) := SrcType.vp 651 csBundle(2 * i).srcType(1) := SrcType.vp 652 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 653 csBundle(2 * i).lsrc(1) := src2 + i.U 654 csBundle(2 * i).lsrc(2) := dest + i.U 655 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 656 csBundle(2 * i).uopIdx := (2 * i).U 657 csBundle(2 * i + 1).srcType(0) := SrcType.fp 658 csBundle(2 * i + 1).lsrc(0) := src1 659 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 660 csBundle(2 * i + 1).ldest := dest + i.U 661 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 662 } 663 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 664 csBundle(numOfUop - 1.U).lsrc(0) := src1 665 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 666 } 667 is(UopSplitType.VEC_VRED) { 668 when(simple.io.enq.vtype.vlmul === "b001".U) { 669 csBundle(0).srcType(2) := SrcType.DC 670 csBundle(0).lsrc(0) := src2 + 1.U 671 csBundle(0).lsrc(1) := src2 672 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 673 csBundle(0).uopIdx := 0.U 674 } 675 when(simple.io.enq.vtype.vlmul === "b010".U) { 676 csBundle(0).srcType(2) := SrcType.DC 677 csBundle(0).lsrc(0) := src2 + 1.U 678 csBundle(0).lsrc(1) := src2 679 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 680 csBundle(0).uopIdx := 0.U 681 682 csBundle(1).srcType(2) := SrcType.DC 683 csBundle(1).lsrc(0) := src2 + 3.U 684 csBundle(1).lsrc(1) := src2 + 2.U 685 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 686 csBundle(1).uopIdx := 1.U 687 688 csBundle(2).srcType(2) := SrcType.DC 689 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 690 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 691 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 692 csBundle(2).uopIdx := 2.U 693 } 694 when(simple.io.enq.vtype.vlmul === "b011".U) { 695 for (i <- 0 until MAX_VLMUL) { 696 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 697 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 698 csBundle(i).lsrc(1) := src2 + (i * 2).U 699 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 700 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 701 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 702 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 703 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 704 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 705 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 706 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 707 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 708 } 709 csBundle(i).srcType(2) := SrcType.DC 710 csBundle(i).uopIdx := i.U 711 } 712 } 713 when(simple.io.enq.vtype.vlmul.orR()) { 714 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 715 csBundle(numOfUop - 1.U).lsrc(0) := src1 716 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 717 csBundle(numOfUop - 1.U).lsrc(2) := dest 718 csBundle(numOfUop - 1.U).ldest := dest 719 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 720 } 721 } 722 is(UopSplitType.VEC_VFRED) { 723 val vlmul = simple.io.enq.vtype.vlmul 724 val vsew = simple.io.enq.vtype.vsew 725 when(vlmul === VLmul.m8){ 726 for (i <- 0 until 4) { 727 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 728 csBundle(i).lsrc(1) := src2 + (i * 2).U 729 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 730 csBundle(i).uopIdx := i.U 731 } 732 for (i <- 4 until 6) { 733 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 734 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 735 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 736 csBundle(i).uopIdx := i.U 737 } 738 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 739 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 740 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 741 csBundle(6).uopIdx := 6.U 742 when(vsew === VSew.e64) { 743 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 744 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 745 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 746 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 747 csBundle(7).uopIdx := 7.U 748 csBundle(8).lsrc(0) := src1 749 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 750 csBundle(8).ldest := dest 751 csBundle(8).uopIdx := 8.U 752 } 753 when(vsew === VSew.e32) { 754 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 755 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 756 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 757 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 758 csBundle(7).uopIdx := 7.U 759 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 760 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 761 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 762 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 763 csBundle(8).uopIdx := 8.U 764 csBundle(9).lsrc(0) := src1 765 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 766 csBundle(9).ldest := dest 767 csBundle(9).uopIdx := 9.U 768 } 769 when(vsew === VSew.e16) { 770 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 771 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 772 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 773 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 774 csBundle(7).uopIdx := 7.U 775 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 776 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 777 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 778 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 779 csBundle(8).uopIdx := 8.U 780 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 781 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 782 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 783 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 784 csBundle(9).uopIdx := 9.U 785 csBundle(10).lsrc(0) := src1 786 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 787 csBundle(10).ldest := dest 788 csBundle(10).uopIdx := 10.U 789 } 790 } 791 when(vlmul === VLmul.m4) { 792 for (i <- 0 until 2) { 793 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 794 csBundle(i).lsrc(1) := src2 + (i * 2).U 795 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 796 csBundle(i).uopIdx := i.U 797 } 798 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 799 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 800 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 801 csBundle(2).uopIdx := 2.U 802 when(vsew === VSew.e64) { 803 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 804 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 805 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 806 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 807 csBundle(3).uopIdx := 3.U 808 csBundle(4).lsrc(0) := src1 809 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 810 csBundle(4).ldest := dest 811 csBundle(4).uopIdx := 4.U 812 } 813 when(vsew === VSew.e32) { 814 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 815 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 816 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 817 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 818 csBundle(3).uopIdx := 3.U 819 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 820 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 821 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 822 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 823 csBundle(4).uopIdx := 4.U 824 csBundle(5).lsrc(0) := src1 825 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 826 csBundle(5).ldest := dest 827 csBundle(5).uopIdx := 5.U 828 } 829 when(vsew === VSew.e16) { 830 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 831 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 832 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 833 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 834 csBundle(3).uopIdx := 3.U 835 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 836 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 837 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 838 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 839 csBundle(4).uopIdx := 4.U 840 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 841 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 842 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 843 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 844 csBundle(5).uopIdx := 5.U 845 csBundle(6).lsrc(0) := src1 846 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 847 csBundle(6).ldest := dest 848 csBundle(6).uopIdx := 6.U 849 } 850 } 851 when(vlmul === VLmul.m2) { 852 csBundle(0).lsrc(0) := src2 + 1.U 853 csBundle(0).lsrc(1) := src2 + 0.U 854 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 855 csBundle(0).uopIdx := 0.U 856 when(vsew === VSew.e64) { 857 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 858 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 859 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 860 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 861 csBundle(1).uopIdx := 1.U 862 csBundle(2).lsrc(0) := src1 863 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 864 csBundle(2).ldest := dest 865 csBundle(2).uopIdx := 2.U 866 } 867 when(vsew === VSew.e32) { 868 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 869 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 870 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 871 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 872 csBundle(1).uopIdx := 1.U 873 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 874 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 875 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 876 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 877 csBundle(2).uopIdx := 2.U 878 csBundle(3).lsrc(0) := src1 879 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 880 csBundle(3).ldest := dest 881 csBundle(3).uopIdx := 3.U 882 } 883 when(vsew === VSew.e16) { 884 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 885 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 886 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 887 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 888 csBundle(1).uopIdx := 1.U 889 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 890 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 891 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 892 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 893 csBundle(2).uopIdx := 2.U 894 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 895 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 896 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 897 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 898 csBundle(3).uopIdx := 3.U 899 csBundle(4).lsrc(0) := src1 900 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 901 csBundle(4).ldest := dest 902 csBundle(4).uopIdx := 4.U 903 } 904 } 905 when(vlmul === VLmul.m1) { 906 when(vsew === VSew.e64) { 907 csBundle(0).lsrc(0) := src2 908 csBundle(0).lsrc(1) := src2 909 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 910 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 911 csBundle(0).uopIdx := 0.U 912 csBundle(1).lsrc(0) := src1 913 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 914 csBundle(1).ldest := dest 915 csBundle(1).uopIdx := 1.U 916 } 917 when(vsew === VSew.e32) { 918 csBundle(0).lsrc(0) := src2 919 csBundle(0).lsrc(1) := src2 920 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 921 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 922 csBundle(0).uopIdx := 0.U 923 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 924 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 925 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 926 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 927 csBundle(1).uopIdx := 1.U 928 csBundle(2).lsrc(0) := src1 929 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 930 csBundle(2).ldest := dest 931 csBundle(2).uopIdx := 2.U 932 } 933 when(vsew === VSew.e16) { 934 csBundle(0).lsrc(0) := src2 935 csBundle(0).lsrc(1) := src2 936 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 937 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 938 csBundle(0).uopIdx := 0.U 939 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 940 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 941 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 942 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 943 csBundle(1).uopIdx := 1.U 944 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 945 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 946 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 947 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 948 csBundle(2).uopIdx := 2.U 949 csBundle(3).lsrc(0) := src1 950 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 951 csBundle(3).ldest := dest 952 csBundle(3).uopIdx := 3.U 953 } 954 } 955 when(vlmul === VLmul.mf2) { 956 when(vsew === VSew.e32) { 957 csBundle(0).lsrc(0) := src2 958 csBundle(0).lsrc(1) := src2 959 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 960 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 961 csBundle(0).uopIdx := 0.U 962 csBundle(1).lsrc(0) := src1 963 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 964 csBundle(1).ldest := dest 965 csBundle(1).uopIdx := 1.U 966 } 967 when(vsew === VSew.e16) { 968 csBundle(0).lsrc(0) := src2 969 csBundle(0).lsrc(1) := src2 970 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 971 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 972 csBundle(0).uopIdx := 0.U 973 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 974 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 975 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 976 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 977 csBundle(1).uopIdx := 1.U 978 csBundle(2).lsrc(0) := src1 979 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 980 csBundle(2).ldest := dest 981 csBundle(2).uopIdx := 2.U 982 } 983 } 984 when(vlmul === VLmul.mf4) { 985 when(vsew === VSew.e16) { 986 csBundle(0).lsrc(0) := src2 987 csBundle(0).lsrc(1) := src2 988 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 989 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 990 csBundle(0).uopIdx := 0.U 991 csBundle(1).lsrc(0) := src1 992 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 993 csBundle(1).ldest := dest 994 csBundle(1).uopIdx := 1.U 995 } 996 } 997 } 998 999 is(UopSplitType.VEC_VFREDOSUM) { 1000 import yunsuan.VfaluType 1001 val vlmul = simple.io.enq.vtype.vlmul 1002 val vsew = simple.io.enq.vtype.vsew 1003 val isWiden = decodedInstsSimple.fuOpType === VfaluType.vfwredosum 1004 when(vlmul === VLmul.m8) { 1005 when(vsew === VSew.e64) { 1006 val vlmax = 16 1007 for (i <- 0 until vlmax) { 1008 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1009 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1010 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1011 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1012 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1013 csBundle(i).uopIdx := i.U 1014 } 1015 } 1016 when(vsew === VSew.e32) { 1017 val vlmax = 32 1018 for (i <- 0 until vlmax) { 1019 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1020 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1021 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1022 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1023 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1024 csBundle(i).uopIdx := i.U 1025 } 1026 } 1027 when(vsew === VSew.e16) { 1028 val vlmax = 64 1029 for (i <- 0 until vlmax) { 1030 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1031 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1032 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1033 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1034 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1035 csBundle(i).uopIdx := i.U 1036 } 1037 } 1038 } 1039 when(vlmul === VLmul.m4) { 1040 when(vsew === VSew.e64) { 1041 val vlmax = 8 1042 for (i <- 0 until vlmax) { 1043 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1044 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1045 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1046 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1047 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1048 csBundle(i).uopIdx := i.U 1049 } 1050 } 1051 when(vsew === VSew.e32) { 1052 val vlmax = 16 1053 for (i <- 0 until vlmax) { 1054 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1055 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1056 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1057 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1058 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1059 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1060 csBundle(i).uopIdx := i.U 1061 } 1062 } 1063 when(vsew === VSew.e16) { 1064 val vlmax = 32 1065 for (i <- 0 until vlmax) { 1066 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1067 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1068 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1069 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1070 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1071 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1072 csBundle(i).uopIdx := i.U 1073 } 1074 } 1075 } 1076 when(vlmul === VLmul.m2) { 1077 when(vsew === VSew.e64) { 1078 val vlmax = 4 1079 for (i <- 0 until vlmax) { 1080 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1081 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1082 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1083 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1084 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1085 csBundle(i).uopIdx := i.U 1086 } 1087 } 1088 when(vsew === VSew.e32) { 1089 val vlmax = 8 1090 for (i <- 0 until vlmax) { 1091 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1092 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1093 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1094 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1095 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1096 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1097 csBundle(i).uopIdx := i.U 1098 } 1099 } 1100 when(vsew === VSew.e16) { 1101 val vlmax = 16 1102 for (i <- 0 until vlmax) { 1103 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1104 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1105 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1106 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1107 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1108 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1109 csBundle(i).uopIdx := i.U 1110 } 1111 } 1112 } 1113 when(vlmul === VLmul.m1) { 1114 when(vsew === VSew.e64) { 1115 val vlmax = 2 1116 for (i <- 0 until vlmax) { 1117 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1118 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1119 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1120 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1121 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1122 csBundle(i).uopIdx := i.U 1123 } 1124 } 1125 when(vsew === VSew.e32) { 1126 val vlmax = 4 1127 for (i <- 0 until vlmax) { 1128 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1129 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1130 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1131 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1132 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1133 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1134 csBundle(i).uopIdx := i.U 1135 } 1136 } 1137 when(vsew === VSew.e16) { 1138 val vlmax = 8 1139 for (i <- 0 until vlmax) { 1140 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1141 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1142 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1143 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1144 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1145 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1146 csBundle(i).uopIdx := i.U 1147 } 1148 } 1149 } 1150 when(vlmul === VLmul.mf2) { 1151 when(vsew === VSew.e32) { 1152 val vlmax = 2 1153 for (i <- 0 until vlmax) { 1154 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1155 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1156 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1157 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1158 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1159 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1160 csBundle(i).uopIdx := i.U 1161 } 1162 } 1163 when(vsew === VSew.e16) { 1164 val vlmax = 4 1165 for (i <- 0 until vlmax) { 1166 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1167 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1168 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1169 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1170 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1171 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1172 csBundle(i).uopIdx := i.U 1173 } 1174 } 1175 } 1176 when(vlmul === VLmul.mf4) { 1177 when(vsew === VSew.e16) { 1178 val vlmax = 2 1179 for (i <- 0 until vlmax) { 1180 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1181 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1182 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1183 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1184 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1185 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1186 csBundle(i).uopIdx := i.U 1187 } 1188 } 1189 } 1190 } 1191 is(UopSplitType.VEC_SLIDEUP) { 1192 // FMV.D.X 1193 csBundle(0).srcType(0) := SrcType.reg 1194 csBundle(0).srcType(1) := SrcType.imm 1195 csBundle(0).lsrc(1) := 0.U 1196 csBundle(0).ldest := FP_TMP_REG_MV.U 1197 csBundle(0).fuType := FuType.i2f.U 1198 csBundle(0).rfWen := false.B 1199 csBundle(0).fpWen := true.B 1200 csBundle(0).vecWen := false.B 1201 csBundle(0).fpu.isAddSub := false.B 1202 csBundle(0).fpu.typeTagIn := FPU.D 1203 csBundle(0).fpu.typeTagOut := FPU.D 1204 csBundle(0).fpu.fromInt := true.B 1205 csBundle(0).fpu.wflags := false.B 1206 csBundle(0).fpu.fpWen := true.B 1207 csBundle(0).fpu.div := false.B 1208 csBundle(0).fpu.sqrt := false.B 1209 csBundle(0).fpu.fcvt := false.B 1210 // LMUL 1211 for (i <- 0 until MAX_VLMUL) 1212 for (j <- 0 to i) { 1213 val old_vd = if (j == 0) { 1214 dest + i.U 1215 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1216 val vd = if (j == i) { 1217 dest + i.U 1218 } else (VECTOR_TMP_REG_LMUL + j).U 1219 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 1220 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 1221 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1222 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1223 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1224 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1225 } 1226 } 1227 1228 is(UopSplitType.VEC_ISLIDEUP) { 1229 // LMUL 1230 for (i <- 0 until MAX_VLMUL) 1231 for (j <- 0 to i) { 1232 val old_vd = if (j == 0) { 1233 dest + i.U 1234 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1235 val vd = if (j == i) { 1236 dest + i.U 1237 } else (VECTOR_TMP_REG_LMUL + j).U 1238 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 1239 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 1240 csBundle(i * (i + 1) / 2 + j).ldest := vd 1241 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 1242 } 1243 } 1244 1245 is(UopSplitType.VEC_SLIDEDOWN) { 1246 // FMV.D.X 1247 csBundle(0).srcType(0) := SrcType.reg 1248 csBundle(0).srcType(1) := SrcType.imm 1249 csBundle(0).lsrc(1) := 0.U 1250 csBundle(0).ldest := FP_TMP_REG_MV.U 1251 csBundle(0).fuType := FuType.i2f.U 1252 csBundle(0).rfWen := false.B 1253 csBundle(0).fpWen := true.B 1254 csBundle(0).vecWen := false.B 1255 csBundle(0).fpu.isAddSub := false.B 1256 csBundle(0).fpu.typeTagIn := FPU.D 1257 csBundle(0).fpu.typeTagOut := FPU.D 1258 csBundle(0).fpu.fromInt := true.B 1259 csBundle(0).fpu.wflags := false.B 1260 csBundle(0).fpu.fpWen := true.B 1261 csBundle(0).fpu.div := false.B 1262 csBundle(0).fpu.sqrt := false.B 1263 csBundle(0).fpu.fcvt := false.B 1264 // LMUL 1265 for (i <- 0 until MAX_VLMUL) 1266 for (j <- (0 to i).reverse) { 1267 when(i.U < lmul) { 1268 val old_vd = if (j == 0) { 1269 dest + lmul - 1.U - i.U 1270 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1271 val vd = if (j == i) { 1272 dest + lmul - 1.U - i.U 1273 } else (VECTOR_TMP_REG_LMUL + j).U 1274 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 1275 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 1276 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1277 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1278 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1279 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1280 } 1281 } 1282 } 1283 1284 is(UopSplitType.VEC_ISLIDEDOWN) { 1285 // LMUL 1286 for (i <- 0 until MAX_VLMUL) 1287 for (j <- (0 to i).reverse) { 1288 when(i.U < lmul) { 1289 val old_vd = if (j == 0) { 1290 dest + lmul - 1.U - i.U 1291 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1292 val vd = if (j == i) { 1293 dest + lmul - 1.U - i.U 1294 } else (VECTOR_TMP_REG_LMUL + j).U 1295 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1296 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1297 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1298 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 1299 } 1300 } 1301 } 1302 1303 is(UopSplitType.VEC_M0X) { 1304 // LMUL 1305 for (i <- 0 until MAX_VLMUL) { 1306 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1307 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1308 csBundle(i).srcType(0) := srcType0 1309 csBundle(i).srcType(1) := SrcType.vp 1310 csBundle(i).rfWen := false.B 1311 csBundle(i).vecWen := true.B 1312 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1313 csBundle(i).lsrc(1) := src2 1314 // csBundle(i).lsrc(2) := dest + i.U DontCare 1315 csBundle(i).ldest := ldest 1316 csBundle(i).uopIdx := i.U 1317 } 1318 csBundle(lmul - 1.U).vecWen := false.B 1319 csBundle(lmul - 1.U).fpWen := true.B 1320 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 1321 // FMV_X_D 1322 csBundle(lmul).srcType(0) := SrcType.fp 1323 csBundle(lmul).srcType(1) := SrcType.imm 1324 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 1325 csBundle(lmul).lsrc(1) := 0.U 1326 csBundle(lmul).ldest := dest 1327 csBundle(lmul).fuType := FuType.fmisc.U 1328 csBundle(lmul).rfWen := true.B 1329 csBundle(lmul).fpWen := false.B 1330 csBundle(lmul).vecWen := false.B 1331 csBundle(lmul).fpu.isAddSub := false.B 1332 csBundle(lmul).fpu.typeTagIn := FPU.D 1333 csBundle(lmul).fpu.typeTagOut := FPU.D 1334 csBundle(lmul).fpu.fromInt := false.B 1335 csBundle(lmul).fpu.wflags := false.B 1336 csBundle(lmul).fpu.fpWen := false.B 1337 csBundle(lmul).fpu.div := false.B 1338 csBundle(lmul).fpu.sqrt := false.B 1339 csBundle(lmul).fpu.fcvt := false.B 1340 } 1341 1342 is(UopSplitType.VEC_MVV) { 1343 // LMUL 1344 for (i <- 0 until MAX_VLMUL) { 1345 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1346 csBundle(i * 2 + 0).srcType(0) := srcType0 1347 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1348 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1349 csBundle(i * 2 + 0).lsrc(1) := src2 1350 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1351 csBundle(i * 2 + 0).ldest := dest + i.U 1352 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1353 1354 csBundle(i * 2 + 1).srcType(0) := srcType0 1355 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1356 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1357 csBundle(i * 2 + 1).lsrc(1) := src2 1358 // csBundle(i).lsrc(2) := dest + i.U DontCare 1359 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1360 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1361 } 1362 } 1363 1364 is(UopSplitType.VEC_M0X_VFIRST) { 1365 // LMUL 1366 csBundle(0).rfWen := false.B 1367 csBundle(0).fpWen := true.B 1368 csBundle(0).ldest := FP_TMP_REG_MV.U 1369 // FMV_X_D 1370 csBundle(1).srcType(0) := SrcType.fp 1371 csBundle(1).srcType(1) := SrcType.imm 1372 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 1373 csBundle(1).lsrc(1) := 0.U 1374 csBundle(1).ldest := dest 1375 csBundle(1).fuType := FuType.fmisc.U 1376 csBundle(1).rfWen := true.B 1377 csBundle(1).fpWen := false.B 1378 csBundle(1).vecWen := false.B 1379 csBundle(1).fpu.isAddSub := false.B 1380 csBundle(1).fpu.typeTagIn := FPU.D 1381 csBundle(1).fpu.typeTagOut := FPU.D 1382 csBundle(1).fpu.fromInt := false.B 1383 csBundle(1).fpu.wflags := false.B 1384 csBundle(1).fpu.fpWen := false.B 1385 csBundle(1).fpu.div := false.B 1386 csBundle(1).fpu.sqrt := false.B 1387 csBundle(1).fpu.fcvt := false.B 1388 } 1389 is(UopSplitType.VEC_VWW) { 1390 for (i <- 0 until MAX_VLMUL*2) { 1391 when(i.U < lmul){ 1392 csBundle(i).srcType(2) := SrcType.DC 1393 csBundle(i).lsrc(0) := src2 + i.U 1394 csBundle(i).lsrc(1) := src2 + i.U 1395 // csBundle(i).lsrc(2) := dest + (2 * i).U 1396 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1397 csBundle(i).uopIdx := i.U 1398 } otherwise { 1399 csBundle(i).srcType(2) := SrcType.DC 1400 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1401 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1402 // csBundle(i).lsrc(2) := dest + (2 * i).U 1403 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1404 csBundle(i).uopIdx := i.U 1405 } 1406 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1407 csBundle(numOfUop-1.U).lsrc(0) := src1 1408 csBundle(numOfUop-1.U).lsrc(2) := dest 1409 csBundle(numOfUop-1.U).ldest := dest 1410 } 1411 } 1412 is(UopSplitType.VEC_RGATHER) { 1413 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1414 for (i <- 0 until len) 1415 for (j <- 0 until len) { 1416 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1417 // csBundle(i * len + j).srcType(1) := SrcType.vp 1418 // csBundle(i * len + j).srcType(2) := SrcType.vp 1419 csBundle(i * len + j).lsrc(0) := src1 + i.U 1420 csBundle(i * len + j).lsrc(1) := src2 + j.U 1421 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1422 csBundle(i * len + j).lsrc(2) := vd_old 1423 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1424 csBundle(i * len + j).ldest := vd 1425 csBundle(i * len + j).uopIdx := (i * len + j).U 1426 } 1427 } 1428 switch(simple.io.enq.vtype.vlmul) { 1429 is("b001".U ){ 1430 genCsBundle_VEC_RGATHER(2) 1431 } 1432 is("b010".U ){ 1433 genCsBundle_VEC_RGATHER(4) 1434 } 1435 is("b011".U ){ 1436 genCsBundle_VEC_RGATHER(8) 1437 } 1438 } 1439 } 1440 is(UopSplitType.VEC_RGATHER_VX) { 1441 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1442 for (i <- 0 until len) 1443 for (j <- 0 until len) { 1444 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 1445 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1446 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1447 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 1448 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1449 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1450 csBundle(i * len + j + 1).lsrc(2) := vd_old 1451 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1452 csBundle(i * len + j + 1).ldest := vd 1453 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1454 } 1455 } 1456 // FMV.D.X 1457 csBundle(0).srcType(0) := SrcType.reg 1458 csBundle(0).srcType(1) := SrcType.imm 1459 csBundle(0).lsrc(1) := 0.U 1460 csBundle(0).ldest := FP_TMP_REG_MV.U 1461 csBundle(0).fuType := FuType.i2f.U 1462 csBundle(0).rfWen := false.B 1463 csBundle(0).fpWen := true.B 1464 csBundle(0).vecWen := false.B 1465 csBundle(0).fpu.isAddSub := false.B 1466 csBundle(0).fpu.typeTagIn := FPU.D 1467 csBundle(0).fpu.typeTagOut := FPU.D 1468 csBundle(0).fpu.fromInt := true.B 1469 csBundle(0).fpu.wflags := false.B 1470 csBundle(0).fpu.fpWen := true.B 1471 csBundle(0).fpu.div := false.B 1472 csBundle(0).fpu.sqrt := false.B 1473 csBundle(0).fpu.fcvt := false.B 1474 switch(simple.io.enq.vtype.vlmul) { 1475 is("b000".U ){ 1476 genCsBundle_RGATHER_VX(1) 1477 } 1478 is("b001".U ){ 1479 genCsBundle_RGATHER_VX(2) 1480 } 1481 is("b010".U ){ 1482 genCsBundle_RGATHER_VX(4) 1483 } 1484 is("b011".U ){ 1485 genCsBundle_RGATHER_VX(8) 1486 } 1487 } 1488 } 1489 is(UopSplitType.VEC_RGATHEREI16) { 1490 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1491 for (i <- 0 until len) 1492 for (j <- 0 until len) { 1493 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1494 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1495 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1496 // csBundle(i * len + j).srcType(1) := SrcType.vp 1497 // csBundle(i * len + j).srcType(2) := SrcType.vp 1498 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1499 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1500 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1501 csBundle((i * len + j)*2+0).ldest := vd0 1502 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1503 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1504 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1505 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1506 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1507 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1508 csBundle((i * len + j)*2+1).ldest := vd1 1509 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1510 } 1511 } 1512 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1513 for (i <- 0 until len) 1514 for (j <- 0 until len) { 1515 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1516 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1517 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1518 // csBundle(i * len + j).srcType(1) := SrcType.vp 1519 // csBundle(i * len + j).srcType(2) := SrcType.vp 1520 csBundle(i * len + j).lsrc(0) := src1 + i.U 1521 csBundle(i * len + j).lsrc(1) := src2 + j.U 1522 csBundle(i * len + j).lsrc(2) := vd_old 1523 csBundle(i * len + j).ldest := vd 1524 csBundle(i * len + j).uopIdx := (i * len + j).U 1525 } 1526 } 1527 switch(simple.io.enq.vtype.vlmul) { 1528 is("b000".U ){ 1529 when(!simple.io.enq.vtype.vsew.orR){ 1530 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1531 } .otherwise{ 1532 genCsBundle_VEC_RGATHEREI16(1) 1533 } 1534 } 1535 is("b001".U) { 1536 when(!simple.io.enq.vtype.vsew.orR) { 1537 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1538 }.otherwise { 1539 genCsBundle_VEC_RGATHEREI16(2) 1540 } 1541 } 1542 is("b010".U) { 1543 when(!simple.io.enq.vtype.vsew.orR) { 1544 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1545 }.otherwise { 1546 genCsBundle_VEC_RGATHEREI16(4) 1547 } 1548 } 1549 is("b011".U) { 1550 genCsBundle_VEC_RGATHEREI16(8) 1551 } 1552 } 1553 } 1554 is(UopSplitType.VEC_COMPRESS) { 1555 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1556 for (i <- 0 until len){ 1557 val jlen = if (i == len-1) i+1 else i+2 1558 for (j <- 0 until jlen) { 1559 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1560 val vd = if(i==len-1) (dest + j.U) else{ 1561 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1562 } 1563 val src23Type = if (j == i+1) DontCare else SrcType.vp 1564 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1565 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1566 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1567 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1568 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1569 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1570 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1571 csBundle(i*(i+3)/2 + j).ldest := vd 1572 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1573 } 1574 } 1575 } 1576 switch(simple.io.enq.vtype.vlmul) { 1577 is("b001".U ){ 1578 genCsBundle_VEC_COMPRESS(2) 1579 } 1580 is("b010".U ){ 1581 genCsBundle_VEC_COMPRESS(4) 1582 } 1583 is("b011".U ){ 1584 genCsBundle_VEC_COMPRESS(8) 1585 } 1586 } 1587 } 1588 is(UopSplitType.VEC_US_LD) { 1589 /* 1590 FMV.D.X 1591 */ 1592 csBundle(0).srcType(0) := SrcType.reg 1593 csBundle(0).srcType(1) := SrcType.imm 1594 csBundle(0).lsrc(1) := 0.U 1595 csBundle(0).ldest := FP_TMP_REG_MV.U 1596 csBundle(0).fuType := FuType.i2f.U 1597 csBundle(0).rfWen := false.B 1598 csBundle(0).fpWen := true.B 1599 csBundle(0).vecWen := false.B 1600 csBundle(0).fpu.isAddSub := false.B 1601 csBundle(0).fpu.typeTagIn := FPU.D 1602 csBundle(0).fpu.typeTagOut := FPU.D 1603 csBundle(0).fpu.fromInt := true.B 1604 csBundle(0).fpu.wflags := false.B 1605 csBundle(0).fpu.fpWen := true.B 1606 csBundle(0).fpu.div := false.B 1607 csBundle(0).fpu.sqrt := false.B 1608 csBundle(0).fpu.fcvt := false.B 1609 //LMUL 1610 for (i <- 0 until MAX_VLMUL) { 1611 csBundle(i + 1).srcType(0) := SrcType.fp 1612 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1613 csBundle(i + 1).ldest := dest + i.U 1614 csBundle(i + 1).uopIdx := i.U 1615 } 1616 } 1617 } 1618 1619 //uops dispatch 1620 val s_normal :: s_ext :: Nil = Enum(2) 1621 val state = RegInit(s_normal) 1622 val state_next = WireDefault(state) 1623 val uopRes = RegInit(0.U) 1624 1625 //readyFromRename Counter 1626 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1627 1628 switch(state) { 1629 is(s_normal) { 1630 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1631 } 1632 is(s_ext) { 1633 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1634 } 1635 } 1636 1637 state := state_next 1638 1639 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1640 val uopResJudge = Mux(state === s_normal, 1641 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1642 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1643 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1644 1645 for(i <- 0 until RenameWidth) { 1646 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1647 (state === s_normal) -> csBundle(i), 1648 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1649 )) 1650 } 1651 1652 1653 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1654 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1655 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1656 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1657 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1658 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1659 notInfVec(0) := true.B 1660 1661 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1662 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1663 1.U) 1664 validToRename.zipWithIndex.foreach{ 1665 case(dst, i) => 1666 dst := MuxCase(false.B, Seq( 1667 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1668 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1669 )) 1670 } 1671 1672 readyToIBuf.zipWithIndex.foreach { 1673 case (dst, i) => 1674 dst := MuxCase(true.B, Seq( 1675 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1676 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1677 )) 1678 } 1679 1680 io.deq.decodedInsts := decodedInsts 1681 io.deq.isVset := isVsetSimple 1682 io.deq.complexNum := complexNum 1683 io.deq.validToRename := validToRename 1684 io.deq.readyToIBuf := readyToIBuf 1685 1686} 1687