1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41} 42 43class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 44 val enq = new Bundle { val staticInst = Input(new StaticInst) } 45 val vtype = Input(new VType) 46 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 47 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 48 val readyFromRename = Input(Vec(RenameWidth, Bool())) 49 val deq = new Bundle { 50 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 51 val isVset = Output(Bool()) 52 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 53 val validToRename = Output(Vec(RenameWidth, Bool())) 54 val complexNum = Output(UInt(3.W)) 55 } 56 val csrCtrl = Input(new CustomCSRCtrlIO) 57} 58 59/** 60 * @author zly 61 */ 62class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 63 val io = IO(new DecodeUnitCompIO) 64 65 val maxUopSize = MaxUopSize 66 //input bits 67 val staticInst = Wire(new StaticInst) 68 69 staticInst := io.enq.staticInst 70 71 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 72 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 73 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 74 val width = staticInst.instr(14, 12) //Vector LS eew 75 val eew = Cat(0.U(1.W), width(1, 0)) 76 77 //output bits 78 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 79 val validToRename = Wire(Vec(RenameWidth, Bool())) 80 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 81 val complexNum = Wire(UInt(3.W)) 82 83 //output of DecodeUnit 84 val decodedInsts_u = Wire(new DecodedInst) 85 val isVset_u = Wire(Bool()) 86 87 //pre decode 88 val simple = Module(new DecodeUnit) 89 simple.io.enq.ctrlFlow := staticInst 90 simple.io.enq.vtype := io.vtype 91 simple.io.csrCtrl := io.csrCtrl 92 decodedInsts_u := simple.io.deq.decodedInst 93 isVset_u := simple.io.deq.decodedInst.isVset 94 when(isVset_u) { 95 when(dest === 0.U && src1 === 0.U) { 96 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 97 }.elsewhen(src1 === 0.U) { 98 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 99 } 100 when(io.vtype.illegal){ 101 decodedInsts_u.flushPipe := true.B 102 } 103 } 104 //Type of uop Div 105 val typeOfDiv = decodedInsts_u.uopSplitType 106 107 val sew = Cat(0.U(1.W), simple.io.enq.vtype.vsew) 108 val vlmul = simple.io.enq.vtype.vlmul 109 110 //LMUL 111 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 112 "b001".U -> 2.U, 113 "b010".U -> 4.U, 114 "b011".U -> 8.U 115 )) 116 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 117 "b001".U -> 3.U, 118 "b010".U -> 10.U, 119 "b011".U -> 36.U 120 )) 121 val vemul : UInt = eew.asUInt + 1.U + vlmul.asUInt + ~sew.asUInt 122 val emul = MuxLookup(vemul, 1.U(4.W), Array( 123 "b001".U -> 2.U, 124 "b010".U -> 4.U, 125 "b011".U -> 8.U 126 )) //TODO : eew and emul illegal exception need to be handled 127 128 //number of uop 129 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 130 UopSplitType.VEC_0XV -> 2.U, 131 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 132 Mux(src1 =/= 0.U, 1.U, 133 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 134 UopSplitType.VEC_VVV -> lmul, 135 UopSplitType.VEC_EXT2 -> lmul, 136 UopSplitType.VEC_EXT4 -> lmul, 137 UopSplitType.VEC_EXT8 -> lmul, 138 UopSplitType.VEC_VVM -> lmul, 139 UopSplitType.VEC_VXM -> (lmul +& 1.U), 140 UopSplitType.VEC_VXV -> (lmul +& 1.U), 141 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 142 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 143 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 144 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 145 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 146 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 147 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 148 UopSplitType.VEC_FSLIDE1UP -> lmul, 149 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 150 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 151 UopSplitType.VEC_VRED -> lmul, 152 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 153 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 154 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 155 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 156 UopSplitType.VEC_M0X -> (lmul +& 1.U), 157 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 158 UopSplitType.VEC_M0X_VFIRST -> 2.U, 159 UopSplitType.VEC_US_LD -> (emul +& 1.U), 160 )) 161 162 //uop div up to maxUopSize 163 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 164 csBundle.map { case dst => 165 dst := decodedInsts_u 166 dst.firstUop := false.B 167 dst.lastUop := false.B 168 } 169 170 csBundle(0).numUops := numOfUop 171 csBundle(0).firstUop := true.B 172 csBundle(numOfUop - 1.U).lastUop := true.B 173 174 switch(typeOfDiv) { 175 is(UopSplitType.DIR) { 176 when(isVset_u) { 177 when(dest =/= 0.U) { 178 csBundle(0).fuType := FuType.vsetiwi.U 179 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 180 csBundle(0).flushPipe := false.B 181 csBundle(0).rfWen := true.B 182 csBundle(0).vecWen := false.B 183 csBundle(1).ldest := VCONFIG_IDX.U 184 csBundle(1).rfWen := false.B 185 csBundle(1).vecWen := true.B 186 }.elsewhen(src1 =/= 0.U) { 187 csBundle(0).ldest := VCONFIG_IDX.U 188 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 189 csBundle(0).fuType := FuType.vsetfwf.U 190 csBundle(0).srcType(0) := SrcType.vp 191 csBundle(0).lsrc(0) := VCONFIG_IDX.U 192 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 193 csBundle(0).srcType(0) := SrcType.reg 194 csBundle(0).srcType(1) := SrcType.imm 195 csBundle(0).lsrc(1) := 0.U 196 csBundle(0).ldest := FP_TMP_REG_MV.U 197 csBundle(0).fuType := FuType.i2f.U 198 csBundle(0).rfWen := false.B 199 csBundle(0).fpWen := true.B 200 csBundle(0).vecWen := false.B 201 csBundle(0).fpu.isAddSub := false.B 202 csBundle(0).fpu.typeTagIn := FPU.D 203 csBundle(0).fpu.typeTagOut := FPU.D 204 csBundle(0).fpu.fromInt := true.B 205 csBundle(0).fpu.wflags := false.B 206 csBundle(0).fpu.fpWen := true.B 207 csBundle(0).fpu.div := false.B 208 csBundle(0).fpu.sqrt := false.B 209 csBundle(0).fpu.fcvt := false.B 210 csBundle(0).flushPipe := false.B 211 csBundle(1).fuType := FuType.vsetfwf.U 212 csBundle(1).srcType(0) := SrcType.vp 213 csBundle(1).lsrc(0) := VCONFIG_IDX.U 214 csBundle(1).srcType(1) := SrcType.fp 215 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 216 csBundle(1).ldest := VCONFIG_IDX.U 217 } 218 } 219 } 220 is(UopSplitType.VEC_VVV) { 221 for (i <- 0 until MAX_VLMUL) { 222 csBundle(i).lsrc(0) := src1 + i.U 223 csBundle(i).lsrc(1) := src2 + i.U 224 csBundle(i).lsrc(2) := dest + i.U 225 csBundle(i).ldest := dest + i.U 226 csBundle(i).uopIdx := i.U 227 } 228 } 229 is(UopSplitType.VEC_EXT2) { 230 for (i <- 0 until MAX_VLMUL / 2) { 231 csBundle(2 * i).lsrc(1) := src2 + i.U 232 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 233 csBundle(2 * i).ldest := dest + (2 * i).U 234 csBundle(2 * i).uopIdx := (2 * i).U 235 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 236 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 237 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 238 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 239 } 240 } 241 is(UopSplitType.VEC_EXT4) { 242 for (i <- 0 until MAX_VLMUL / 4) { 243 csBundle(4 * i).lsrc(1) := src2 + i.U 244 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 245 csBundle(4 * i).ldest := dest + (4 * i).U 246 csBundle(4 * i).uopIdx := (4 * i).U 247 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 248 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 249 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 250 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 251 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 252 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 253 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 254 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 255 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 256 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 257 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 258 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 259 } 260 } 261 is(UopSplitType.VEC_EXT8) { 262 for (i <- 0 until MAX_VLMUL) { 263 csBundle(i).lsrc(1) := src2 264 csBundle(i).lsrc(2) := dest + i.U 265 csBundle(i).ldest := dest + i.U 266 csBundle(i).uopIdx := i.U 267 } 268 } 269 is(UopSplitType.VEC_0XV) { 270 /* 271 FMV.D.X 272 */ 273 csBundle(0).srcType(0) := SrcType.reg 274 csBundle(0).srcType(1) := SrcType.imm 275 csBundle(0).lsrc(1) := 0.U 276 csBundle(0).ldest := FP_TMP_REG_MV.U 277 csBundle(0).fuType := FuType.i2f.U 278 csBundle(0).rfWen := false.B 279 csBundle(0).fpWen := true.B 280 csBundle(0).vecWen := false.B 281 csBundle(0).fpu.isAddSub := false.B 282 csBundle(0).fpu.typeTagIn := FPU.D 283 csBundle(0).fpu.typeTagOut := FPU.D 284 csBundle(0).fpu.fromInt := true.B 285 csBundle(0).fpu.wflags := false.B 286 csBundle(0).fpu.fpWen := true.B 287 csBundle(0).fpu.div := false.B 288 csBundle(0).fpu.sqrt := false.B 289 csBundle(0).fpu.fcvt := false.B 290 /* 291 vfmv.s.f 292 */ 293 csBundle(1).srcType(0) := SrcType.fp 294 csBundle(1).srcType(1) := SrcType.vp 295 csBundle(1).srcType(2) := SrcType.vp 296 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 297 csBundle(1).lsrc(1) := 0.U 298 csBundle(1).lsrc(2) := dest 299 csBundle(1).ldest := dest 300 csBundle(1).fuType := FuType.vppu.U 301 csBundle(1).fuOpType := VpermType.dummy 302 csBundle(1).rfWen := false.B 303 csBundle(1).fpWen := false.B 304 csBundle(1).vecWen := true.B 305 } 306 is(UopSplitType.VEC_VXV) { 307 /* 308 FMV.D.X 309 */ 310 csBundle(0).srcType(0) := SrcType.reg 311 csBundle(0).srcType(1) := SrcType.imm 312 csBundle(0).lsrc(1) := 0.U 313 csBundle(0).ldest := FP_TMP_REG_MV.U 314 csBundle(0).fuType := FuType.i2f.U 315 csBundle(0).rfWen := false.B 316 csBundle(0).fpWen := true.B 317 csBundle(0).vecWen := false.B 318 csBundle(0).fpu.isAddSub := false.B 319 csBundle(0).fpu.typeTagIn := FPU.D 320 csBundle(0).fpu.typeTagOut := FPU.D 321 csBundle(0).fpu.fromInt := true.B 322 csBundle(0).fpu.wflags := false.B 323 csBundle(0).fpu.fpWen := true.B 324 csBundle(0).fpu.div := false.B 325 csBundle(0).fpu.sqrt := false.B 326 csBundle(0).fpu.fcvt := false.B 327 /* 328 LMUL 329 */ 330 for (i <- 0 until MAX_VLMUL) { 331 csBundle(i + 1).srcType(0) := SrcType.fp 332 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 333 csBundle(i + 1).lsrc(1) := src2 + i.U 334 csBundle(i + 1).lsrc(2) := dest + i.U 335 csBundle(i + 1).ldest := dest + i.U 336 csBundle(i + 1).uopIdx := i.U 337 } 338 } 339 is(UopSplitType.VEC_VVW) { 340 for (i <- 0 until MAX_VLMUL / 2) { 341 csBundle(2 * i).lsrc(0) := src1 + i.U 342 csBundle(2 * i).lsrc(1) := src2 + i.U 343 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 344 csBundle(2 * i).ldest := dest + (2 * i).U 345 csBundle(2 * i).uopIdx := (2 * i).U 346 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 347 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 348 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 349 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 350 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 351 } 352 } 353 is(UopSplitType.VEC_WVW) { 354 for (i <- 0 until MAX_VLMUL / 2) { 355 csBundle(2 * i).lsrc(0) := src1 + i.U 356 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 357 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 358 csBundle(2 * i).ldest := dest + (2 * i).U 359 csBundle(2 * i).uopIdx := (2 * i).U 360 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 361 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 362 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 363 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 364 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 365 } 366 } 367 is(UopSplitType.VEC_VXW) { 368 /* 369 FMV.D.X 370 */ 371 csBundle(0).srcType(0) := SrcType.reg 372 csBundle(0).srcType(1) := SrcType.imm 373 csBundle(0).lsrc(1) := 0.U 374 csBundle(0).ldest := FP_TMP_REG_MV.U 375 csBundle(0).fuType := FuType.i2f.U 376 csBundle(0).rfWen := false.B 377 csBundle(0).fpWen := true.B 378 csBundle(0).vecWen := false.B 379 csBundle(0).fpu.isAddSub := false.B 380 csBundle(0).fpu.typeTagIn := FPU.D 381 csBundle(0).fpu.typeTagOut := FPU.D 382 csBundle(0).fpu.fromInt := true.B 383 csBundle(0).fpu.wflags := false.B 384 csBundle(0).fpu.fpWen := true.B 385 csBundle(0).fpu.div := false.B 386 csBundle(0).fpu.sqrt := false.B 387 csBundle(0).fpu.fcvt := false.B 388 389 for (i <- 0 until MAX_VLMUL / 2) { 390 csBundle(2 * i + 1).srcType(0) := SrcType.fp 391 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 392 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 393 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 394 csBundle(2 * i + 1).ldest := dest + (2 * i).U 395 csBundle(2 * i + 1).uopIdx := (2 * i).U 396 csBundle(2 * i + 2).srcType(0) := SrcType.fp 397 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 398 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 399 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 400 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 401 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 402 } 403 } 404 is(UopSplitType.VEC_WXW) { 405 /* 406 FMV.D.X 407 */ 408 csBundle(0).srcType(0) := SrcType.reg 409 csBundle(0).srcType(1) := SrcType.imm 410 csBundle(0).lsrc(1) := 0.U 411 csBundle(0).ldest := FP_TMP_REG_MV.U 412 csBundle(0).fuType := FuType.i2f.U 413 csBundle(0).rfWen := false.B 414 csBundle(0).fpWen := true.B 415 csBundle(0).vecWen := false.B 416 csBundle(0).fpu.isAddSub := false.B 417 csBundle(0).fpu.typeTagIn := FPU.D 418 csBundle(0).fpu.typeTagOut := FPU.D 419 csBundle(0).fpu.fromInt := true.B 420 csBundle(0).fpu.wflags := false.B 421 csBundle(0).fpu.fpWen := true.B 422 csBundle(0).fpu.div := false.B 423 csBundle(0).fpu.sqrt := false.B 424 csBundle(0).fpu.fcvt := false.B 425 426 for (i <- 0 until MAX_VLMUL / 2) { 427 csBundle(2 * i + 1).srcType(0) := SrcType.fp 428 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 429 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 430 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 431 csBundle(2 * i + 1).ldest := dest + (2 * i).U 432 csBundle(2 * i + 1).uopIdx := (2 * i).U 433 csBundle(2 * i + 2).srcType(0) := SrcType.fp 434 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 435 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 436 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 437 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 438 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 439 } 440 } 441 is(UopSplitType.VEC_WVV) { 442 for (i <- 0 until MAX_VLMUL / 2) { 443 444 csBundle(2 * i).lsrc(0) := src1 + i.U 445 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 446 csBundle(2 * i).lsrc(2) := dest + i.U 447 csBundle(2 * i).ldest := dest + i.U 448 csBundle(2 * i).uopIdx := (2 * i).U 449 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 450 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 451 csBundle(2 * i + 1).lsrc(2) := dest + i.U 452 csBundle(2 * i + 1).ldest := dest + i.U 453 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 454 } 455 } 456 is(UopSplitType.VEC_WXV) { 457 /* 458 FMV.D.X 459 */ 460 csBundle(0).srcType(0) := SrcType.reg 461 csBundle(0).srcType(1) := SrcType.imm 462 csBundle(0).lsrc(1) := 0.U 463 csBundle(0).ldest := FP_TMP_REG_MV.U 464 csBundle(0).fuType := FuType.i2f.U 465 csBundle(0).rfWen := false.B 466 csBundle(0).fpWen := true.B 467 csBundle(0).vecWen := false.B 468 csBundle(0).fpu.isAddSub := false.B 469 csBundle(0).fpu.typeTagIn := FPU.D 470 csBundle(0).fpu.typeTagOut := FPU.D 471 csBundle(0).fpu.fromInt := true.B 472 csBundle(0).fpu.wflags := false.B 473 csBundle(0).fpu.fpWen := true.B 474 csBundle(0).fpu.div := false.B 475 csBundle(0).fpu.sqrt := false.B 476 csBundle(0).fpu.fcvt := false.B 477 478 for (i <- 0 until MAX_VLMUL / 2) { 479 csBundle(2 * i + 1).srcType(0) := SrcType.fp 480 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 481 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 482 csBundle(2 * i + 1).lsrc(2) := dest + i.U 483 csBundle(2 * i + 1).ldest := dest + i.U 484 csBundle(2 * i + 1).uopIdx := (2 * i).U 485 csBundle(2 * i + 2).srcType(0) := SrcType.fp 486 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 487 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 488 csBundle(2 * i + 2).lsrc(2) := dest + i.U 489 csBundle(2 * i + 2).ldest := dest + i.U 490 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 491 } 492 } 493 is(UopSplitType.VEC_VVM) { 494 csBundle(0).lsrc(2) := dest 495 csBundle(0).ldest := dest 496 csBundle(0).uopIdx := 0.U 497 for (i <- 1 until MAX_VLMUL) { 498 csBundle(i).lsrc(0) := src1 + i.U 499 csBundle(i).lsrc(1) := src2 + i.U 500 csBundle(i).lsrc(2) := dest 501 csBundle(i).ldest := dest 502 csBundle(i).uopIdx := i.U 503 } 504 csBundle(numOfUop - 1.U).ldest := dest 505 } 506 is(UopSplitType.VEC_VXM) { 507 /* 508 FMV.D.X 509 */ 510 csBundle(0).srcType(0) := SrcType.reg 511 csBundle(0).srcType(1) := SrcType.imm 512 csBundle(0).lsrc(1) := 0.U 513 csBundle(0).ldest := FP_TMP_REG_MV.U 514 csBundle(0).fuType := FuType.i2f.U 515 csBundle(0).rfWen := false.B 516 csBundle(0).fpWen := true.B 517 csBundle(0).vecWen := false.B 518 csBundle(0).fpu.isAddSub := false.B 519 csBundle(0).fpu.typeTagIn := FPU.D 520 csBundle(0).fpu.typeTagOut := FPU.D 521 csBundle(0).fpu.fromInt := true.B 522 csBundle(0).fpu.wflags := false.B 523 csBundle(0).fpu.fpWen := true.B 524 csBundle(0).fpu.div := false.B 525 csBundle(0).fpu.sqrt := false.B 526 csBundle(0).fpu.fcvt := false.B 527 //LMUL 528 csBundle(1).srcType(0) := SrcType.fp 529 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 530 csBundle(1).lsrc(2) := dest 531 csBundle(1).ldest := dest 532 csBundle(1).uopIdx := 0.U 533 for (i <- 1 until MAX_VLMUL) { 534 csBundle(i + 1).srcType(0) := SrcType.fp 535 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 536 csBundle(i + 1).lsrc(1) := src2 + i.U 537 csBundle(i + 1).lsrc(2) := dest 538 csBundle(i + 1).ldest := dest 539 csBundle(i + 1).uopIdx := i.U 540 } 541 csBundle(numOfUop - 1.U).ldest := dest 542 } 543 is(UopSplitType.VEC_SLIDE1UP) { 544 /* 545 FMV.D.X 546 */ 547 csBundle(0).srcType(0) := SrcType.reg 548 csBundle(0).srcType(1) := SrcType.imm 549 csBundle(0).lsrc(1) := 0.U 550 csBundle(0).ldest := FP_TMP_REG_MV.U 551 csBundle(0).fuType := FuType.i2f.U 552 csBundle(0).rfWen := false.B 553 csBundle(0).fpWen := true.B 554 csBundle(0).vecWen := false.B 555 csBundle(0).fpu.isAddSub := false.B 556 csBundle(0).fpu.typeTagIn := FPU.D 557 csBundle(0).fpu.typeTagOut := FPU.D 558 csBundle(0).fpu.fromInt := true.B 559 csBundle(0).fpu.wflags := false.B 560 csBundle(0).fpu.fpWen := true.B 561 csBundle(0).fpu.div := false.B 562 csBundle(0).fpu.sqrt := false.B 563 csBundle(0).fpu.fcvt := false.B 564 //LMUL 565 csBundle(1).srcType(0) := SrcType.fp 566 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 567 csBundle(1).lsrc(2) := dest 568 csBundle(1).ldest := dest 569 csBundle(1).uopIdx := 0.U 570 for (i <- 1 until MAX_VLMUL) { 571 csBundle(i + 1).srcType(0) := SrcType.vp 572 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 573 csBundle(i + 1).lsrc(1) := src2 + i.U 574 csBundle(i + 1).lsrc(2) := dest + i.U 575 csBundle(i + 1).ldest := dest + i.U 576 csBundle(i + 1).uopIdx := i.U 577 } 578 } 579 is(UopSplitType.VEC_FSLIDE1UP) { 580 //LMUL 581 csBundle(0).srcType(0) := SrcType.fp 582 csBundle(0).lsrc(0) := src1 583 csBundle(0).lsrc(1) := src2 584 csBundle(0).lsrc(2) := dest 585 csBundle(0).ldest := dest 586 csBundle(0).uopIdx := 0.U 587 for (i <- 1 until MAX_VLMUL) { 588 csBundle(i).srcType(0) := SrcType.vp 589 csBundle(i).lsrc(0) := src2 + (i - 1).U 590 csBundle(i).lsrc(1) := src2 + i.U 591 csBundle(i).lsrc(2) := dest + i.U 592 csBundle(i).ldest := dest + i.U 593 csBundle(i).uopIdx := i.U 594 } 595 } 596 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 597 /* 598 FMV.D.X 599 */ 600 csBundle(0).srcType(0) := SrcType.reg 601 csBundle(0).srcType(1) := SrcType.imm 602 csBundle(0).lsrc(1) := 0.U 603 csBundle(0).ldest := FP_TMP_REG_MV.U 604 csBundle(0).fuType := FuType.i2f.U 605 csBundle(0).rfWen := false.B 606 csBundle(0).fpWen := true.B 607 csBundle(0).vecWen := false.B 608 csBundle(0).fpu.isAddSub := false.B 609 csBundle(0).fpu.typeTagIn := FPU.D 610 csBundle(0).fpu.typeTagOut := FPU.D 611 csBundle(0).fpu.fromInt := true.B 612 csBundle(0).fpu.wflags := false.B 613 csBundle(0).fpu.fpWen := true.B 614 csBundle(0).fpu.div := false.B 615 csBundle(0).fpu.sqrt := false.B 616 csBundle(0).fpu.fcvt := false.B 617 //LMUL 618 for (i <- 0 until MAX_VLMUL) { 619 csBundle(2 * i + 1).srcType(0) := SrcType.vp 620 csBundle(2 * i + 1).srcType(1) := SrcType.vp 621 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 622 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 623 csBundle(2 * i + 1).lsrc(2) := dest + i.U 624 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 625 csBundle(2 * i + 1).uopIdx := (2 * i).U 626 if (2 * i + 2 < MAX_VLMUL * 2) { 627 csBundle(2 * i + 2).srcType(0) := SrcType.fp 628 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 629 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 630 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 631 csBundle(2 * i + 2).ldest := dest + i.U 632 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 633 } 634 } 635 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 636 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 637 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 638 } 639 is(UopSplitType.VEC_FSLIDE1DOWN) { 640 //LMUL 641 for (i <- 0 until MAX_VLMUL) { 642 csBundle(2 * i).srcType(0) := SrcType.vp 643 csBundle(2 * i).srcType(1) := SrcType.vp 644 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 645 csBundle(2 * i).lsrc(1) := src2 + i.U 646 csBundle(2 * i).lsrc(2) := dest + i.U 647 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 648 csBundle(2 * i).uopIdx := (2 * i).U 649 csBundle(2 * i + 1).srcType(0) := SrcType.fp 650 csBundle(2 * i + 1).lsrc(0) := src1 651 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 652 csBundle(2 * i + 1).ldest := dest + i.U 653 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 654 } 655 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 656 csBundle(numOfUop - 1.U).lsrc(0) := src1 657 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 658 } 659 is(UopSplitType.VEC_VRED) { 660 when(simple.io.enq.vtype.vlmul === "b001".U) { 661 csBundle(0).srcType(2) := SrcType.DC 662 csBundle(0).lsrc(0) := src2 + 1.U 663 csBundle(0).lsrc(1) := src2 664 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 665 csBundle(0).uopIdx := 0.U 666 } 667 when(simple.io.enq.vtype.vlmul === "b010".U) { 668 csBundle(0).srcType(2) := SrcType.DC 669 csBundle(0).lsrc(0) := src2 + 1.U 670 csBundle(0).lsrc(1) := src2 671 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 672 csBundle(0).uopIdx := 0.U 673 674 csBundle(1).srcType(2) := SrcType.DC 675 csBundle(1).lsrc(0) := src2 + 3.U 676 csBundle(1).lsrc(1) := src2 + 2.U 677 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 678 csBundle(1).uopIdx := 1.U 679 680 csBundle(2).srcType(2) := SrcType.DC 681 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 682 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 683 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 684 csBundle(2).uopIdx := 2.U 685 } 686 when(simple.io.enq.vtype.vlmul === "b011".U) { 687 for (i <- 0 until MAX_VLMUL) { 688 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 689 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 690 csBundle(i).lsrc(1) := src2 + (i * 2).U 691 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 692 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 693 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 694 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 695 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 696 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 697 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 698 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 699 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 700 } 701 csBundle(i).srcType(2) := SrcType.DC 702 csBundle(i).uopIdx := i.U 703 } 704 } 705 when(simple.io.enq.vtype.vlmul.orR()) { 706 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 707 csBundle(numOfUop - 1.U).lsrc(0) := src1 708 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 709 csBundle(numOfUop - 1.U).lsrc(2) := dest 710 csBundle(numOfUop - 1.U).ldest := dest 711 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 712 } 713 } 714 715 is(UopSplitType.VEC_SLIDEUP) { 716 // FMV.D.X 717 csBundle(0).srcType(0) := SrcType.reg 718 csBundle(0).srcType(1) := SrcType.imm 719 csBundle(0).lsrc(1) := 0.U 720 csBundle(0).ldest := FP_TMP_REG_MV.U 721 csBundle(0).fuType := FuType.i2f.U 722 csBundle(0).rfWen := false.B 723 csBundle(0).fpWen := true.B 724 csBundle(0).vecWen := false.B 725 csBundle(0).fpu.isAddSub := false.B 726 csBundle(0).fpu.typeTagIn := FPU.D 727 csBundle(0).fpu.typeTagOut := FPU.D 728 csBundle(0).fpu.fromInt := true.B 729 csBundle(0).fpu.wflags := false.B 730 csBundle(0).fpu.fpWen := true.B 731 csBundle(0).fpu.div := false.B 732 csBundle(0).fpu.sqrt := false.B 733 csBundle(0).fpu.fcvt := false.B 734 // LMUL 735 for (i <- 0 until MAX_VLMUL) 736 for (j <- 0 to i) { 737 val old_vd = if (j == 0) { 738 dest + i.U 739 } else (VECTOR_TMP_REG_LMUL + j - 1).U 740 val vd = if (j == i) { 741 dest + i.U 742 } else (VECTOR_TMP_REG_LMUL + j).U 743 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 744 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 745 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 746 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 747 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 748 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 749 } 750 } 751 752 is(UopSplitType.VEC_ISLIDEUP) { 753 // LMUL 754 for (i <- 0 until MAX_VLMUL) 755 for (j <- 0 to i) { 756 val old_vd = if (j == 0) { 757 dest + i.U 758 } else (VECTOR_TMP_REG_LMUL + j - 1).U 759 val vd = if (j == i) { 760 dest + i.U 761 } else (VECTOR_TMP_REG_LMUL + j).U 762 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 763 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 764 csBundle(i * (i + 1) / 2 + j).ldest := vd 765 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 766 } 767 } 768 769 is(UopSplitType.VEC_SLIDEDOWN) { 770 // FMV.D.X 771 csBundle(0).srcType(0) := SrcType.reg 772 csBundle(0).srcType(1) := SrcType.imm 773 csBundle(0).lsrc(1) := 0.U 774 csBundle(0).ldest := FP_TMP_REG_MV.U 775 csBundle(0).fuType := FuType.i2f.U 776 csBundle(0).rfWen := false.B 777 csBundle(0).fpWen := true.B 778 csBundle(0).vecWen := false.B 779 csBundle(0).fpu.isAddSub := false.B 780 csBundle(0).fpu.typeTagIn := FPU.D 781 csBundle(0).fpu.typeTagOut := FPU.D 782 csBundle(0).fpu.fromInt := true.B 783 csBundle(0).fpu.wflags := false.B 784 csBundle(0).fpu.fpWen := true.B 785 csBundle(0).fpu.div := false.B 786 csBundle(0).fpu.sqrt := false.B 787 csBundle(0).fpu.fcvt := false.B 788 // LMUL 789 for (i <- 0 until MAX_VLMUL) 790 for (j <- (0 to i).reverse) { 791 when(i.U < lmul) { 792 val old_vd = if (j == 0) { 793 dest + lmul - 1.U - i.U 794 } else (VECTOR_TMP_REG_LMUL + j - 1).U 795 val vd = if (j == i) { 796 dest + lmul - 1.U - i.U 797 } else (VECTOR_TMP_REG_LMUL + j).U 798 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 799 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 800 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 801 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 802 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 803 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 804 } 805 } 806 } 807 808 is(UopSplitType.VEC_ISLIDEDOWN) { 809 // LMUL 810 for (i <- 0 until MAX_VLMUL) 811 for (j <- (0 to i).reverse) { 812 when(i.U < lmul) { 813 val old_vd = if (j == 0) { 814 dest + lmul - 1.U - i.U 815 } else (VECTOR_TMP_REG_LMUL + j - 1).U 816 val vd = if (j == i) { 817 dest + lmul - 1.U - i.U 818 } else (VECTOR_TMP_REG_LMUL + j).U 819 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 820 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 821 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 822 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 823 } 824 } 825 } 826 827 is(UopSplitType.VEC_M0X) { 828 // LMUL 829 for (i <- 0 until MAX_VLMUL) { 830 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 831 val ldest = (VECTOR_TMP_REG_LMUL + i).U 832 csBundle(i).srcType(0) := srcType0 833 csBundle(i).srcType(1) := SrcType.vp 834 csBundle(i).rfWen := false.B 835 csBundle(i).vecWen := true.B 836 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 837 csBundle(i).lsrc(1) := src2 838 // csBundle(i).lsrc(2) := dest + i.U DontCare 839 csBundle(i).ldest := ldest 840 csBundle(i).uopIdx := i.U 841 } 842 csBundle(lmul - 1.U).vecWen := false.B 843 csBundle(lmul - 1.U).fpWen := true.B 844 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 845 // FMV_X_D 846 csBundle(lmul).srcType(0) := SrcType.fp 847 csBundle(lmul).srcType(1) := SrcType.imm 848 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 849 csBundle(lmul).lsrc(1) := 0.U 850 csBundle(lmul).ldest := dest 851 csBundle(lmul).fuType := FuType.fmisc.U 852 csBundle(lmul).rfWen := true.B 853 csBundle(lmul).fpWen := false.B 854 csBundle(lmul).vecWen := false.B 855 csBundle(lmul).fpu.isAddSub := false.B 856 csBundle(lmul).fpu.typeTagIn := FPU.D 857 csBundle(lmul).fpu.typeTagOut := FPU.D 858 csBundle(lmul).fpu.fromInt := false.B 859 csBundle(lmul).fpu.wflags := false.B 860 csBundle(lmul).fpu.fpWen := false.B 861 csBundle(lmul).fpu.div := false.B 862 csBundle(lmul).fpu.sqrt := false.B 863 csBundle(lmul).fpu.fcvt := false.B 864 } 865 866 is(UopSplitType.VEC_MVV) { 867 // LMUL 868 for (i <- 0 until MAX_VLMUL) { 869 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 870 csBundle(i * 2 + 0).srcType(0) := srcType0 871 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 872 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 873 csBundle(i * 2 + 0).lsrc(1) := src2 874 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 875 csBundle(i * 2 + 0).ldest := dest + i.U 876 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 877 878 csBundle(i * 2 + 1).srcType(0) := srcType0 879 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 880 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 881 csBundle(i * 2 + 1).lsrc(1) := src2 882 // csBundle(i).lsrc(2) := dest + i.U DontCare 883 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 884 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 885 } 886 } 887 888 is(UopSplitType.VEC_M0X_VFIRST) { 889 // LMUL 890 csBundle(0).rfWen := false.B 891 csBundle(0).fpWen := true.B 892 csBundle(0).ldest := FP_TMP_REG_MV.U 893 // FMV_X_D 894 csBundle(1).srcType(0) := SrcType.fp 895 csBundle(1).srcType(1) := SrcType.imm 896 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 897 csBundle(1).lsrc(1) := 0.U 898 csBundle(1).ldest := dest 899 csBundle(1).fuType := FuType.fmisc.U 900 csBundle(1).rfWen := true.B 901 csBundle(1).fpWen := false.B 902 csBundle(1).vecWen := false.B 903 csBundle(1).fpu.isAddSub := false.B 904 csBundle(1).fpu.typeTagIn := FPU.D 905 csBundle(1).fpu.typeTagOut := FPU.D 906 csBundle(1).fpu.fromInt := false.B 907 csBundle(1).fpu.wflags := false.B 908 csBundle(1).fpu.fpWen := false.B 909 csBundle(1).fpu.div := false.B 910 csBundle(1).fpu.sqrt := false.B 911 csBundle(1).fpu.fcvt := false.B 912 } 913 is(UopSplitType.VEC_US_LD) { 914 /* 915 FMV.D.X 916 */ 917 csBundle(0).srcType(0) := SrcType.reg 918 csBundle(0).srcType(1) := SrcType.imm 919 csBundle(0).lsrc(1) := 0.U 920 csBundle(0).ldest := FP_TMP_REG_MV.U 921 csBundle(0).fuType := FuType.i2f.U 922 csBundle(0).rfWen := false.B 923 csBundle(0).fpWen := true.B 924 csBundle(0).vecWen := false.B 925 csBundle(0).fpu.isAddSub := false.B 926 csBundle(0).fpu.typeTagIn := FPU.D 927 csBundle(0).fpu.typeTagOut := FPU.D 928 csBundle(0).fpu.fromInt := true.B 929 csBundle(0).fpu.wflags := false.B 930 csBundle(0).fpu.fpWen := true.B 931 csBundle(0).fpu.div := false.B 932 csBundle(0).fpu.sqrt := false.B 933 csBundle(0).fpu.fcvt := false.B 934 //LMUL 935 for (i <- 0 until MAX_VLMUL) { 936 csBundle(i + 1).srcType(0) := SrcType.fp 937 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 938 csBundle(i + 1).ldest := dest + i.U 939 csBundle(i + 1).uopIdx := i.U 940 } 941 } 942 } 943 944 //uops dispatch 945 val normal :: ext :: Nil = Enum(2) 946 val stateReg = RegInit(normal) 947 val uopRes = RegInit(0.U) 948 949 //readyFromRename Counter 950 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 951 952 switch(stateReg) { 953 is(normal) { 954 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 955 } 956 is(ext) { 957 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 958 } 959 } 960 961 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 962 val uopResJudge = Mux(stateReg === normal, 963 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 964 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 965 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 966 967 for(i <- 0 until RenameWidth) { 968 decodedInsts(i) := MuxCase(csBundle(i), Seq( 969 (stateReg === normal) -> csBundle(i), 970 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 971 )) 972 } 973 974 975 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 976 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 977 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 978 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 979 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 980 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 981 notInfVec(0) := true.B 982 983 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 984 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 985 1.U) 986 validToRename.zipWithIndex.foreach{ 987 case(dst, i) => 988 dst := MuxCase(false.B, Seq( 989 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 990 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 991 )) 992 } 993 994 readyToIBuf.zipWithIndex.foreach { 995 case (dst, i) => 996 dst := MuxCase(true.B, Seq( 997 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 998 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 999 )) 1000 } 1001 1002 io.deq.decodedInsts := decodedInsts 1003 io.deq.isVset := isVset_u 1004 io.deq.complexNum := complexNum 1005 io.deq.validToRename := validToRename 1006 io.deq.readyToIBuf := readyToIBuf 1007 1008} 1009