1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35import scala.collection.Seq 36import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 37 38class indexedLSUopTable(uopIdx:Int) extends Module { 39 val src = IO(Input(UInt(7.W))) 40 val outOffsetVs2 = IO(Output(UInt(3.W))) 41 val outOffsetVd = IO(Output(UInt(3.W))) 42 val outIsFirstUopInVd = IO(Output(Bool())) 43 def genCsBundle_VEC_INDEXED_LDST(lmul:Int, emul:Int, nfields:Int, uopIdx:Int): (Int, Int, Int) ={ 44 if (lmul * nfields <= 8) { 45 for (k <-0 until nfields) { 46 if (lmul < emul) { // lmul < emul, uop num is depend on emul * nf 47 var offset = 1 << (emul - lmul) 48 for (i <- 0 until (1 << emul)) { 49 if (uopIdx == k * (1 << emul) + i) { 50 return (i, i / offset + k * (1 << lmul), if (i % offset == 0) 1 else 0) 51 } 52 } 53 } else { // lmul > emul, uop num is depend on lmul * nf 54 var offset = 1 << (lmul - emul) 55 for (i <- 0 until (1 << lmul)) { 56 if (uopIdx == k * (1 << lmul) + i) { 57 return (i / offset, i + k * (1 << lmul), 1) 58 } 59 } 60 } 61 } 62 } 63 return (0, 0, 1) 64 } 65 // strided load/store 66 var combVemulNf : Seq[(Int, Int, Int, Int, Int, Int)] = Seq() 67 for (emul <- 0 until 4) { 68 for (lmul <- 0 until 4) { 69 for (nf <- 0 until 8) { 70 var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, nf+1, uopIdx) 71 var offsetVs2 = offset._1 72 var offsetVd = offset._2 73 var isFirstUopInVd = offset._3 74 combVemulNf :+= (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) 75 } 76 } 77 } 78 val out = decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 79 case (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) => 80 (BitPat((emul << 5 | lmul << 3 | nf).U(7.W)), BitPat((isFirstUopInVd << 6 | offsetVs2 << 3 | offsetVd).U(7.W))) 81 }, BitPat.N(7))) 82 outOffsetVs2 := out(5, 3) 83 outOffsetVd := out(2, 0) 84 outIsFirstUopInVd := out(6).asBool 85} 86 87trait VectorConstants { 88 val MAX_VLMUL = 8 89 val FP_TMP_REG_MV = 32 90 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 91 val MAX_INDEXED_LS_UOPNUM = 64 92} 93 94class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 95 val redirect = Input(Bool()) 96 val csrCtrl = Input(new CustomCSRCtrlIO) 97 // When the first inst in decode vector is complex inst, pass it in 98 val in = Flipped(DecoupledIO(new Bundle { 99 val simpleDecodedInst = new DecodedInst 100 val uopInfo = new UopInfo 101 })) 102 val out = new Bundle { 103 val complexDecodedInsts = Vec(RenameWidth, DecoupledIO(new DecodedInst)) 104 } 105 val complexNum = Output(UInt(3.W)) 106} 107 108/** 109 * @author zly 110 */ 111class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 112 val io = IO(new DecodeUnitCompIO) 113 114 // alias 115 private val inReady = io.in.ready 116 private val inValid = io.in.valid 117 private val inDecodedInst = WireInit(io.in.bits.simpleDecodedInst) 118 private val inInstFields = io.in.bits.simpleDecodedInst.instr.asTypeOf(new XSInstBitFields) 119 private val inUopInfo = io.in.bits.uopInfo 120 private val outValids = io.out.complexDecodedInsts.map(_.valid) 121 private val outReadys = io.out.complexDecodedInsts.map(_.ready) 122 private val outDecodedInsts = io.out.complexDecodedInsts.map(_.bits) 123 private val outComplexNum = io.complexNum 124 125 val maxUopSize = MaxUopSize 126 when (io.in.fire && io.in.bits.simpleDecodedInst.isVset) { 127 when(inInstFields.RD === 0.U && inInstFields.RS1 === 0.U) { 128 inDecodedInst.fuOpType := VSETOpType.keepVl(io.in.bits.simpleDecodedInst.fuOpType) 129 }.elsewhen(inInstFields.RS1 === 0.U) { 130 inDecodedInst.fuOpType := VSETOpType.setVlmax(io.in.bits.simpleDecodedInst.fuOpType) 131 } 132 } 133 134 val latchedInst = RegEnable(inDecodedInst, inValid && inReady) 135 val latchedUopInfo = RegEnable(inUopInfo, inValid && inReady) 136 //input bits 137 private val instFields: XSInstBitFields = latchedInst.instr.asTypeOf(new XSInstBitFields) 138 139 val src1 = Cat(0.U(1.W), instFields.RS1) 140 val src2 = Cat(0.U(1.W), instFields.RS2) 141 val dest = Cat(0.U(1.W), instFields.RD) 142 143 val nf = instFields.NF 144 val width = instFields.WIDTH(1, 0) 145 146 //output of DecodeUnit 147 val numOfUop = Wire(UInt(log2Up(maxUopSize).W)) 148 val numOfWB = Wire(UInt(log2Up(maxUopSize).W)) 149 val lmul = Wire(UInt(4.W)) 150 val isVsetSimple = Wire(Bool()) 151 152 val indexedLSRegOffset = Seq.tabulate(MAX_INDEXED_LS_UOPNUM)(i => Module(new indexedLSUopTable(i))) 153 indexedLSRegOffset.map(_.src := 0.U) 154 155 //pre decode 156 lmul := latchedUopInfo.lmul 157 isVsetSimple := latchedInst.isVset 158 val vlmulReg = latchedInst.vpu.vlmul 159 val vsewReg = latchedInst.vpu.vsew 160 161 //Type of uop Div 162 val typeOfSplit = latchedInst.uopSplitType 163 val src1Type = latchedInst.srcType(0) 164 val src1IsImm = src1Type === SrcType.imm 165 166 numOfUop := latchedUopInfo.numOfUop 167 numOfWB := latchedUopInfo.numOfWB 168 169 //uops dispatch 170 val s_idle :: s_active :: Nil = Enum(2) 171 val state = RegInit(s_idle) 172 val stateNext = WireDefault(state) 173 val numDecodedUop = RegInit(0.U(log2Up(maxUopSize).W)) 174 val uopRes = RegInit(0.U(log2Up(maxUopSize).W)) 175 val uopResNext = WireInit(uopRes) 176 177 //uop div up to maxUopSize 178 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 179 csBundle.foreach { case dst => 180 dst := latchedInst 181 dst.numUops := latchedUopInfo.numOfUop 182 dst.numWB := latchedUopInfo.numOfWB 183 dst.firstUop := false.B 184 dst.lastUop := false.B 185 } 186 187 csBundle(0).firstUop := true.B 188 csBundle(numOfUop - 1.U).lastUop := true.B 189 190 switch(typeOfSplit) { 191 is(UopSplitType.VSET) { 192 // In simple decoder, rfWen and vecWen are not set 193 when(isVsetSimple) { 194 // Default 195 // uop0 set rd, never flushPipe 196 csBundle(0).fuType := FuType.vsetiwi.U 197 csBundle(0).flushPipe := false.B 198 csBundle(0).rfWen := true.B 199 // uop1 set vl, vsetvl will flushPipe 200 csBundle(1).ldest := VCONFIG_IDX.U 201 csBundle(1).vecWen := true.B 202 when(VSETOpType.isVsetvli(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 203 csBundle(1).fuType := FuType.vsetfwf.U 204 csBundle(1).srcType(0) := SrcType.vp 205 csBundle(1).lsrc(0) := VCONFIG_IDX.U 206 }.elsewhen(VSETOpType.isVsetvl(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 207 // uop0: mv vtype gpr to vector region 208 csBundle(0).srcType(0) := SrcType.xp 209 csBundle(0).srcType(1) := SrcType.no 210 csBundle(0).lsrc(1) := 0.U 211 csBundle(0).ldest := FP_TMP_REG_MV.U 212 csBundle(0).fuType := FuType.i2f.U 213 csBundle(0).fpWen := true.B 214 csBundle(0).fpu.isAddSub := false.B 215 csBundle(0).fpu.typeTagIn := FPU.D 216 csBundle(0).fpu.typeTagOut := FPU.D 217 csBundle(0).fpu.fromInt := true.B 218 csBundle(0).fpu.wflags := false.B 219 csBundle(0).fpu.fpWen := true.B 220 csBundle(0).fpu.div := false.B 221 csBundle(0).fpu.sqrt := false.B 222 csBundle(0).fpu.fcvt := false.B 223 csBundle(0).flushPipe := false.B 224 // uop1: uvsetvcfg_vv 225 csBundle(1).fuType := FuType.vsetfwf.U 226 // vl 227 csBundle(1).srcType(0) := SrcType.vp 228 csBundle(1).lsrc(0) := VCONFIG_IDX.U 229 // vtype 230 csBundle(1).srcType(1) := SrcType.fp 231 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 232 csBundle(1).vecWen := true.B 233 csBundle(1).ldest := VCONFIG_IDX.U 234 } 235 } 236 } 237 is(UopSplitType.VEC_VVV) { 238 for (i <- 0 until MAX_VLMUL) { 239 csBundle(i).lsrc(0) := src1 + i.U 240 csBundle(i).lsrc(1) := src2 + i.U 241 csBundle(i).lsrc(2) := dest + i.U 242 csBundle(i).ldest := dest + i.U 243 csBundle(i).uopIdx := i.U 244 } 245 } 246 is(UopSplitType.VEC_VFV) { 247 for (i <- 0 until MAX_VLMUL) { 248 csBundle(i).lsrc(1) := src2 + i.U 249 csBundle(i).lsrc(2) := dest + i.U 250 csBundle(i).ldest := dest + i.U 251 csBundle(i).uopIdx := i.U 252 } 253 } 254 is(UopSplitType.VEC_EXT2) { 255 for (i <- 0 until MAX_VLMUL / 2) { 256 csBundle(2 * i).lsrc(1) := src2 + i.U 257 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 258 csBundle(2 * i).ldest := dest + (2 * i).U 259 csBundle(2 * i).uopIdx := (2 * i).U 260 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 261 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 262 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 263 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 264 } 265 } 266 is(UopSplitType.VEC_EXT4) { 267 for (i <- 0 until MAX_VLMUL / 4) { 268 csBundle(4 * i).lsrc(1) := src2 + i.U 269 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 270 csBundle(4 * i).ldest := dest + (4 * i).U 271 csBundle(4 * i).uopIdx := (4 * i).U 272 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 273 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 274 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 275 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 276 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 277 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 278 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 279 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 280 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 281 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 282 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 283 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 284 } 285 } 286 is(UopSplitType.VEC_EXT8) { 287 for (i <- 0 until MAX_VLMUL) { 288 csBundle(i).lsrc(1) := src2 289 csBundle(i).lsrc(2) := dest + i.U 290 csBundle(i).ldest := dest + i.U 291 csBundle(i).uopIdx := i.U 292 } 293 } 294 is(UopSplitType.VEC_0XV) { 295 /* 296 FMV.D.X 297 */ 298 csBundle(0).srcType(0) := SrcType.reg 299 csBundle(0).srcType(1) := SrcType.imm 300 csBundle(0).lsrc(1) := 0.U 301 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 302 csBundle(0).fuType := FuType.i2v.U 303 csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), vsewReg) 304 csBundle(0).rfWen := false.B 305 csBundle(0).fpWen := false.B 306 csBundle(0).vecWen := true.B 307 /* 308 vmv.s.x 309 */ 310 csBundle(1).srcType(0) := SrcType.vp 311 csBundle(1).srcType(1) := SrcType.imm 312 csBundle(1).srcType(2) := SrcType.vp 313 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 314 csBundle(1).lsrc(1) := 0.U 315 csBundle(1).lsrc(2) := dest 316 csBundle(1).ldest := dest 317 csBundle(1).rfWen := false.B 318 csBundle(1).fpWen := false.B 319 csBundle(1).vecWen := true.B 320 csBundle(1).uopIdx := 0.U 321 } 322 is(UopSplitType.VEC_VXV) { 323 /* 324 i to vector move 325 */ 326 csBundle(0).srcType(0) := SrcType.reg 327 csBundle(0).srcType(1) := SrcType.imm 328 csBundle(0).lsrc(1) := 0.U 329 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 330 csBundle(0).fuType := FuType.i2v.U 331 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 332 csBundle(0).vecWen := true.B 333 /* 334 LMUL 335 */ 336 for (i <- 0 until MAX_VLMUL) { 337 csBundle(i + 1).srcType(0) := SrcType.vp 338 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 339 csBundle(i + 1).lsrc(1) := src2 + i.U 340 csBundle(i + 1).lsrc(2) := dest + i.U 341 csBundle(i + 1).ldest := dest + i.U 342 csBundle(i + 1).uopIdx := i.U 343 } 344 } 345 is(UopSplitType.VEC_VVW) { 346 for (i <- 0 until MAX_VLMUL / 2) { 347 csBundle(2 * i).lsrc(0) := src1 + i.U 348 csBundle(2 * i).lsrc(1) := src2 + i.U 349 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 350 csBundle(2 * i).ldest := dest + (2 * i).U 351 csBundle(2 * i).uopIdx := (2 * i).U 352 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 353 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 354 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 355 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 356 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 357 } 358 } 359 is(UopSplitType.VEC_VFW) { 360 for (i <- 0 until MAX_VLMUL / 2) { 361 csBundle(2 * i).lsrc(0) := src1 362 csBundle(2 * i).lsrc(1) := src2 + i.U 363 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 364 csBundle(2 * i).ldest := dest + (2 * i).U 365 csBundle(2 * i).uopIdx := (2 * i).U 366 csBundle(2 * i + 1).lsrc(0) := src1 367 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 368 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 369 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 370 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 371 } 372 } 373 is(UopSplitType.VEC_WVW) { 374 for (i <- 0 until MAX_VLMUL / 2) { 375 csBundle(2 * i).lsrc(0) := src1 + i.U 376 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 377 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 378 csBundle(2 * i).ldest := dest + (2 * i).U 379 csBundle(2 * i).uopIdx := (2 * i).U 380 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 381 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 382 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 383 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 384 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 385 } 386 } 387 is(UopSplitType.VEC_VXW) { 388 /* 389 i to vector move 390 */ 391 csBundle(0).srcType(0) := SrcType.reg 392 csBundle(0).srcType(1) := SrcType.imm 393 csBundle(0).lsrc(1) := 0.U 394 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 395 csBundle(0).fuType := FuType.i2v.U 396 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 397 csBundle(0).vecWen := true.B 398 399 for (i <- 0 until MAX_VLMUL / 2) { 400 csBundle(2 * i + 1).srcType(0) := SrcType.vp 401 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 402 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 403 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 404 csBundle(2 * i + 1).ldest := dest + (2 * i).U 405 csBundle(2 * i + 1).uopIdx := (2 * i).U 406 csBundle(2 * i + 2).srcType(0) := SrcType.vp 407 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 408 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 409 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 410 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 411 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 412 } 413 } 414 is(UopSplitType.VEC_WXW) { 415 /* 416 i to vector move 417 */ 418 csBundle(0).srcType(0) := SrcType.reg 419 csBundle(0).srcType(1) := SrcType.imm 420 csBundle(0).lsrc(1) := 0.U 421 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 422 csBundle(0).fuType := FuType.i2v.U 423 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 424 csBundle(0).vecWen := true.B 425 426 for (i <- 0 until MAX_VLMUL / 2) { 427 csBundle(2 * i + 1).srcType(0) := SrcType.vp 428 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 429 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 430 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 431 csBundle(2 * i + 1).ldest := dest + (2 * i).U 432 csBundle(2 * i + 1).uopIdx := (2 * i).U 433 csBundle(2 * i + 2).srcType(0) := SrcType.vp 434 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 435 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 436 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 437 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 438 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 439 } 440 } 441 is(UopSplitType.VEC_WVV) { 442 for (i <- 0 until MAX_VLMUL / 2) { 443 444 csBundle(2 * i).lsrc(0) := src1 + i.U 445 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 446 csBundle(2 * i).lsrc(2) := dest + i.U 447 csBundle(2 * i).ldest := dest + i.U 448 csBundle(2 * i).uopIdx := (2 * i).U 449 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 450 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 451 csBundle(2 * i + 1).lsrc(2) := dest + i.U 452 csBundle(2 * i + 1).ldest := dest + i.U 453 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 454 } 455 } 456 is(UopSplitType.VEC_WFW) { 457 for (i <- 0 until MAX_VLMUL / 2) { 458 csBundle(2 * i).lsrc(0) := src1 459 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 460 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 461 csBundle(2 * i).ldest := dest + (2 * i).U 462 csBundle(2 * i).uopIdx := (2 * i).U 463 csBundle(2 * i + 1).lsrc(0) := src1 464 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 465 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 466 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 467 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 468 } 469 } 470 is(UopSplitType.VEC_WXV) { 471 /* 472 i to vector move 473 */ 474 csBundle(0).srcType(0) := SrcType.reg 475 csBundle(0).srcType(1) := SrcType.imm 476 csBundle(0).lsrc(1) := 0.U 477 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 478 csBundle(0).fuType := FuType.i2v.U 479 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 480 csBundle(0).vecWen := true.B 481 482 for (i <- 0 until MAX_VLMUL / 2) { 483 csBundle(2 * i + 1).srcType(0) := SrcType.vp 484 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 485 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 486 csBundle(2 * i + 1).lsrc(2) := dest + i.U 487 csBundle(2 * i + 1).ldest := dest + i.U 488 csBundle(2 * i + 1).uopIdx := (2 * i).U 489 csBundle(2 * i + 2).srcType(0) := SrcType.vp 490 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 491 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 492 csBundle(2 * i + 2).lsrc(2) := dest + i.U 493 csBundle(2 * i + 2).ldest := dest + i.U 494 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 495 } 496 } 497 is(UopSplitType.VEC_VVM) { 498 csBundle(0).lsrc(2) := dest 499 csBundle(0).ldest := dest 500 csBundle(0).uopIdx := 0.U 501 for (i <- 1 until MAX_VLMUL) { 502 csBundle(i).lsrc(0) := src1 + i.U 503 csBundle(i).lsrc(1) := src2 + i.U 504 csBundle(i).lsrc(2) := dest 505 csBundle(i).ldest := dest 506 csBundle(i).uopIdx := i.U 507 } 508 } 509 is(UopSplitType.VEC_VFM) { 510 csBundle(0).lsrc(2) := dest 511 csBundle(0).ldest := dest 512 csBundle(0).uopIdx := 0.U 513 for (i <- 1 until MAX_VLMUL) { 514 csBundle(i).lsrc(0) := src1 515 csBundle(i).lsrc(1) := src2 + i.U 516 csBundle(i).lsrc(2) := dest 517 csBundle(i).ldest := dest 518 csBundle(i).uopIdx := i.U 519 } 520 csBundle(numOfUop - 1.U).ldest := dest 521 } 522 is(UopSplitType.VEC_VXM) { 523 /* 524 i to vector move 525 */ 526 csBundle(0).srcType(0) := SrcType.reg 527 csBundle(0).srcType(1) := SrcType.imm 528 csBundle(0).lsrc(1) := 0.U 529 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 530 csBundle(0).fuType := FuType.i2v.U 531 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 532 csBundle(0).vecWen := true.B 533 //LMUL 534 csBundle(1).srcType(0) := SrcType.vp 535 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 536 csBundle(1).lsrc(2) := dest 537 csBundle(1).ldest := dest 538 csBundle(1).uopIdx := 0.U 539 for (i <- 1 until MAX_VLMUL) { 540 csBundle(i + 1).srcType(0) := SrcType.vp 541 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 542 csBundle(i + 1).lsrc(1) := src2 + i.U 543 csBundle(i + 1).lsrc(2) := dest 544 csBundle(i + 1).ldest := dest 545 csBundle(i + 1).uopIdx := i.U 546 } 547 csBundle(numOfUop - 1.U).ldest := dest 548 } 549 is(UopSplitType.VEC_SLIDE1UP) { 550 /* 551 i to vector move 552 */ 553 csBundle(0).srcType(0) := SrcType.reg 554 csBundle(0).srcType(1) := SrcType.imm 555 csBundle(0).lsrc(1) := 0.U 556 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 557 csBundle(0).fuType := FuType.i2v.U 558 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 559 csBundle(0).vecWen := true.B 560 //LMUL 561 csBundle(1).srcType(0) := SrcType.vp 562 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 563 csBundle(1).lsrc(2) := dest 564 csBundle(1).ldest := dest 565 csBundle(1).uopIdx := 0.U 566 for (i <- 1 until MAX_VLMUL) { 567 csBundle(i + 1).srcType(0) := SrcType.vp 568 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 569 csBundle(i + 1).lsrc(1) := src2 + i.U 570 csBundle(i + 1).lsrc(2) := dest + i.U 571 csBundle(i + 1).ldest := dest + i.U 572 csBundle(i + 1).uopIdx := i.U 573 } 574 } 575 is(UopSplitType.VEC_FSLIDE1UP) { 576 //LMUL 577 csBundle(0).srcType(0) := SrcType.fp 578 csBundle(0).lsrc(0) := src1 579 csBundle(0).lsrc(1) := src2 580 csBundle(0).lsrc(2) := dest 581 csBundle(0).ldest := dest 582 csBundle(0).uopIdx := 0.U 583 for (i <- 1 until MAX_VLMUL) { 584 csBundle(i).srcType(0) := SrcType.vp 585 csBundle(i).lsrc(0) := src2 + (i - 1).U 586 csBundle(i).lsrc(1) := src2 + i.U 587 csBundle(i).lsrc(2) := dest + i.U 588 csBundle(i).ldest := dest + i.U 589 csBundle(i).uopIdx := i.U 590 } 591 } 592 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 593 /* 594 i to vector move 595 */ 596 csBundle(0).srcType(0) := SrcType.reg 597 csBundle(0).srcType(1) := SrcType.imm 598 csBundle(0).lsrc(1) := 0.U 599 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 600 csBundle(0).fuType := FuType.i2v.U 601 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 602 csBundle(0).vecWen := true.B 603 //LMUL 604 for (i <- 0 until MAX_VLMUL) { 605 csBundle(2 * i + 1).srcType(0) := SrcType.vp 606 csBundle(2 * i + 1).srcType(1) := SrcType.vp 607 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 608 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 609 csBundle(2 * i + 1).lsrc(2) := dest + i.U 610 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 611 csBundle(2 * i + 1).uopIdx := (2 * i).U 612 if (2 * i + 2 < MAX_VLMUL * 2) { 613 csBundle(2 * i + 2).srcType(0) := SrcType.vp 614 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 615 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 616 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 617 csBundle(2 * i + 2).ldest := dest + i.U 618 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 619 } 620 } 621 csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 622 csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 623 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 624 } 625 is(UopSplitType.VEC_FSLIDE1DOWN) { 626 //LMUL 627 for (i <- 0 until MAX_VLMUL) { 628 csBundle(2 * i).srcType(0) := SrcType.vp 629 csBundle(2 * i).srcType(1) := SrcType.vp 630 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 631 csBundle(2 * i).lsrc(1) := src2 + i.U 632 csBundle(2 * i).lsrc(2) := dest + i.U 633 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 634 csBundle(2 * i).uopIdx := (2 * i).U 635 csBundle(2 * i + 1).srcType(0) := SrcType.fp 636 csBundle(2 * i + 1).lsrc(0) := src1 637 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 638 csBundle(2 * i + 1).ldest := dest + i.U 639 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 640 } 641 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 642 csBundle(numOfUop - 1.U).lsrc(0) := src1 643 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 644 } 645 is(UopSplitType.VEC_VRED) { 646 when(vlmulReg === "b001".U) { 647 csBundle(0).srcType(2) := SrcType.DC 648 csBundle(0).lsrc(0) := src2 + 1.U 649 csBundle(0).lsrc(1) := src2 650 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 651 csBundle(0).uopIdx := 0.U 652 } 653 when(vlmulReg === "b010".U) { 654 csBundle(0).srcType(2) := SrcType.DC 655 csBundle(0).lsrc(0) := src2 + 1.U 656 csBundle(0).lsrc(1) := src2 657 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 658 csBundle(0).uopIdx := 0.U 659 660 csBundle(1).srcType(2) := SrcType.DC 661 csBundle(1).lsrc(0) := src2 + 3.U 662 csBundle(1).lsrc(1) := src2 + 2.U 663 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 664 csBundle(1).uopIdx := 1.U 665 666 csBundle(2).srcType(2) := SrcType.DC 667 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 668 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 669 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 670 csBundle(2).uopIdx := 2.U 671 } 672 when(vlmulReg === "b011".U) { 673 for (i <- 0 until MAX_VLMUL) { 674 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 675 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 676 csBundle(i).lsrc(1) := src2 + (i * 2).U 677 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 678 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 679 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 680 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 681 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 682 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 683 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 684 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 685 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 686 } 687 csBundle(i).srcType(2) := SrcType.DC 688 csBundle(i).uopIdx := i.U 689 } 690 } 691 when(vlmulReg.orR) { 692 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 693 csBundle(numOfUop - 1.U).lsrc(0) := src1 694 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 695 csBundle(numOfUop - 1.U).lsrc(2) := dest 696 csBundle(numOfUop - 1.U).ldest := dest 697 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 698 } 699 } 700 is(UopSplitType.VEC_VFRED) { 701 val vlmul = vlmulReg 702 val vsew = vsewReg 703 when(vlmul === VLmul.m8){ 704 for (i <- 0 until 4) { 705 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 706 csBundle(i).lsrc(1) := src2 + (i * 2).U 707 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 708 csBundle(i).uopIdx := i.U 709 } 710 for (i <- 4 until 6) { 711 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 712 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 713 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 714 csBundle(i).uopIdx := i.U 715 } 716 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 717 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 718 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 719 csBundle(6).uopIdx := 6.U 720 when(vsew === VSew.e64) { 721 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 722 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 723 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 724 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 725 csBundle(7).uopIdx := 7.U 726 csBundle(8).lsrc(0) := src1 727 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 728 csBundle(8).ldest := dest 729 csBundle(8).uopIdx := 8.U 730 } 731 when(vsew === VSew.e32) { 732 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 733 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 734 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 735 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 736 csBundle(7).uopIdx := 7.U 737 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 738 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 739 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 740 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 741 csBundle(8).uopIdx := 8.U 742 csBundle(9).lsrc(0) := src1 743 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 744 csBundle(9).ldest := dest 745 csBundle(9).uopIdx := 9.U 746 } 747 when(vsew === VSew.e16) { 748 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 749 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 750 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 751 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 752 csBundle(7).uopIdx := 7.U 753 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 754 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 755 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 756 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 757 csBundle(8).uopIdx := 8.U 758 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 759 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 760 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 761 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 762 csBundle(9).uopIdx := 9.U 763 csBundle(10).lsrc(0) := src1 764 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 765 csBundle(10).ldest := dest 766 csBundle(10).uopIdx := 10.U 767 } 768 } 769 when(vlmul === VLmul.m4) { 770 for (i <- 0 until 2) { 771 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 772 csBundle(i).lsrc(1) := src2 + (i * 2).U 773 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 774 csBundle(i).uopIdx := i.U 775 } 776 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 777 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 778 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 779 csBundle(2).uopIdx := 2.U 780 when(vsew === VSew.e64) { 781 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 782 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 783 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 784 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 785 csBundle(3).uopIdx := 3.U 786 csBundle(4).lsrc(0) := src1 787 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 788 csBundle(4).ldest := dest 789 csBundle(4).uopIdx := 4.U 790 } 791 when(vsew === VSew.e32) { 792 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 793 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 794 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 795 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 796 csBundle(3).uopIdx := 3.U 797 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 798 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 799 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 800 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 801 csBundle(4).uopIdx := 4.U 802 csBundle(5).lsrc(0) := src1 803 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 804 csBundle(5).ldest := dest 805 csBundle(5).uopIdx := 5.U 806 } 807 when(vsew === VSew.e16) { 808 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 809 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 810 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 811 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 812 csBundle(3).uopIdx := 3.U 813 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 814 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 815 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 816 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 817 csBundle(4).uopIdx := 4.U 818 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 819 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 820 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 821 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 822 csBundle(5).uopIdx := 5.U 823 csBundle(6).lsrc(0) := src1 824 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 825 csBundle(6).ldest := dest 826 csBundle(6).uopIdx := 6.U 827 } 828 } 829 when(vlmul === VLmul.m2) { 830 csBundle(0).lsrc(0) := src2 + 1.U 831 csBundle(0).lsrc(1) := src2 + 0.U 832 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 833 csBundle(0).uopIdx := 0.U 834 when(vsew === VSew.e64) { 835 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 836 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 837 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 838 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 839 csBundle(1).uopIdx := 1.U 840 csBundle(2).lsrc(0) := src1 841 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 842 csBundle(2).ldest := dest 843 csBundle(2).uopIdx := 2.U 844 } 845 when(vsew === VSew.e32) { 846 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 847 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 848 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 849 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 850 csBundle(1).uopIdx := 1.U 851 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 852 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 853 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 854 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 855 csBundle(2).uopIdx := 2.U 856 csBundle(3).lsrc(0) := src1 857 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 858 csBundle(3).ldest := dest 859 csBundle(3).uopIdx := 3.U 860 } 861 when(vsew === VSew.e16) { 862 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 863 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 864 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 865 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 866 csBundle(1).uopIdx := 1.U 867 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 868 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 869 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 870 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 871 csBundle(2).uopIdx := 2.U 872 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 873 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 874 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 875 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 876 csBundle(3).uopIdx := 3.U 877 csBundle(4).lsrc(0) := src1 878 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 879 csBundle(4).ldest := dest 880 csBundle(4).uopIdx := 4.U 881 } 882 } 883 when(vlmul === VLmul.m1) { 884 when(vsew === VSew.e64) { 885 csBundle(0).lsrc(0) := src2 886 csBundle(0).lsrc(1) := src2 887 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 888 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 889 csBundle(0).uopIdx := 0.U 890 csBundle(1).lsrc(0) := src1 891 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 892 csBundle(1).ldest := dest 893 csBundle(1).uopIdx := 1.U 894 } 895 when(vsew === VSew.e32) { 896 csBundle(0).lsrc(0) := src2 897 csBundle(0).lsrc(1) := src2 898 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 899 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 900 csBundle(0).uopIdx := 0.U 901 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 902 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 903 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 904 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 905 csBundle(1).uopIdx := 1.U 906 csBundle(2).lsrc(0) := src1 907 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 908 csBundle(2).ldest := dest 909 csBundle(2).uopIdx := 2.U 910 } 911 when(vsew === VSew.e16) { 912 csBundle(0).lsrc(0) := src2 913 csBundle(0).lsrc(1) := src2 914 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 915 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 916 csBundle(0).uopIdx := 0.U 917 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 918 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 919 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 920 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 921 csBundle(1).uopIdx := 1.U 922 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 923 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 924 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 925 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 926 csBundle(2).uopIdx := 2.U 927 csBundle(3).lsrc(0) := src1 928 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 929 csBundle(3).ldest := dest 930 csBundle(3).uopIdx := 3.U 931 } 932 } 933 when(vlmul === VLmul.mf2) { 934 when(vsew === VSew.e32) { 935 csBundle(0).lsrc(0) := src2 936 csBundle(0).lsrc(1) := src2 937 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 938 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 939 csBundle(0).uopIdx := 0.U 940 csBundle(1).lsrc(0) := src1 941 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 942 csBundle(1).ldest := dest 943 csBundle(1).uopIdx := 1.U 944 } 945 when(vsew === VSew.e16) { 946 csBundle(0).lsrc(0) := src2 947 csBundle(0).lsrc(1) := src2 948 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 949 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 950 csBundle(0).uopIdx := 0.U 951 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 952 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 953 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 954 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 955 csBundle(1).uopIdx := 1.U 956 csBundle(2).lsrc(0) := src1 957 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 958 csBundle(2).ldest := dest 959 csBundle(2).uopIdx := 2.U 960 } 961 } 962 when(vlmul === VLmul.mf4) { 963 when(vsew === VSew.e16) { 964 csBundle(0).lsrc(0) := src2 965 csBundle(0).lsrc(1) := src2 966 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 967 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 968 csBundle(0).uopIdx := 0.U 969 csBundle(1).lsrc(0) := src1 970 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 971 csBundle(1).ldest := dest 972 csBundle(1).uopIdx := 1.U 973 } 974 } 975 } 976 977 is(UopSplitType.VEC_VFREDOSUM) { 978 import yunsuan.VfaluType 979 val vlmul = vlmulReg 980 val vsew = vsewReg 981 val isWiden = latchedInst.fuOpType === VfaluType.vfwredosum 982 when(vlmul === VLmul.m8) { 983 when(vsew === VSew.e64) { 984 val vlmax = 16 985 for (i <- 0 until vlmax) { 986 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 987 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 988 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 989 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 990 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 991 csBundle(i).uopIdx := i.U 992 } 993 } 994 when(vsew === VSew.e32) { 995 val vlmax = 32 996 for (i <- 0 until vlmax) { 997 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 998 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 999 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1000 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1001 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1002 csBundle(i).uopIdx := i.U 1003 } 1004 } 1005 when(vsew === VSew.e16) { 1006 val vlmax = 64 1007 for (i <- 0 until vlmax) { 1008 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1009 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1010 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1011 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1012 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1013 csBundle(i).uopIdx := i.U 1014 } 1015 } 1016 } 1017 when(vlmul === VLmul.m4) { 1018 when(vsew === VSew.e64) { 1019 val vlmax = 8 1020 for (i <- 0 until vlmax) { 1021 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1022 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1023 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1024 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1025 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1026 csBundle(i).uopIdx := i.U 1027 } 1028 } 1029 when(vsew === VSew.e32) { 1030 val vlmax = 16 1031 for (i <- 0 until vlmax) { 1032 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1033 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1034 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1035 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1036 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1037 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1038 csBundle(i).uopIdx := i.U 1039 } 1040 } 1041 when(vsew === VSew.e16) { 1042 val vlmax = 32 1043 for (i <- 0 until vlmax) { 1044 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1045 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1046 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1047 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1048 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1049 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1050 csBundle(i).uopIdx := i.U 1051 } 1052 } 1053 } 1054 when(vlmul === VLmul.m2) { 1055 when(vsew === VSew.e64) { 1056 val vlmax = 4 1057 for (i <- 0 until vlmax) { 1058 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1059 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1060 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1061 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1062 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1063 csBundle(i).uopIdx := i.U 1064 } 1065 } 1066 when(vsew === VSew.e32) { 1067 val vlmax = 8 1068 for (i <- 0 until vlmax) { 1069 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1070 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1071 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1072 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1073 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1074 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1075 csBundle(i).uopIdx := i.U 1076 } 1077 } 1078 when(vsew === VSew.e16) { 1079 val vlmax = 16 1080 for (i <- 0 until vlmax) { 1081 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1082 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1083 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1084 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1085 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1086 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1087 csBundle(i).uopIdx := i.U 1088 } 1089 } 1090 } 1091 when(vlmul === VLmul.m1) { 1092 when(vsew === VSew.e64) { 1093 val vlmax = 2 1094 for (i <- 0 until vlmax) { 1095 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1096 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1097 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1098 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1099 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1100 csBundle(i).uopIdx := i.U 1101 } 1102 } 1103 when(vsew === VSew.e32) { 1104 val vlmax = 4 1105 for (i <- 0 until vlmax) { 1106 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1107 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1108 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1109 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1110 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1111 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1112 csBundle(i).uopIdx := i.U 1113 } 1114 } 1115 when(vsew === VSew.e16) { 1116 val vlmax = 8 1117 for (i <- 0 until vlmax) { 1118 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1119 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1120 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1121 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1122 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1123 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1124 csBundle(i).uopIdx := i.U 1125 } 1126 } 1127 } 1128 when(vlmul === VLmul.mf2) { 1129 when(vsew === VSew.e32) { 1130 val vlmax = 2 1131 for (i <- 0 until vlmax) { 1132 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1133 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1134 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1135 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1136 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1137 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1138 csBundle(i).uopIdx := i.U 1139 } 1140 } 1141 when(vsew === VSew.e16) { 1142 val vlmax = 4 1143 for (i <- 0 until vlmax) { 1144 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1145 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1146 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1147 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1148 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1149 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1150 csBundle(i).uopIdx := i.U 1151 } 1152 } 1153 } 1154 when(vlmul === VLmul.mf4) { 1155 when(vsew === VSew.e16) { 1156 val vlmax = 2 1157 for (i <- 0 until vlmax) { 1158 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1159 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1160 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1161 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1162 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1163 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1164 csBundle(i).uopIdx := i.U 1165 } 1166 } 1167 } 1168 } 1169 1170 is(UopSplitType.VEC_SLIDEUP) { 1171 // i to vector move 1172 csBundle(0).srcType(0) := SrcType.reg 1173 csBundle(0).srcType(1) := SrcType.imm 1174 csBundle(0).lsrc(1) := 0.U 1175 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1176 csBundle(0).fuType := FuType.i2v.U 1177 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1178 csBundle(0).vecWen := true.B 1179 // LMUL 1180 for (i <- 0 until MAX_VLMUL) 1181 for (j <- 0 to i) { 1182 val old_vd = if (j == 0) { 1183 dest + i.U 1184 } else (VECTOR_TMP_REG_LMUL + j).U 1185 val vd = if (j == i) { 1186 dest + i.U 1187 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1188 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1189 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1190 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1191 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1192 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1193 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1194 } 1195 } 1196 1197 is(UopSplitType.VEC_SLIDEDOWN) { 1198 // i to vector move 1199 csBundle(0).srcType(0) := SrcType.reg 1200 csBundle(0).srcType(1) := SrcType.imm 1201 csBundle(0).lsrc(1) := 0.U 1202 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1203 csBundle(0).fuType := FuType.i2v.U 1204 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1205 csBundle(0).vecWen := true.B 1206 // LMUL 1207 for (i <- 0 until MAX_VLMUL) 1208 for (j <- (0 to i).reverse) { 1209 when(i.U < lmul) { 1210 val old_vd = if (j == 0) { 1211 dest + lmul - 1.U - i.U 1212 } else (VECTOR_TMP_REG_LMUL + j).U 1213 val vd = if (j == i) { 1214 dest + lmul - 1.U - i.U 1215 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1216 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1217 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1218 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1219 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1220 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1221 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1222 } 1223 } 1224 } 1225 1226 is(UopSplitType.VEC_M0X) { 1227 // LMUL 1228 for (i <- 0 until MAX_VLMUL) { 1229 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1230 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1231 csBundle(i).srcType(0) := srcType0 1232 csBundle(i).srcType(1) := SrcType.vp 1233 csBundle(i).rfWen := false.B 1234 csBundle(i).fpWen := false.B 1235 csBundle(i).vecWen := true.B 1236 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1237 csBundle(i).lsrc(1) := src2 1238 // csBundle(i).lsrc(2) := dest + i.U DontCare 1239 csBundle(i).ldest := ldest 1240 csBundle(i).uopIdx := i.U 1241 } 1242 csBundle(lmul - 1.U).rfWen := true.B 1243 csBundle(lmul - 1.U).fpWen := false.B 1244 csBundle(lmul - 1.U).vecWen := false.B 1245 csBundle(lmul - 1.U).ldest := dest 1246 } 1247 1248 is(UopSplitType.VEC_MVV) { 1249 // LMUL 1250 for (i <- 0 until MAX_VLMUL) { 1251 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1252 csBundle(i * 2 + 0).srcType(0) := srcType0 1253 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1254 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1255 csBundle(i * 2 + 0).lsrc(1) := src2 1256 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1257 csBundle(i * 2 + 0).ldest := dest + i.U 1258 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1259 1260 csBundle(i * 2 + 1).srcType(0) := srcType0 1261 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1262 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1263 csBundle(i * 2 + 1).lsrc(1) := src2 1264 // csBundle(i).lsrc(2) := dest + i.U DontCare 1265 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1266 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1267 } 1268 } 1269 1270 is(UopSplitType.VEC_M0X_VFIRST) { 1271 // LMUL 1272 csBundle(0).rfWen := true.B 1273 csBundle(0).fpWen := false.B 1274 csBundle(0).vecWen := false.B 1275 csBundle(0).ldest := dest 1276 } 1277 is(UopSplitType.VEC_VWW) { 1278 for (i <- 0 until MAX_VLMUL*2) { 1279 when(i.U < lmul){ 1280 csBundle(i).srcType(2) := SrcType.DC 1281 csBundle(i).lsrc(0) := src2 + i.U 1282 csBundle(i).lsrc(1) := src2 + i.U 1283 // csBundle(i).lsrc(2) := dest + (2 * i).U 1284 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1285 csBundle(i).uopIdx := i.U 1286 } otherwise { 1287 csBundle(i).srcType(2) := SrcType.DC 1288 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1289 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1290 // csBundle(i).lsrc(2) := dest + (2 * i).U 1291 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1292 csBundle(i).uopIdx := i.U 1293 } 1294 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1295 csBundle(numOfUop-1.U).lsrc(0) := src1 1296 csBundle(numOfUop-1.U).lsrc(2) := dest 1297 csBundle(numOfUop-1.U).ldest := dest 1298 } 1299 } 1300 is(UopSplitType.VEC_RGATHER) { 1301 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1302 for (i <- 0 until len) 1303 for (j <- 0 until len) { 1304 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1305 // csBundle(i * len + j).srcType(1) := SrcType.vp 1306 // csBundle(i * len + j).srcType(2) := SrcType.vp 1307 csBundle(i * len + j).lsrc(0) := src1 + i.U 1308 csBundle(i * len + j).lsrc(1) := src2 + j.U 1309 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1310 csBundle(i * len + j).lsrc(2) := vd_old 1311 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1312 csBundle(i * len + j).ldest := vd 1313 csBundle(i * len + j).uopIdx := (i * len + j).U 1314 } 1315 } 1316 switch(vlmulReg) { 1317 is("b001".U ){ 1318 genCsBundle_VEC_RGATHER(2) 1319 } 1320 is("b010".U ){ 1321 genCsBundle_VEC_RGATHER(4) 1322 } 1323 is("b011".U ){ 1324 genCsBundle_VEC_RGATHER(8) 1325 } 1326 } 1327 } 1328 is(UopSplitType.VEC_RGATHER_VX) { 1329 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1330 for (i <- 0 until len) 1331 for (j <- 0 until len) { 1332 csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1333 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1334 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1335 csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1336 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1337 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1338 csBundle(i * len + j + 1).lsrc(2) := vd_old 1339 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1340 csBundle(i * len + j + 1).ldest := vd 1341 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1342 } 1343 } 1344 // i to vector move 1345 csBundle(0).srcType(0) := SrcType.reg 1346 csBundle(0).srcType(1) := SrcType.imm 1347 csBundle(0).lsrc(1) := 0.U 1348 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1349 csBundle(0).fuType := FuType.i2v.U 1350 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1351 csBundle(0).vecWen := true.B 1352 switch(vlmulReg) { 1353 is("b000".U ){ 1354 genCsBundle_RGATHER_VX(1) 1355 } 1356 is("b001".U ){ 1357 genCsBundle_RGATHER_VX(2) 1358 } 1359 is("b010".U ){ 1360 genCsBundle_RGATHER_VX(4) 1361 } 1362 is("b011".U ){ 1363 genCsBundle_RGATHER_VX(8) 1364 } 1365 } 1366 } 1367 is(UopSplitType.VEC_RGATHEREI16) { 1368 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1369 for (i <- 0 until len) 1370 for (j <- 0 until len) { 1371 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1372 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1373 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1374 // csBundle(i * len + j).srcType(1) := SrcType.vp 1375 // csBundle(i * len + j).srcType(2) := SrcType.vp 1376 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1377 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1378 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1379 csBundle((i * len + j)*2+0).ldest := vd0 1380 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1381 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1382 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1383 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1384 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1385 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1386 csBundle((i * len + j)*2+1).ldest := vd1 1387 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1388 } 1389 } 1390 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1391 for (i <- 0 until len) 1392 for (j <- 0 until len) { 1393 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1394 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1395 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1396 // csBundle(i * len + j).srcType(1) := SrcType.vp 1397 // csBundle(i * len + j).srcType(2) := SrcType.vp 1398 csBundle(i * len + j).lsrc(0) := src1 + i.U 1399 csBundle(i * len + j).lsrc(1) := src2 + j.U 1400 csBundle(i * len + j).lsrc(2) := vd_old 1401 csBundle(i * len + j).ldest := vd 1402 csBundle(i * len + j).uopIdx := (i * len + j).U 1403 } 1404 } 1405 switch(vlmulReg) { 1406 is("b000".U ){ 1407 when(!vsewReg.orR){ 1408 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1409 } .otherwise{ 1410 genCsBundle_VEC_RGATHEREI16(1) 1411 } 1412 } 1413 is("b001".U) { 1414 when(!vsewReg.orR) { 1415 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1416 }.otherwise { 1417 genCsBundle_VEC_RGATHEREI16(2) 1418 } 1419 } 1420 is("b010".U) { 1421 when(!vsewReg.orR) { 1422 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1423 }.otherwise { 1424 genCsBundle_VEC_RGATHEREI16(4) 1425 } 1426 } 1427 is("b011".U) { 1428 genCsBundle_VEC_RGATHEREI16(8) 1429 } 1430 } 1431 } 1432 is(UopSplitType.VEC_COMPRESS) { 1433 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1434 for (i <- 0 until len){ 1435 val jlen = if (i == len-1) i+1 else i+2 1436 for (j <- 0 until jlen) { 1437 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1438 val vd = if(i==len-1) (dest + j.U) else{ 1439 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1440 } 1441 val src23Type = if (j == i+1) DontCare else SrcType.vp 1442 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1443 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1444 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1445 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1446 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1447 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1448 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1449 csBundle(i*(i+3)/2 + j).ldest := vd 1450 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1451 } 1452 } 1453 } 1454 switch(vlmulReg) { 1455 is("b001".U ){ 1456 genCsBundle_VEC_COMPRESS(2) 1457 } 1458 is("b010".U ){ 1459 genCsBundle_VEC_COMPRESS(4) 1460 } 1461 is("b011".U ){ 1462 genCsBundle_VEC_COMPRESS(8) 1463 } 1464 } 1465 } 1466 is(UopSplitType.VEC_MVNR) { 1467 for (i <- 0 until MAX_VLMUL) { 1468 csBundle(i).lsrc(0) := src1 + i.U 1469 csBundle(i).lsrc(1) := src2 + i.U 1470 csBundle(i).lsrc(2) := dest + i.U 1471 csBundle(i).ldest := dest + i.U 1472 csBundle(i).uopIdx := i.U 1473 } 1474 } 1475 is(UopSplitType.VEC_US_LDST) { 1476 /* 1477 FMV.D.X 1478 */ 1479 csBundle(0).srcType(0) := SrcType.reg 1480 csBundle(0).srcType(1) := SrcType.imm 1481 csBundle(0).lsrc(1) := 0.U 1482 csBundle(0).ldest := FP_TMP_REG_MV.U 1483 csBundle(0).fuType := FuType.i2f.U 1484 csBundle(0).rfWen := false.B 1485 csBundle(0).fpWen := true.B 1486 csBundle(0).vecWen := false.B 1487 csBundle(0).fpu.isAddSub := false.B 1488 csBundle(0).fpu.typeTagIn := FPU.D 1489 csBundle(0).fpu.typeTagOut := FPU.D 1490 csBundle(0).fpu.fromInt := true.B 1491 csBundle(0).fpu.wflags := false.B 1492 csBundle(0).fpu.fpWen := true.B 1493 csBundle(0).fpu.div := false.B 1494 csBundle(0).fpu.sqrt := false.B 1495 csBundle(0).fpu.fcvt := false.B 1496 //LMUL 1497 for (i <- 0 until MAX_VLMUL) { 1498 csBundle(i + 1).srcType(0) := SrcType.fp 1499 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1500 csBundle(i + 1).lsrc(2) := dest + i.U // old vd 1501 csBundle(i + 1).ldest := dest + i.U 1502 csBundle(i + 1).uopIdx := i.U 1503 } 1504 } 1505 is(UopSplitType.VEC_S_LDST) { 1506 /* 1507 FMV.D.X 1508 */ 1509 csBundle(0).srcType(0) := SrcType.reg 1510 csBundle(0).srcType(1) := SrcType.imm 1511 csBundle(0).lsrc(1) := 0.U 1512 csBundle(0).ldest := FP_TMP_REG_MV.U 1513 csBundle(0).fuType := FuType.i2f.U 1514 csBundle(0).rfWen := false.B 1515 csBundle(0).fpWen := true.B 1516 csBundle(0).vecWen := false.B 1517 csBundle(0).fpu.isAddSub := false.B 1518 csBundle(0).fpu.typeTagIn := FPU.D 1519 csBundle(0).fpu.typeTagOut := FPU.D 1520 csBundle(0).fpu.fromInt := true.B 1521 csBundle(0).fpu.wflags := false.B 1522 csBundle(0).fpu.fpWen := true.B 1523 csBundle(0).fpu.div := false.B 1524 csBundle(0).fpu.sqrt := false.B 1525 csBundle(0).fpu.fcvt := false.B 1526 1527 csBundle(1).srcType(0) := SrcType.reg 1528 csBundle(1).srcType(1) := SrcType.imm 1529 csBundle(1).lsrc(0) := latchedInst.lsrc(1) 1530 csBundle(1).lsrc(1) := 0.U 1531 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 1532 csBundle(1).fuType := FuType.i2f.U 1533 csBundle(1).rfWen := false.B 1534 csBundle(1).fpWen := true.B 1535 csBundle(1).vecWen := false.B 1536 csBundle(1).fpu.isAddSub := false.B 1537 csBundle(1).fpu.typeTagIn := FPU.D 1538 csBundle(1).fpu.typeTagOut := FPU.D 1539 csBundle(1).fpu.fromInt := true.B 1540 csBundle(1).fpu.wflags := false.B 1541 csBundle(1).fpu.fpWen := true.B 1542 csBundle(1).fpu.div := false.B 1543 csBundle(1).fpu.sqrt := false.B 1544 csBundle(1).fpu.fcvt := false.B 1545 1546 //LMUL 1547 for (i <- 0 until MAX_VLMUL) { 1548 csBundle(i + 2).srcType(0) := SrcType.fp 1549 csBundle(i + 2).srcType(1) := SrcType.fp 1550 csBundle(i + 2).lsrc(0) := FP_TMP_REG_MV.U 1551 csBundle(i + 2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 1552 csBundle(i + 2).lsrc(2) := dest + i.U // old vd 1553 csBundle(i + 2).ldest := dest + i.U 1554 csBundle(i + 2).uopIdx := i.U 1555 } 1556 } 1557 is(UopSplitType.VEC_I_LDST) { 1558 /* 1559 FMV.D.X 1560 */ 1561 val vlmul = vlmulReg 1562 val vsew = Cat(0.U(1.W), vsewReg) 1563 val veew = Cat(0.U(1.W), width) 1564 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 1565 val simple_lmul = MuxLookup(vlmul, 0.U(2.W), Array( 1566 "b001".U -> 1.U, 1567 "b010".U -> 2.U, 1568 "b011".U -> 3.U 1569 )) 1570 val simple_emul = MuxLookup(vemul, 0.U(2.W), Array( 1571 "b001".U -> 1.U, 1572 "b010".U -> 2.U, 1573 "b011".U -> 3.U 1574 )) 1575 csBundle(0).srcType(0) := SrcType.reg 1576 csBundle(0).srcType(1) := SrcType.imm 1577 csBundle(0).lsrc(1) := 0.U 1578 csBundle(0).ldest := FP_TMP_REG_MV.U 1579 csBundle(0).fuType := FuType.i2f.U 1580 csBundle(0).rfWen := false.B 1581 csBundle(0).fpWen := true.B 1582 csBundle(0).vecWen := false.B 1583 csBundle(0).fpu.isAddSub := false.B 1584 csBundle(0).fpu.typeTagIn := FPU.D 1585 csBundle(0).fpu.typeTagOut := FPU.D 1586 csBundle(0).fpu.fromInt := true.B 1587 csBundle(0).fpu.wflags := false.B 1588 csBundle(0).fpu.fpWen := true.B 1589 csBundle(0).fpu.div := false.B 1590 csBundle(0).fpu.sqrt := false.B 1591 csBundle(0).fpu.fcvt := false.B 1592 1593 //LMUL 1594 for (i <- 0 until MAX_INDEXED_LS_UOPNUM) { 1595 indexedLSRegOffset(i).src := Cat(simple_emul, simple_lmul, nf) 1596 val offsetVs2 = indexedLSRegOffset(i).outOffsetVs2 1597 val offsetVd = indexedLSRegOffset(i).outOffsetVd 1598 val isFirstUopInVd = indexedLSRegOffset(i).outIsFirstUopInVd 1599 csBundle(i + 1).srcType(0) := SrcType.fp 1600 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1601 csBundle(i + 1).lsrc(1) := Mux1H(UIntToOH(offsetVs2, MAX_VLMUL), (0 until MAX_VLMUL).map(j => src2 + j.U)) 1602 /** 1603 * For indexed instructions, VLSU will concatenate all the uops that write the same logic vd register and 1604 * writeback only once for all these uops. However, these uops share the same lsrc(2)/old vd and the same 1605 * ldest/vd that is equal to old vd, which leads to data dependence between the uops. Therefore there will be 1606 * deadlock for indexed instructions with emul > lmul. 1607 * 1608 * Assume N = emul/lmul. To break the deadlock, only the first uop will read old vd as lsrc(2), and the rest 1609 * N-1 uops will read temporary vector register. 1610 */ 1611 // csBundle(i + 1).lsrc(2) := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1612 csBundle(i + 1).lsrc(2) := Mux( 1613 isFirstUopInVd, 1614 Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)), 1615 VECTOR_TMP_REG_LMUL.U 1616 ) 1617 csBundle(i + 1).ldest := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1618 csBundle(i + 1).uopIdx := i.U 1619 } 1620 } 1621 } 1622 1623 //readyFromRename Counter 1624 val readyCounter = PriorityMuxDefault(outReadys.map(x => !x).zip((0 until RenameWidth).map(_.U)), RenameWidth.U) 1625 1626 // The left uops of the complex inst in ComplexDecoder can be send out this cycle 1627 val thisAllOut = uopRes <= readyCounter 1628 1629 switch(state) { 1630 is(s_idle) { 1631 when (inValid) { 1632 stateNext := s_active 1633 uopResNext := inUopInfo.numOfUop 1634 } 1635 } 1636 is(s_active) { 1637 when (thisAllOut) { 1638 when (inValid) { 1639 stateNext := s_active 1640 uopResNext := inUopInfo.numOfUop 1641 }.otherwise { 1642 stateNext := s_idle 1643 uopResNext := 0.U 1644 } 1645 }.otherwise { 1646 stateNext := s_active 1647 uopResNext := uopRes - readyCounter 1648 } 1649 } 1650 } 1651 1652 state := Mux(io.redirect, s_idle, stateNext) 1653 uopRes := Mux(io.redirect, 0.U, uopResNext) 1654 1655 val complexNum = Mux(uopRes > readyCounter, readyCounter, uopRes) 1656 1657 for(i <- 0 until RenameWidth) { 1658 outValids(i) := complexNum > i.U 1659 outDecodedInsts(i) := Mux((i.U + numOfUop - uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1660 } 1661 1662 outComplexNum := Mux(state === s_active, complexNum, 0.U) 1663 inReady := state === s_idle || state === s_active && thisAllOut 1664 1665// val validSimple = Wire(Vec(DecodeWidth, Bool())) 1666// validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1667// val notInf = Wire(Vec(DecodeWidth, Bool())) 1668// notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1669// notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1670// val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1671// notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1672// 1673// complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1674// Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1675// 0.U) 1676// validToRename.zipWithIndex.foreach{ 1677// case(dst, i) => 1678// val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1679// dst := MuxCase(false.B, Seq( 1680// (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1681// (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1682// ).toSeq) 1683// } 1684// 1685// readyToIBuf.zipWithIndex.foreach { 1686// case (dst, i) => 1687// val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1688// dst := MuxCase(true.B, Seq( 1689// (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1690// (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1691// ).toSeq) 1692// } 1693// 1694// io.deq.decodedInsts := decodedInsts 1695// io.deq.complexNum := complexNum 1696// io.deq.validToRename := validToRename 1697// io.deq.readyToIBuf := readyToIBuf 1698} 1699