1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35import scala.collection.Seq 36import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 37 38class indexedLSUopTable(uopIdx:Int) extends Module { 39 val src = IO(Input(UInt(7.W))) 40 val outOffsetVs2 = IO(Output(UInt(3.W))) 41 val outOffsetVd = IO(Output(UInt(3.W))) 42 def genCsBundle_VEC_INDEXED_LDST(lmul:Int, emul:Int, nfields:Int, uopIdx:Int): (Int, Int) ={ 43 if (lmul * nfields <= 8) { 44 for (k <-0 until nfields) { 45 if (lmul < emul) { // lmul < emul, uop num is depend on emul * nf 46 var offset = 1 << (emul - lmul) 47 for (i <- 0 until emul) { 48 if (uopIdx == k * (1 << emul) + (1 << i)) { 49 return ((1 << i), (1 << i) / offset + k * (1 << lmul)) 50 } 51 } 52 } else { // lmul > emul, uop num is depend on lmul * nf 53 var offset = 1 << (lmul - emul) 54 for (i <- 0 until lmul) { 55 if (uopIdx == k * (1 << lmul) + (1 << i)) { 56 return ((1 << i) / offset, (1 << i) + k * (1 << lmul)) 57 } 58 } 59 } 60 } 61 } 62 return (0, 0) 63 } 64 // strided load/store 65 var combVemulNf : Seq[(Int, Int, Int, Int, Int)] = Seq() 66 for (emul <- 0 until 4) { 67 for (lmul <- 0 until 4) { 68 for (nf <- 0 until 8) { 69 var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, nf, uopIdx) 70 var offsetVs2 = offset._1 71 var offsetVd = offset._2 72 combVemulNf :+= (emul, lmul, nf, offsetVs2, offsetVd) 73 } 74 } 75 } 76 val out = decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 77 case (emul, lmul, nf, offsetVs2, offsetVd) => (BitPat((emul << 5 | lmul << 3 | nf).U(7.W)), BitPat((offsetVs2 << 3 | offsetVd).U(6.W))) 78 }, BitPat.N(6))) 79 outOffsetVs2 := out(5, 3) 80 outOffsetVd := out(2, 0) 81} 82 83trait VectorConstants { 84 val MAX_VLMUL = 8 85 val FP_TMP_REG_MV = 32 86 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 87 val MAX_INDEXED_LS_UOPNUM = 64 88} 89 90class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 91 val simple = new Bundle { 92 val decodedInst = Input(new DecodedInst) 93 val isComplex = Input(Bool()) 94 val uopInfo = Input(new UopInfo) 95 } 96 val vtype = Input(new VType) 97 val in0pc = Input(UInt(VAddrBits.W)) 98 val isComplex = Input(Vec(DecodeWidth, Bool())) 99 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 100 val readyFromRename = Input(Vec(RenameWidth, Bool())) 101 val deq = new Bundle { 102 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 103 val isVset = Output(Bool()) 104 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 105 val validToRename = Output(Vec(RenameWidth, Bool())) 106 val complexNum = Output(UInt(3.W)) 107 } 108 val csrCtrl = Input(new CustomCSRCtrlIO) 109} 110 111/** 112 * @author zly 113 */ 114class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 115 val io = IO(new DecodeUnitCompIO) 116 117 val maxUopSize = MaxUopSize 118 //input bits 119 private val inst: XSInstBitFields = io.simple.decodedInst.instr.asTypeOf(new XSInstBitFields) 120 121 val src1 = Cat(0.U(1.W), inst.RS1) 122 val src2 = Cat(0.U(1.W), inst.RS2) 123 val dest = Cat(0.U(1.W), inst.RD) 124 125 val nf = inst.NF 126 val width = inst.WIDTH(1, 0) 127 128 //output bits 129 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 130 val validToRename = Wire(Vec(RenameWidth, Bool())) 131 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 132 val complexNum = Wire(UInt(3.W)) 133 134 //output of DecodeUnit 135 val decodedInstsSimple = Wire(new DecodedInst) 136 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 137 val lmul = Wire(UInt(4.W)) 138 val isVsetSimple = Wire(Bool()) 139 140 val indexedLSRegOffset = Seq.tabulate(MAX_INDEXED_LS_UOPNUM)(i => Module(new indexedLSUopTable(i))) 141 indexedLSRegOffset.map(_.src := 0.U) 142 143 //pre decode 144 decodedInstsSimple := io.simple.decodedInst 145 lmul := io.simple.uopInfo.lmul 146 isVsetSimple := io.simple.decodedInst.isVset 147 val vlmulReg = io.simple.decodedInst.vpu.vlmul 148 val vsewReg = io.simple.decodedInst.vpu.vsew 149 when(isVsetSimple) { 150 when(dest === 0.U && src1 === 0.U) { 151 decodedInstsSimple.fuOpType := VSETOpType.keepVl(io.simple.decodedInst.fuOpType) 152 }.elsewhen(src1 === 0.U) { 153 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(io.simple.decodedInst.fuOpType) 154 } 155 when(io.vtype.illegal){ 156 decodedInstsSimple.flushPipe := true.B 157 } 158 } 159 //Type of uop Div 160 val typeOfSplit = decodedInstsSimple.uopSplitType 161 val src1Type = decodedInstsSimple.srcType(0) 162 val src1IsImm = src1Type === SrcType.imm 163 164 when(typeOfSplit === UopSplitType.DIR) { 165 numOfUop := Mux(dest =/= 0.U, 2.U, 166 Mux(src1 =/= 0.U, 1.U, 167 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 168 } .otherwise { 169 numOfUop := io.simple.uopInfo.numOfUop 170 } 171 172 173 //uop div up to maxUopSize 174 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 175 csBundle.map { case dst => 176 dst := decodedInstsSimple 177 dst.firstUop := false.B 178 dst.lastUop := false.B 179 } 180 181 csBundle(0).numUops := numOfUop 182 csBundle(0).firstUop := true.B 183 csBundle(numOfUop - 1.U).lastUop := true.B 184 185 switch(typeOfSplit) { 186 is(UopSplitType.DIR) { 187 when(isVsetSimple) { 188 when(dest =/= 0.U) { 189 csBundle(0).fuType := FuType.vsetiwi.U 190 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 191 csBundle(0).flushPipe := false.B 192 csBundle(0).rfWen := true.B 193 csBundle(0).vecWen := false.B 194 csBundle(1).ldest := VCONFIG_IDX.U 195 csBundle(1).rfWen := false.B 196 csBundle(1).vecWen := true.B 197 }.elsewhen(src1 =/= 0.U) { 198 csBundle(0).ldest := VCONFIG_IDX.U 199 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 200 csBundle(0).fuType := FuType.vsetfwf.U 201 csBundle(0).srcType(0) := SrcType.vp 202 csBundle(0).lsrc(0) := VCONFIG_IDX.U 203 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 204 csBundle(0).srcType(0) := SrcType.reg 205 csBundle(0).srcType(1) := SrcType.imm 206 csBundle(0).lsrc(1) := 0.U 207 csBundle(0).ldest := FP_TMP_REG_MV.U 208 csBundle(0).fuType := FuType.i2f.U 209 csBundle(0).rfWen := false.B 210 csBundle(0).fpWen := true.B 211 csBundle(0).vecWen := false.B 212 csBundle(0).fpu.isAddSub := false.B 213 csBundle(0).fpu.typeTagIn := FPU.D 214 csBundle(0).fpu.typeTagOut := FPU.D 215 csBundle(0).fpu.fromInt := true.B 216 csBundle(0).fpu.wflags := false.B 217 csBundle(0).fpu.fpWen := true.B 218 csBundle(0).fpu.div := false.B 219 csBundle(0).fpu.sqrt := false.B 220 csBundle(0).fpu.fcvt := false.B 221 csBundle(0).flushPipe := false.B 222 csBundle(1).fuType := FuType.vsetfwf.U 223 csBundle(1).srcType(0) := SrcType.vp 224 csBundle(1).lsrc(0) := VCONFIG_IDX.U 225 csBundle(1).srcType(1) := SrcType.fp 226 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 227 csBundle(1).ldest := VCONFIG_IDX.U 228 } 229 } 230 } 231 is(UopSplitType.VEC_VVV) { 232 for (i <- 0 until MAX_VLMUL) { 233 csBundle(i).lsrc(0) := src1 + i.U 234 csBundle(i).lsrc(1) := src2 + i.U 235 csBundle(i).lsrc(2) := dest + i.U 236 csBundle(i).ldest := dest + i.U 237 csBundle(i).uopIdx := i.U 238 } 239 } 240 is(UopSplitType.VEC_VFV) { 241 for (i <- 0 until MAX_VLMUL) { 242 csBundle(i).lsrc(1) := src2 + i.U 243 csBundle(i).lsrc(2) := dest + i.U 244 csBundle(i).ldest := dest + i.U 245 csBundle(i).uopIdx := i.U 246 } 247 } 248 is(UopSplitType.VEC_EXT2) { 249 for (i <- 0 until MAX_VLMUL / 2) { 250 csBundle(2 * i).lsrc(1) := src2 + i.U 251 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 252 csBundle(2 * i).ldest := dest + (2 * i).U 253 csBundle(2 * i).uopIdx := (2 * i).U 254 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 255 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 256 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 257 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 258 } 259 } 260 is(UopSplitType.VEC_EXT4) { 261 for (i <- 0 until MAX_VLMUL / 4) { 262 csBundle(4 * i).lsrc(1) := src2 + i.U 263 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 264 csBundle(4 * i).ldest := dest + (4 * i).U 265 csBundle(4 * i).uopIdx := (4 * i).U 266 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 267 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 268 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 269 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 270 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 271 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 272 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 273 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 274 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 275 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 276 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 277 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 278 } 279 } 280 is(UopSplitType.VEC_EXT8) { 281 for (i <- 0 until MAX_VLMUL) { 282 csBundle(i).lsrc(1) := src2 283 csBundle(i).lsrc(2) := dest + i.U 284 csBundle(i).ldest := dest + i.U 285 csBundle(i).uopIdx := i.U 286 } 287 } 288 is(UopSplitType.VEC_0XV) { 289 /* 290 FMV.D.X 291 */ 292 csBundle(0).srcType(0) := SrcType.reg 293 csBundle(0).srcType(1) := SrcType.imm 294 csBundle(0).lsrc(1) := 0.U 295 csBundle(0).ldest := FP_TMP_REG_MV.U 296 csBundle(0).fuType := FuType.i2f.U 297 csBundle(0).rfWen := false.B 298 csBundle(0).fpWen := true.B 299 csBundle(0).vecWen := false.B 300 csBundle(0).fpu.isAddSub := false.B 301 csBundle(0).fpu.typeTagIn := FPU.D 302 csBundle(0).fpu.typeTagOut := FPU.D 303 csBundle(0).fpu.fromInt := true.B 304 csBundle(0).fpu.wflags := false.B 305 csBundle(0).fpu.fpWen := true.B 306 csBundle(0).fpu.div := false.B 307 csBundle(0).fpu.sqrt := false.B 308 csBundle(0).fpu.fcvt := false.B 309 /* 310 vfmv.s.f 311 */ 312 csBundle(1).srcType(0) := SrcType.fp 313 csBundle(1).srcType(1) := SrcType.vp 314 csBundle(1).srcType(2) := SrcType.vp 315 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 316 csBundle(1).lsrc(1) := 0.U 317 csBundle(1).lsrc(2) := dest 318 csBundle(1).ldest := dest 319 csBundle(1).fuType := FuType.vppu.U 320 csBundle(1).fuOpType := VpermType.dummy 321 csBundle(1).rfWen := false.B 322 csBundle(1).fpWen := false.B 323 csBundle(1).vecWen := true.B 324 } 325 is(UopSplitType.VEC_VXV) { 326 /* 327 i to vector move 328 */ 329 csBundle(0).srcType(0) := SrcType.reg 330 csBundle(0).srcType(1) := SrcType.imm 331 csBundle(0).lsrc(1) := 0.U 332 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 333 csBundle(0).fuType := FuType.i2v.U 334 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 335 csBundle(0).vecWen := true.B 336 /* 337 LMUL 338 */ 339 for (i <- 0 until MAX_VLMUL) { 340 csBundle(i + 1).srcType(0) := SrcType.vp 341 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 342 csBundle(i + 1).lsrc(1) := src2 + i.U 343 csBundle(i + 1).lsrc(2) := dest + i.U 344 csBundle(i + 1).ldest := dest + i.U 345 csBundle(i + 1).uopIdx := i.U 346 } 347 } 348 is(UopSplitType.VEC_VVW) { 349 for (i <- 0 until MAX_VLMUL / 2) { 350 csBundle(2 * i).lsrc(0) := src1 + i.U 351 csBundle(2 * i).lsrc(1) := src2 + i.U 352 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 353 csBundle(2 * i).ldest := dest + (2 * i).U 354 csBundle(2 * i).uopIdx := (2 * i).U 355 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 356 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 357 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 358 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 359 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 360 } 361 } 362 is(UopSplitType.VEC_VFW) { 363 for (i <- 0 until MAX_VLMUL / 2) { 364 csBundle(2 * i).lsrc(0) := src1 365 csBundle(2 * i).lsrc(1) := src2 + i.U 366 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 367 csBundle(2 * i).ldest := dest + (2 * i).U 368 csBundle(2 * i).uopIdx := (2 * i).U 369 csBundle(2 * i + 1).lsrc(0) := src1 370 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 371 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 372 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 373 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 374 } 375 } 376 is(UopSplitType.VEC_WVW) { 377 for (i <- 0 until MAX_VLMUL / 2) { 378 csBundle(2 * i).lsrc(0) := src1 + i.U 379 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 380 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 381 csBundle(2 * i).ldest := dest + (2 * i).U 382 csBundle(2 * i).uopIdx := (2 * i).U 383 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 384 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 385 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 386 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 387 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 388 } 389 } 390 is(UopSplitType.VEC_VXW) { 391 /* 392 i to vector move 393 */ 394 csBundle(0).srcType(0) := SrcType.reg 395 csBundle(0).srcType(1) := SrcType.imm 396 csBundle(0).lsrc(1) := 0.U 397 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 398 csBundle(0).fuType := FuType.i2v.U 399 csBundle(0).fuOpType := vsewReg 400 csBundle(0).vecWen := true.B 401 402 for (i <- 0 until MAX_VLMUL / 2) { 403 csBundle(2 * i + 1).srcType(0) := SrcType.vp 404 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 405 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 406 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 407 csBundle(2 * i + 1).ldest := dest + (2 * i).U 408 csBundle(2 * i + 1).uopIdx := (2 * i).U 409 csBundle(2 * i + 2).srcType(0) := SrcType.vp 410 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 411 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 412 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 413 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 414 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 415 } 416 } 417 is(UopSplitType.VEC_WXW) { 418 /* 419 i to vector move 420 */ 421 csBundle(0).srcType(0) := SrcType.reg 422 csBundle(0).srcType(1) := SrcType.imm 423 csBundle(0).lsrc(1) := 0.U 424 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 425 csBundle(0).fuType := FuType.i2v.U 426 csBundle(0).fuOpType := vsewReg 427 csBundle(0).vecWen := true.B 428 429 for (i <- 0 until MAX_VLMUL / 2) { 430 csBundle(2 * i + 1).srcType(0) := SrcType.vp 431 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 432 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 433 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 434 csBundle(2 * i + 1).ldest := dest + (2 * i).U 435 csBundle(2 * i + 1).uopIdx := (2 * i).U 436 csBundle(2 * i + 2).srcType(0) := SrcType.vp 437 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 438 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 439 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 440 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 441 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 442 } 443 } 444 is(UopSplitType.VEC_WVV) { 445 for (i <- 0 until MAX_VLMUL / 2) { 446 447 csBundle(2 * i).lsrc(0) := src1 + i.U 448 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 449 csBundle(2 * i).lsrc(2) := dest + i.U 450 csBundle(2 * i).ldest := dest + i.U 451 csBundle(2 * i).uopIdx := (2 * i).U 452 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 453 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 454 csBundle(2 * i + 1).lsrc(2) := dest + i.U 455 csBundle(2 * i + 1).ldest := dest + i.U 456 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 457 } 458 } 459 is(UopSplitType.VEC_WFW) { 460 for (i <- 0 until MAX_VLMUL / 2) { 461 csBundle(2 * i).lsrc(0) := src1 462 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 463 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 464 csBundle(2 * i).ldest := dest + (2 * i).U 465 csBundle(2 * i).uopIdx := (2 * i).U 466 csBundle(2 * i + 1).lsrc(0) := src1 467 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 468 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 469 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 470 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 471 } 472 } 473 is(UopSplitType.VEC_WXV) { 474 /* 475 i to vector move 476 */ 477 csBundle(0).srcType(0) := SrcType.reg 478 csBundle(0).srcType(1) := SrcType.imm 479 csBundle(0).lsrc(1) := 0.U 480 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 481 csBundle(0).fuType := FuType.i2v.U 482 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 483 csBundle(0).vecWen := true.B 484 485 for (i <- 0 until MAX_VLMUL / 2) { 486 csBundle(2 * i + 1).srcType(0) := SrcType.vp 487 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 488 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 489 csBundle(2 * i + 1).lsrc(2) := dest + i.U 490 csBundle(2 * i + 1).ldest := dest + i.U 491 csBundle(2 * i + 1).uopIdx := (2 * i).U 492 csBundle(2 * i + 2).srcType(0) := SrcType.vp 493 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 494 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 495 csBundle(2 * i + 2).lsrc(2) := dest + i.U 496 csBundle(2 * i + 2).ldest := dest + i.U 497 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 498 } 499 } 500 is(UopSplitType.VEC_VVM) { 501 csBundle(0).lsrc(2) := dest 502 csBundle(0).ldest := dest 503 csBundle(0).uopIdx := 0.U 504 for (i <- 1 until MAX_VLMUL) { 505 csBundle(i).lsrc(0) := src1 + i.U 506 csBundle(i).lsrc(1) := src2 + i.U 507 csBundle(i).lsrc(2) := dest 508 csBundle(i).ldest := dest 509 csBundle(i).uopIdx := i.U 510 } 511 } 512 is(UopSplitType.VEC_VFM) { 513 csBundle(0).lsrc(2) := dest 514 csBundle(0).ldest := dest 515 csBundle(0).uopIdx := 0.U 516 for (i <- 1 until MAX_VLMUL) { 517 csBundle(i).lsrc(0) := src1 518 csBundle(i).lsrc(1) := src2 + i.U 519 csBundle(i).lsrc(2) := dest 520 csBundle(i).ldest := dest 521 csBundle(i).uopIdx := i.U 522 } 523 csBundle(numOfUop - 1.U).ldest := dest 524 } 525 is(UopSplitType.VEC_VXM) { 526 /* 527 i to vector move 528 */ 529 csBundle(0).srcType(0) := SrcType.reg 530 csBundle(0).srcType(1) := SrcType.imm 531 csBundle(0).lsrc(1) := 0.U 532 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 533 csBundle(0).fuType := FuType.i2v.U 534 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 535 csBundle(0).vecWen := true.B 536 //LMUL 537 csBundle(1).srcType(0) := SrcType.vp 538 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 539 csBundle(1).lsrc(2) := dest 540 csBundle(1).ldest := dest 541 csBundle(1).uopIdx := 0.U 542 for (i <- 1 until MAX_VLMUL) { 543 csBundle(i + 1).srcType(0) := SrcType.vp 544 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 545 csBundle(i + 1).lsrc(1) := src2 + i.U 546 csBundle(i + 1).lsrc(2) := dest 547 csBundle(i + 1).ldest := dest 548 csBundle(i + 1).uopIdx := i.U 549 } 550 csBundle(numOfUop - 1.U).ldest := dest 551 } 552 is(UopSplitType.VEC_SLIDE1UP) { 553 /* 554 i to vector move 555 */ 556 csBundle(0).srcType(0) := SrcType.reg 557 csBundle(0).srcType(1) := SrcType.imm 558 csBundle(0).lsrc(1) := 0.U 559 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 560 csBundle(0).fuType := FuType.i2v.U 561 csBundle(0).fuOpType := vsewReg 562 csBundle(0).vecWen := true.B 563 //LMUL 564 csBundle(1).srcType(0) := SrcType.vp 565 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 566 csBundle(1).lsrc(2) := dest 567 csBundle(1).ldest := dest 568 csBundle(1).uopIdx := 0.U 569 for (i <- 1 until MAX_VLMUL) { 570 csBundle(i + 1).srcType(0) := SrcType.vp 571 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 572 csBundle(i + 1).lsrc(1) := src2 + i.U 573 csBundle(i + 1).lsrc(2) := dest + i.U 574 csBundle(i + 1).ldest := dest + i.U 575 csBundle(i + 1).uopIdx := i.U 576 } 577 } 578 is(UopSplitType.VEC_FSLIDE1UP) { 579 //LMUL 580 csBundle(0).srcType(0) := SrcType.fp 581 csBundle(0).lsrc(0) := src1 582 csBundle(0).lsrc(1) := src2 583 csBundle(0).lsrc(2) := dest 584 csBundle(0).ldest := dest 585 csBundle(0).uopIdx := 0.U 586 for (i <- 1 until MAX_VLMUL) { 587 csBundle(i).srcType(0) := SrcType.vp 588 csBundle(i).lsrc(0) := src2 + (i - 1).U 589 csBundle(i).lsrc(1) := src2 + i.U 590 csBundle(i).lsrc(2) := dest + i.U 591 csBundle(i).ldest := dest + i.U 592 csBundle(i).uopIdx := i.U 593 } 594 } 595 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 596 /* 597 i to vector move 598 */ 599 csBundle(0).srcType(0) := SrcType.reg 600 csBundle(0).srcType(1) := SrcType.imm 601 csBundle(0).lsrc(1) := 0.U 602 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 603 csBundle(0).fuType := FuType.i2v.U 604 csBundle(0).fuOpType := vsewReg 605 csBundle(0).vecWen := true.B 606 //LMUL 607 for (i <- 0 until MAX_VLMUL) { 608 csBundle(2 * i + 1).srcType(0) := SrcType.vp 609 csBundle(2 * i + 1).srcType(1) := SrcType.vp 610 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 611 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 612 csBundle(2 * i + 1).lsrc(2) := dest + i.U 613 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 614 csBundle(2 * i + 1).uopIdx := (2 * i).U 615 if (2 * i + 2 < MAX_VLMUL * 2) { 616 csBundle(2 * i + 2).srcType(0) := SrcType.vp 617 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 618 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 619 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 620 csBundle(2 * i + 2).ldest := dest + i.U 621 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 622 } 623 } 624 csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 625 csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 626 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 627 } 628 is(UopSplitType.VEC_FSLIDE1DOWN) { 629 //LMUL 630 for (i <- 0 until MAX_VLMUL) { 631 csBundle(2 * i).srcType(0) := SrcType.vp 632 csBundle(2 * i).srcType(1) := SrcType.vp 633 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 634 csBundle(2 * i).lsrc(1) := src2 + i.U 635 csBundle(2 * i).lsrc(2) := dest + i.U 636 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 637 csBundle(2 * i).uopIdx := (2 * i).U 638 csBundle(2 * i + 1).srcType(0) := SrcType.fp 639 csBundle(2 * i + 1).lsrc(0) := src1 640 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 641 csBundle(2 * i + 1).ldest := dest + i.U 642 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 643 } 644 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 645 csBundle(numOfUop - 1.U).lsrc(0) := src1 646 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 647 } 648 is(UopSplitType.VEC_VRED) { 649 when(vlmulReg === "b001".U) { 650 csBundle(0).srcType(2) := SrcType.DC 651 csBundle(0).lsrc(0) := src2 + 1.U 652 csBundle(0).lsrc(1) := src2 653 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 654 csBundle(0).uopIdx := 0.U 655 } 656 when(vlmulReg === "b010".U) { 657 csBundle(0).srcType(2) := SrcType.DC 658 csBundle(0).lsrc(0) := src2 + 1.U 659 csBundle(0).lsrc(1) := src2 660 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 661 csBundle(0).uopIdx := 0.U 662 663 csBundle(1).srcType(2) := SrcType.DC 664 csBundle(1).lsrc(0) := src2 + 3.U 665 csBundle(1).lsrc(1) := src2 + 2.U 666 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 667 csBundle(1).uopIdx := 1.U 668 669 csBundle(2).srcType(2) := SrcType.DC 670 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 671 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 672 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 673 csBundle(2).uopIdx := 2.U 674 } 675 when(vlmulReg === "b011".U) { 676 for (i <- 0 until MAX_VLMUL) { 677 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 678 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 679 csBundle(i).lsrc(1) := src2 + (i * 2).U 680 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 681 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 682 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 683 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 684 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 685 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 686 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 687 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 688 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 689 } 690 csBundle(i).srcType(2) := SrcType.DC 691 csBundle(i).uopIdx := i.U 692 } 693 } 694 when(vlmulReg.orR) { 695 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 696 csBundle(numOfUop - 1.U).lsrc(0) := src1 697 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 698 csBundle(numOfUop - 1.U).lsrc(2) := dest 699 csBundle(numOfUop - 1.U).ldest := dest 700 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 701 } 702 } 703 is(UopSplitType.VEC_VFRED) { 704 val vlmul = vlmulReg 705 val vsew = vsewReg 706 when(vlmul === VLmul.m8){ 707 for (i <- 0 until 4) { 708 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 709 csBundle(i).lsrc(1) := src2 + (i * 2).U 710 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 711 csBundle(i).uopIdx := i.U 712 } 713 for (i <- 4 until 6) { 714 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 715 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 716 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 717 csBundle(i).uopIdx := i.U 718 } 719 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 720 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 721 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 722 csBundle(6).uopIdx := 6.U 723 when(vsew === VSew.e64) { 724 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 725 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 726 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 727 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 728 csBundle(7).uopIdx := 7.U 729 csBundle(8).lsrc(0) := src1 730 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 731 csBundle(8).ldest := dest 732 csBundle(8).uopIdx := 8.U 733 } 734 when(vsew === VSew.e32) { 735 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 736 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 737 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 738 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 739 csBundle(7).uopIdx := 7.U 740 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 741 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 742 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 743 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 744 csBundle(8).uopIdx := 8.U 745 csBundle(9).lsrc(0) := src1 746 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 747 csBundle(9).ldest := dest 748 csBundle(9).uopIdx := 9.U 749 } 750 when(vsew === VSew.e16) { 751 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 752 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 753 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 754 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 755 csBundle(7).uopIdx := 7.U 756 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 757 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 758 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 759 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 760 csBundle(8).uopIdx := 8.U 761 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 762 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 763 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 764 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 765 csBundle(9).uopIdx := 9.U 766 csBundle(10).lsrc(0) := src1 767 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 768 csBundle(10).ldest := dest 769 csBundle(10).uopIdx := 10.U 770 } 771 } 772 when(vlmul === VLmul.m4) { 773 for (i <- 0 until 2) { 774 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 775 csBundle(i).lsrc(1) := src2 + (i * 2).U 776 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 777 csBundle(i).uopIdx := i.U 778 } 779 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 780 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 781 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 782 csBundle(2).uopIdx := 2.U 783 when(vsew === VSew.e64) { 784 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 785 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 786 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 787 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 788 csBundle(3).uopIdx := 3.U 789 csBundle(4).lsrc(0) := src1 790 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 791 csBundle(4).ldest := dest 792 csBundle(4).uopIdx := 4.U 793 } 794 when(vsew === VSew.e32) { 795 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 796 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 797 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 798 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 799 csBundle(3).uopIdx := 3.U 800 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 801 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 802 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 803 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 804 csBundle(4).uopIdx := 4.U 805 csBundle(5).lsrc(0) := src1 806 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 807 csBundle(5).ldest := dest 808 csBundle(5).uopIdx := 5.U 809 } 810 when(vsew === VSew.e16) { 811 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 812 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 813 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 814 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 815 csBundle(3).uopIdx := 3.U 816 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 817 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 818 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 819 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 820 csBundle(4).uopIdx := 4.U 821 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 822 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 823 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 824 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 825 csBundle(5).uopIdx := 5.U 826 csBundle(6).lsrc(0) := src1 827 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 828 csBundle(6).ldest := dest 829 csBundle(6).uopIdx := 6.U 830 } 831 } 832 when(vlmul === VLmul.m2) { 833 csBundle(0).lsrc(0) := src2 + 1.U 834 csBundle(0).lsrc(1) := src2 + 0.U 835 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 836 csBundle(0).uopIdx := 0.U 837 when(vsew === VSew.e64) { 838 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 839 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 840 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 841 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 842 csBundle(1).uopIdx := 1.U 843 csBundle(2).lsrc(0) := src1 844 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 845 csBundle(2).ldest := dest 846 csBundle(2).uopIdx := 2.U 847 } 848 when(vsew === VSew.e32) { 849 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 850 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 851 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 852 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 853 csBundle(1).uopIdx := 1.U 854 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 855 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 856 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 857 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 858 csBundle(2).uopIdx := 2.U 859 csBundle(3).lsrc(0) := src1 860 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 861 csBundle(3).ldest := dest 862 csBundle(3).uopIdx := 3.U 863 } 864 when(vsew === VSew.e16) { 865 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 866 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 867 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 868 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 869 csBundle(1).uopIdx := 1.U 870 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 871 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 872 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 873 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 874 csBundle(2).uopIdx := 2.U 875 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 876 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 877 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 878 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 879 csBundle(3).uopIdx := 3.U 880 csBundle(4).lsrc(0) := src1 881 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 882 csBundle(4).ldest := dest 883 csBundle(4).uopIdx := 4.U 884 } 885 } 886 when(vlmul === VLmul.m1) { 887 when(vsew === VSew.e64) { 888 csBundle(0).lsrc(0) := src2 889 csBundle(0).lsrc(1) := src2 890 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 891 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 892 csBundle(0).uopIdx := 0.U 893 csBundle(1).lsrc(0) := src1 894 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 895 csBundle(1).ldest := dest 896 csBundle(1).uopIdx := 1.U 897 } 898 when(vsew === VSew.e32) { 899 csBundle(0).lsrc(0) := src2 900 csBundle(0).lsrc(1) := src2 901 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 902 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 903 csBundle(0).uopIdx := 0.U 904 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 905 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 906 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 907 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 908 csBundle(1).uopIdx := 1.U 909 csBundle(2).lsrc(0) := src1 910 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 911 csBundle(2).ldest := dest 912 csBundle(2).uopIdx := 2.U 913 } 914 when(vsew === VSew.e16) { 915 csBundle(0).lsrc(0) := src2 916 csBundle(0).lsrc(1) := src2 917 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 918 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 919 csBundle(0).uopIdx := 0.U 920 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 921 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 922 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 923 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 924 csBundle(1).uopIdx := 1.U 925 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 926 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 927 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 928 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 929 csBundle(2).uopIdx := 2.U 930 csBundle(3).lsrc(0) := src1 931 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 932 csBundle(3).ldest := dest 933 csBundle(3).uopIdx := 3.U 934 } 935 } 936 when(vlmul === VLmul.mf2) { 937 when(vsew === VSew.e32) { 938 csBundle(0).lsrc(0) := src2 939 csBundle(0).lsrc(1) := src2 940 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 941 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 942 csBundle(0).uopIdx := 0.U 943 csBundle(1).lsrc(0) := src1 944 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 945 csBundle(1).ldest := dest 946 csBundle(1).uopIdx := 1.U 947 } 948 when(vsew === VSew.e16) { 949 csBundle(0).lsrc(0) := src2 950 csBundle(0).lsrc(1) := src2 951 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 952 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 953 csBundle(0).uopIdx := 0.U 954 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 955 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 956 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 957 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 958 csBundle(1).uopIdx := 1.U 959 csBundle(2).lsrc(0) := src1 960 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 961 csBundle(2).ldest := dest 962 csBundle(2).uopIdx := 2.U 963 } 964 } 965 when(vlmul === VLmul.mf4) { 966 when(vsew === VSew.e16) { 967 csBundle(0).lsrc(0) := src2 968 csBundle(0).lsrc(1) := src2 969 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 970 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 971 csBundle(0).uopIdx := 0.U 972 csBundle(1).lsrc(0) := src1 973 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 974 csBundle(1).ldest := dest 975 csBundle(1).uopIdx := 1.U 976 } 977 } 978 } 979 980 is(UopSplitType.VEC_VFREDOSUM) { 981 import yunsuan.VfaluType 982 val vlmul = vlmulReg 983 val vsew = vsewReg 984 val isWiden = decodedInstsSimple.fuOpType === VfaluType.vfwredosum 985 when(vlmul === VLmul.m8) { 986 when(vsew === VSew.e64) { 987 val vlmax = 16 988 for (i <- 0 until vlmax) { 989 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 990 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 991 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 992 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 993 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 994 csBundle(i).uopIdx := i.U 995 } 996 } 997 when(vsew === VSew.e32) { 998 val vlmax = 32 999 for (i <- 0 until vlmax) { 1000 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1001 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1002 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1003 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1004 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1005 csBundle(i).uopIdx := i.U 1006 } 1007 } 1008 when(vsew === VSew.e16) { 1009 val vlmax = 64 1010 for (i <- 0 until vlmax) { 1011 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1012 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1013 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1014 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1015 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1016 csBundle(i).uopIdx := i.U 1017 } 1018 } 1019 } 1020 when(vlmul === VLmul.m4) { 1021 when(vsew === VSew.e64) { 1022 val vlmax = 8 1023 for (i <- 0 until vlmax) { 1024 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1025 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1026 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1027 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1028 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1029 csBundle(i).uopIdx := i.U 1030 } 1031 } 1032 when(vsew === VSew.e32) { 1033 val vlmax = 16 1034 for (i <- 0 until vlmax) { 1035 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1036 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1037 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1038 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1039 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1040 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1041 csBundle(i).uopIdx := i.U 1042 } 1043 } 1044 when(vsew === VSew.e16) { 1045 val vlmax = 32 1046 for (i <- 0 until vlmax) { 1047 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1048 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1049 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1050 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1051 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1052 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1053 csBundle(i).uopIdx := i.U 1054 } 1055 } 1056 } 1057 when(vlmul === VLmul.m2) { 1058 when(vsew === VSew.e64) { 1059 val vlmax = 4 1060 for (i <- 0 until vlmax) { 1061 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1062 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1063 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1064 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1065 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1066 csBundle(i).uopIdx := i.U 1067 } 1068 } 1069 when(vsew === VSew.e32) { 1070 val vlmax = 8 1071 for (i <- 0 until vlmax) { 1072 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1073 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1074 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1075 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1076 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1077 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1078 csBundle(i).uopIdx := i.U 1079 } 1080 } 1081 when(vsew === VSew.e16) { 1082 val vlmax = 16 1083 for (i <- 0 until vlmax) { 1084 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1085 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1086 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1087 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1088 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1089 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1090 csBundle(i).uopIdx := i.U 1091 } 1092 } 1093 } 1094 when(vlmul === VLmul.m1) { 1095 when(vsew === VSew.e64) { 1096 val vlmax = 2 1097 for (i <- 0 until vlmax) { 1098 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1099 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1100 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1101 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1102 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1103 csBundle(i).uopIdx := i.U 1104 } 1105 } 1106 when(vsew === VSew.e32) { 1107 val vlmax = 4 1108 for (i <- 0 until vlmax) { 1109 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1110 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1111 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1112 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1113 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1114 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1115 csBundle(i).uopIdx := i.U 1116 } 1117 } 1118 when(vsew === VSew.e16) { 1119 val vlmax = 8 1120 for (i <- 0 until vlmax) { 1121 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1122 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1123 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1124 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1125 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1126 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1127 csBundle(i).uopIdx := i.U 1128 } 1129 } 1130 } 1131 when(vlmul === VLmul.mf2) { 1132 when(vsew === VSew.e32) { 1133 val vlmax = 2 1134 for (i <- 0 until vlmax) { 1135 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1136 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1137 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1138 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1139 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1140 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1141 csBundle(i).uopIdx := i.U 1142 } 1143 } 1144 when(vsew === VSew.e16) { 1145 val vlmax = 4 1146 for (i <- 0 until vlmax) { 1147 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1148 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1149 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1150 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1151 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1152 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1153 csBundle(i).uopIdx := i.U 1154 } 1155 } 1156 } 1157 when(vlmul === VLmul.mf4) { 1158 when(vsew === VSew.e16) { 1159 val vlmax = 2 1160 for (i <- 0 until vlmax) { 1161 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1162 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1163 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1164 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1165 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1166 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1167 csBundle(i).uopIdx := i.U 1168 } 1169 } 1170 } 1171 } 1172 1173 is(UopSplitType.VEC_SLIDEUP) { 1174 // i to vector move 1175 csBundle(0).srcType(0) := SrcType.reg 1176 csBundle(0).srcType(1) := SrcType.imm 1177 csBundle(0).lsrc(1) := 0.U 1178 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1179 csBundle(0).fuType := FuType.i2v.U 1180 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1181 csBundle(0).vecWen := true.B 1182 // LMUL 1183 for (i <- 0 until MAX_VLMUL) 1184 for (j <- 0 to i) { 1185 val old_vd = if (j == 0) { 1186 dest + i.U 1187 } else (VECTOR_TMP_REG_LMUL + j).U 1188 val vd = if (j == i) { 1189 dest + i.U 1190 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1191 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1192 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1193 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1194 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1195 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1196 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1197 } 1198 } 1199 1200 is(UopSplitType.VEC_SLIDEDOWN) { 1201 // i to vector move 1202 csBundle(0).srcType(0) := SrcType.reg 1203 csBundle(0).srcType(1) := SrcType.imm 1204 csBundle(0).lsrc(1) := 0.U 1205 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1206 csBundle(0).fuType := FuType.i2v.U 1207 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1208 csBundle(0).vecWen := true.B 1209 // LMUL 1210 for (i <- 0 until MAX_VLMUL) 1211 for (j <- (0 to i).reverse) { 1212 when(i.U < lmul) { 1213 val old_vd = if (j == 0) { 1214 dest + lmul - 1.U - i.U 1215 } else (VECTOR_TMP_REG_LMUL + j).U 1216 val vd = if (j == i) { 1217 dest + lmul - 1.U - i.U 1218 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1219 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1220 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1221 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1222 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1223 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1224 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1225 } 1226 } 1227 } 1228 1229 is(UopSplitType.VEC_M0X) { 1230 // LMUL 1231 for (i <- 0 until MAX_VLMUL) { 1232 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1233 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1234 csBundle(i).srcType(0) := srcType0 1235 csBundle(i).srcType(1) := SrcType.vp 1236 csBundle(i).rfWen := false.B 1237 csBundle(i).vecWen := true.B 1238 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1239 csBundle(i).lsrc(1) := src2 1240 // csBundle(i).lsrc(2) := dest + i.U DontCare 1241 csBundle(i).ldest := ldest 1242 csBundle(i).uopIdx := i.U 1243 } 1244 csBundle(lmul - 1.U).vecWen := false.B 1245 csBundle(lmul - 1.U).fpWen := true.B 1246 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 1247 // FMV_X_D 1248 csBundle(lmul).srcType(0) := SrcType.fp 1249 csBundle(lmul).srcType(1) := SrcType.imm 1250 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 1251 csBundle(lmul).lsrc(1) := 0.U 1252 csBundle(lmul).ldest := dest 1253 csBundle(lmul).fuType := FuType.fmisc.U 1254 csBundle(lmul).rfWen := true.B 1255 csBundle(lmul).fpWen := false.B 1256 csBundle(lmul).vecWen := false.B 1257 csBundle(lmul).fpu.isAddSub := false.B 1258 csBundle(lmul).fpu.typeTagIn := FPU.D 1259 csBundle(lmul).fpu.typeTagOut := FPU.D 1260 csBundle(lmul).fpu.fromInt := false.B 1261 csBundle(lmul).fpu.wflags := false.B 1262 csBundle(lmul).fpu.fpWen := false.B 1263 csBundle(lmul).fpu.div := false.B 1264 csBundle(lmul).fpu.sqrt := false.B 1265 csBundle(lmul).fpu.fcvt := false.B 1266 } 1267 1268 is(UopSplitType.VEC_MVV) { 1269 // LMUL 1270 for (i <- 0 until MAX_VLMUL) { 1271 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1272 csBundle(i * 2 + 0).srcType(0) := srcType0 1273 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1274 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1275 csBundle(i * 2 + 0).lsrc(1) := src2 1276 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1277 csBundle(i * 2 + 0).ldest := dest + i.U 1278 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1279 1280 csBundle(i * 2 + 1).srcType(0) := srcType0 1281 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1282 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1283 csBundle(i * 2 + 1).lsrc(1) := src2 1284 // csBundle(i).lsrc(2) := dest + i.U DontCare 1285 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1286 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1287 } 1288 } 1289 1290 is(UopSplitType.VEC_M0X_VFIRST) { 1291 // LMUL 1292 csBundle(0).rfWen := false.B 1293 csBundle(0).fpWen := true.B 1294 csBundle(0).ldest := FP_TMP_REG_MV.U 1295 // FMV_X_D 1296 csBundle(1).srcType(0) := SrcType.fp 1297 csBundle(1).srcType(1) := SrcType.imm 1298 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 1299 csBundle(1).lsrc(1) := 0.U 1300 csBundle(1).ldest := dest 1301 csBundle(1).fuType := FuType.fmisc.U 1302 csBundle(1).rfWen := true.B 1303 csBundle(1).fpWen := false.B 1304 csBundle(1).vecWen := false.B 1305 csBundle(1).fpu.isAddSub := false.B 1306 csBundle(1).fpu.typeTagIn := FPU.D 1307 csBundle(1).fpu.typeTagOut := FPU.D 1308 csBundle(1).fpu.fromInt := false.B 1309 csBundle(1).fpu.wflags := false.B 1310 csBundle(1).fpu.fpWen := false.B 1311 csBundle(1).fpu.div := false.B 1312 csBundle(1).fpu.sqrt := false.B 1313 csBundle(1).fpu.fcvt := false.B 1314 } 1315 is(UopSplitType.VEC_VWW) { 1316 for (i <- 0 until MAX_VLMUL*2) { 1317 when(i.U < lmul){ 1318 csBundle(i).srcType(2) := SrcType.DC 1319 csBundle(i).lsrc(0) := src2 + i.U 1320 csBundle(i).lsrc(1) := src2 + i.U 1321 // csBundle(i).lsrc(2) := dest + (2 * i).U 1322 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1323 csBundle(i).uopIdx := i.U 1324 } otherwise { 1325 csBundle(i).srcType(2) := SrcType.DC 1326 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1327 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1328 // csBundle(i).lsrc(2) := dest + (2 * i).U 1329 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1330 csBundle(i).uopIdx := i.U 1331 } 1332 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1333 csBundle(numOfUop-1.U).lsrc(0) := src1 1334 csBundle(numOfUop-1.U).lsrc(2) := dest 1335 csBundle(numOfUop-1.U).ldest := dest 1336 } 1337 } 1338 is(UopSplitType.VEC_RGATHER) { 1339 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1340 for (i <- 0 until len) 1341 for (j <- 0 until len) { 1342 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1343 // csBundle(i * len + j).srcType(1) := SrcType.vp 1344 // csBundle(i * len + j).srcType(2) := SrcType.vp 1345 csBundle(i * len + j).lsrc(0) := src1 + i.U 1346 csBundle(i * len + j).lsrc(1) := src2 + j.U 1347 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1348 csBundle(i * len + j).lsrc(2) := vd_old 1349 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1350 csBundle(i * len + j).ldest := vd 1351 csBundle(i * len + j).uopIdx := (i * len + j).U 1352 } 1353 } 1354 switch(vlmulReg) { 1355 is("b001".U ){ 1356 genCsBundle_VEC_RGATHER(2) 1357 } 1358 is("b010".U ){ 1359 genCsBundle_VEC_RGATHER(4) 1360 } 1361 is("b011".U ){ 1362 genCsBundle_VEC_RGATHER(8) 1363 } 1364 } 1365 } 1366 is(UopSplitType.VEC_RGATHER_VX) { 1367 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1368 for (i <- 0 until len) 1369 for (j <- 0 until len) { 1370 csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1371 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1372 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1373 csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1374 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1375 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1376 csBundle(i * len + j + 1).lsrc(2) := vd_old 1377 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1378 csBundle(i * len + j + 1).ldest := vd 1379 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1380 } 1381 } 1382 // i to vector move 1383 csBundle(0).srcType(0) := SrcType.reg 1384 csBundle(0).srcType(1) := SrcType.imm 1385 csBundle(0).lsrc(1) := 0.U 1386 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1387 csBundle(0).fuType := FuType.i2v.U 1388 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1389 csBundle(0).vecWen := true.B 1390 switch(vlmulReg) { 1391 is("b000".U ){ 1392 genCsBundle_RGATHER_VX(1) 1393 } 1394 is("b001".U ){ 1395 genCsBundle_RGATHER_VX(2) 1396 } 1397 is("b010".U ){ 1398 genCsBundle_RGATHER_VX(4) 1399 } 1400 is("b011".U ){ 1401 genCsBundle_RGATHER_VX(8) 1402 } 1403 } 1404 } 1405 is(UopSplitType.VEC_RGATHEREI16) { 1406 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1407 for (i <- 0 until len) 1408 for (j <- 0 until len) { 1409 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1410 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1411 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1412 // csBundle(i * len + j).srcType(1) := SrcType.vp 1413 // csBundle(i * len + j).srcType(2) := SrcType.vp 1414 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1415 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1416 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1417 csBundle((i * len + j)*2+0).ldest := vd0 1418 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1419 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1420 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1421 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1422 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1423 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1424 csBundle((i * len + j)*2+1).ldest := vd1 1425 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1426 } 1427 } 1428 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1429 for (i <- 0 until len) 1430 for (j <- 0 until len) { 1431 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1432 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1433 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1434 // csBundle(i * len + j).srcType(1) := SrcType.vp 1435 // csBundle(i * len + j).srcType(2) := SrcType.vp 1436 csBundle(i * len + j).lsrc(0) := src1 + i.U 1437 csBundle(i * len + j).lsrc(1) := src2 + j.U 1438 csBundle(i * len + j).lsrc(2) := vd_old 1439 csBundle(i * len + j).ldest := vd 1440 csBundle(i * len + j).uopIdx := (i * len + j).U 1441 } 1442 } 1443 switch(vlmulReg) { 1444 is("b000".U ){ 1445 when(!vsewReg.orR){ 1446 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1447 } .otherwise{ 1448 genCsBundle_VEC_RGATHEREI16(1) 1449 } 1450 } 1451 is("b001".U) { 1452 when(!vsewReg.orR) { 1453 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1454 }.otherwise { 1455 genCsBundle_VEC_RGATHEREI16(2) 1456 } 1457 } 1458 is("b010".U) { 1459 when(!vsewReg.orR) { 1460 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1461 }.otherwise { 1462 genCsBundle_VEC_RGATHEREI16(4) 1463 } 1464 } 1465 is("b011".U) { 1466 genCsBundle_VEC_RGATHEREI16(8) 1467 } 1468 } 1469 } 1470 is(UopSplitType.VEC_COMPRESS) { 1471 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1472 for (i <- 0 until len){ 1473 val jlen = if (i == len-1) i+1 else i+2 1474 for (j <- 0 until jlen) { 1475 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1476 val vd = if(i==len-1) (dest + j.U) else{ 1477 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1478 } 1479 val src23Type = if (j == i+1) DontCare else SrcType.vp 1480 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1481 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1482 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1483 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1484 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1485 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1486 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1487 csBundle(i*(i+3)/2 + j).ldest := vd 1488 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1489 } 1490 } 1491 } 1492 switch(vlmulReg) { 1493 is("b001".U ){ 1494 genCsBundle_VEC_COMPRESS(2) 1495 } 1496 is("b010".U ){ 1497 genCsBundle_VEC_COMPRESS(4) 1498 } 1499 is("b011".U ){ 1500 genCsBundle_VEC_COMPRESS(8) 1501 } 1502 } 1503 } 1504 is(UopSplitType.VEC_MVNR) { 1505 for (i <- 0 until MAX_VLMUL) { 1506 csBundle(i).lsrc(0) := src1 + i.U 1507 csBundle(i).lsrc(1) := src2 + i.U 1508 csBundle(i).lsrc(2) := dest + i.U 1509 csBundle(i).ldest := dest + i.U 1510 csBundle(i).uopIdx := i.U 1511 } 1512 } 1513 is(UopSplitType.VEC_US_LDST) { 1514 /* 1515 FMV.D.X 1516 */ 1517 csBundle(0).srcType(0) := SrcType.reg 1518 csBundle(0).srcType(1) := SrcType.imm 1519 csBundle(0).lsrc(1) := 0.U 1520 csBundle(0).ldest := FP_TMP_REG_MV.U 1521 csBundle(0).fuType := FuType.i2f.U 1522 csBundle(0).rfWen := false.B 1523 csBundle(0).fpWen := true.B 1524 csBundle(0).vecWen := false.B 1525 csBundle(0).fpu.isAddSub := false.B 1526 csBundle(0).fpu.typeTagIn := FPU.D 1527 csBundle(0).fpu.typeTagOut := FPU.D 1528 csBundle(0).fpu.fromInt := true.B 1529 csBundle(0).fpu.wflags := false.B 1530 csBundle(0).fpu.fpWen := true.B 1531 csBundle(0).fpu.div := false.B 1532 csBundle(0).fpu.sqrt := false.B 1533 csBundle(0).fpu.fcvt := false.B 1534 //LMUL 1535 for (i <- 0 until MAX_VLMUL) { 1536 csBundle(i + 1).srcType(0) := SrcType.fp 1537 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1538 csBundle(i + 1).ldest := dest + i.U 1539 csBundle(i + 1).uopIdx := i.U 1540 } 1541 } 1542 is(UopSplitType.VEC_S_LDST) { 1543 /* 1544 FMV.D.X 1545 */ 1546 csBundle(0).srcType(0) := SrcType.reg 1547 csBundle(0).srcType(1) := SrcType.imm 1548 csBundle(0).lsrc(1) := 0.U 1549 csBundle(0).ldest := FP_TMP_REG_MV.U 1550 csBundle(0).fuType := FuType.i2f.U 1551 csBundle(0).rfWen := false.B 1552 csBundle(0).fpWen := true.B 1553 csBundle(0).vecWen := false.B 1554 csBundle(0).fpu.isAddSub := false.B 1555 csBundle(0).fpu.typeTagIn := FPU.D 1556 csBundle(0).fpu.typeTagOut := FPU.D 1557 csBundle(0).fpu.fromInt := true.B 1558 csBundle(0).fpu.wflags := false.B 1559 csBundle(0).fpu.fpWen := true.B 1560 csBundle(0).fpu.div := false.B 1561 csBundle(0).fpu.sqrt := false.B 1562 csBundle(0).fpu.fcvt := false.B 1563 1564 csBundle(1).srcType(0) := SrcType.imm 1565 csBundle(1).srcType(1) := SrcType.reg 1566 csBundle(1).lsrc(0) := 0.U 1567 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 1568 csBundle(1).fuType := FuType.i2f.U 1569 csBundle(1).rfWen := false.B 1570 csBundle(1).fpWen := true.B 1571 csBundle(1).vecWen := false.B 1572 csBundle(1).fpu.isAddSub := false.B 1573 csBundle(1).fpu.typeTagIn := FPU.D 1574 csBundle(1).fpu.typeTagOut := FPU.D 1575 csBundle(1).fpu.fromInt := true.B 1576 csBundle(1).fpu.wflags := false.B 1577 csBundle(1).fpu.fpWen := true.B 1578 csBundle(1).fpu.div := false.B 1579 csBundle(1).fpu.sqrt := false.B 1580 csBundle(1).fpu.fcvt := false.B 1581 1582 //LMUL 1583 for (i <- 0 until MAX_VLMUL) { 1584 csBundle(i + 2).srcType(0) := SrcType.fp 1585 csBundle(i + 2).lsrc(0) := FP_TMP_REG_MV.U 1586 csBundle(i + 2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 1587 csBundle(i + 2).ldest := dest + i.U 1588 csBundle(i + 2).uopIdx := i.U 1589 } 1590 } 1591 is(UopSplitType.VEC_I_LDST) { 1592 /* 1593 FMV.D.X 1594 */ 1595 val vlmul = vlmulReg 1596 val vsew = vsewReg 1597 val veew = Cat(0.U(1.W), width) 1598 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 1599 val simple_lmul = MuxLookup(vlmul, 0.U(2.W), Array( 1600 "b001".U -> 1.U, 1601 "b010".U -> 2.U, 1602 "b011".U -> 3.U 1603 )) 1604 val simple_emul = MuxLookup(vemul, 0.U(2.W), Array( 1605 "b001".U -> 1.U, 1606 "b010".U -> 2.U, 1607 "b011".U -> 3.U 1608 )) 1609 csBundle(0).srcType(0) := SrcType.reg 1610 csBundle(0).srcType(1) := SrcType.imm 1611 csBundle(0).lsrc(1) := 0.U 1612 csBundle(0).ldest := FP_TMP_REG_MV.U 1613 csBundle(0).fuType := FuType.i2f.U 1614 csBundle(0).rfWen := false.B 1615 csBundle(0).fpWen := true.B 1616 csBundle(0).vecWen := false.B 1617 csBundle(0).fpu.isAddSub := false.B 1618 csBundle(0).fpu.typeTagIn := FPU.D 1619 csBundle(0).fpu.typeTagOut := FPU.D 1620 csBundle(0).fpu.fromInt := true.B 1621 csBundle(0).fpu.wflags := false.B 1622 csBundle(0).fpu.fpWen := true.B 1623 csBundle(0).fpu.div := false.B 1624 csBundle(0).fpu.sqrt := false.B 1625 csBundle(0).fpu.fcvt := false.B 1626 1627 //LMUL 1628 for (i <- 0 until MAX_INDEXED_LS_UOPNUM) { 1629 indexedLSRegOffset(i).src := Cat(simple_emul, simple_lmul, nf) 1630 val offsetVs2 = indexedLSRegOffset(i).outOffsetVs2 1631 val offsetVd = indexedLSRegOffset(i).outOffsetVd 1632 csBundle(i + 1).srcType(0) := SrcType.fp 1633 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1634 csBundle(i + 1).lsrc(1) := Mux1H(UIntToOH(offsetVs2, MAX_VLMUL), (0 until MAX_VLMUL).map(j => src2 + j.U)) 1635 csBundle(i + 1).ldest := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1636 csBundle(i + 1).uopIdx := i.U 1637 } 1638 } 1639 } 1640 1641 //uops dispatch 1642 val s_normal :: s_ext :: Nil = Enum(2) 1643 val state = RegInit(s_normal) 1644 val state_next = WireDefault(state) 1645 val uopRes = RegInit(0.U) 1646 1647 //readyFromRename Counter 1648 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1649 1650 switch(state) { 1651 is(s_normal) { 1652 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1653 } 1654 is(s_ext) { 1655 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1656 } 1657 } 1658 1659 state := state_next 1660 1661 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1662 val uopResJudge = Mux(state === s_normal, 1663 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1664 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1665 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1666 1667 for(i <- 0 until RenameWidth) { 1668 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1669 (state === s_normal) -> csBundle(i), 1670 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1671 ).toSeq) 1672 } 1673 1674 val validSimple = Wire(Vec(DecodeWidth, Bool())) 1675 validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1676 val notInf = Wire(Vec(DecodeWidth, Bool())) 1677 notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1678 notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1679 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1680 notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1681 1682 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1683 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1684 0.U) 1685 validToRename.zipWithIndex.foreach{ 1686 case(dst, i) => 1687 val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1688 dst := MuxCase(false.B, Seq( 1689 (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1690 (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1691 ).toSeq) 1692 } 1693 1694 readyToIBuf.zipWithIndex.foreach { 1695 case (dst, i) => 1696 val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1697 dst := MuxCase(true.B, Seq( 1698 (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1699 (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1700 ).toSeq) 1701 } 1702 1703 io.deq.decodedInsts := decodedInsts 1704 io.deq.isVset := isVsetSimple 1705 io.deq.complexNum := complexNum 1706 io.deq.validToRename := validToRename 1707 io.deq.readyToIBuf := readyToIBuf 1708 1709} 1710