1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val simple = new Bundle { 46 val decodedInst = Input(new DecodedInst) 47 val isComplex = Input(Bool()) 48 val uopInfo = Input(new UopInfo) 49 } 50 val vtype = Input(new VType) 51 val in0pc = Input(UInt(VAddrBits.W)) 52 val isComplex = Input(Vec(DecodeWidth, Bool())) 53 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 54 val readyFromRename = Input(Vec(RenameWidth, Bool())) 55 val deq = new Bundle { 56 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 57 val isVset = Output(Bool()) 58 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 59 val validToRename = Output(Vec(RenameWidth, Bool())) 60 val complexNum = Output(UInt(3.W)) 61 } 62 val csrCtrl = Input(new CustomCSRCtrlIO) 63} 64 65/** 66 * @author zly 67 */ 68class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 69 val io = IO(new DecodeUnitCompIO) 70 71 val maxUopSize = MaxUopSize 72 //input bits 73 private val inst: XSInstBitFields = io.simple.decodedInst.instr.asTypeOf(new XSInstBitFields) 74 75 val src1 = Cat(0.U(1.W), inst.RS1) 76 val src2 = Cat(0.U(1.W), inst.RS2) 77 val dest = Cat(0.U(1.W), inst.RD) 78 79 80 //output bits 81 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 82 val validToRename = Wire(Vec(RenameWidth, Bool())) 83 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 84 val complexNum = Wire(UInt(3.W)) 85 86 //output of DecodeUnit 87 val decodedInstsSimple = Wire(new DecodedInst) 88 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 89 val lmul = Wire(UInt(4.W)) 90 val isVsetSimple = Wire(Bool()) 91 92 //pre decode 93 decodedInstsSimple := io.simple.decodedInst 94 lmul := io.simple.uopInfo.lmul 95 isVsetSimple := io.simple.decodedInst.isVset 96 val vlmulReg = io.simple.decodedInst.vpu.vlmul 97 val vsewReg = io.simple.decodedInst.vpu.vsew 98 when(isVsetSimple) { 99 when(dest === 0.U && src1 === 0.U) { 100 decodedInstsSimple.fuOpType := VSETOpType.keepVl(io.simple.decodedInst.fuOpType) 101 }.elsewhen(src1 === 0.U) { 102 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(io.simple.decodedInst.fuOpType) 103 } 104 when(io.vtype.illegal){ 105 decodedInstsSimple.flushPipe := true.B 106 } 107 } 108 //Type of uop Div 109 val typeOfSplit = decodedInstsSimple.uopSplitType 110 111 when(typeOfSplit === UopSplitType.DIR) { 112 numOfUop := Mux(dest =/= 0.U, 2.U, 113 Mux(src1 =/= 0.U, 1.U, 114 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 115 } .otherwise { 116 numOfUop := io.simple.uopInfo.numOfUop 117 } 118 119 120 //uop div up to maxUopSize 121 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 122 csBundle.map { case dst => 123 dst := decodedInstsSimple 124 dst.firstUop := false.B 125 dst.lastUop := false.B 126 } 127 128 csBundle(0).numUops := numOfUop 129 csBundle(0).firstUop := true.B 130 csBundle(numOfUop - 1.U).lastUop := true.B 131 132 switch(typeOfSplit) { 133 is(UopSplitType.DIR) { 134 when(isVsetSimple) { 135 when(dest =/= 0.U) { 136 csBundle(0).fuType := FuType.vsetiwi.U 137 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 138 csBundle(0).flushPipe := false.B 139 csBundle(0).rfWen := true.B 140 csBundle(0).vecWen := false.B 141 csBundle(1).ldest := VCONFIG_IDX.U 142 csBundle(1).rfWen := false.B 143 csBundle(1).vecWen := true.B 144 }.elsewhen(src1 =/= 0.U) { 145 csBundle(0).ldest := VCONFIG_IDX.U 146 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 147 csBundle(0).fuType := FuType.vsetfwf.U 148 csBundle(0).srcType(0) := SrcType.vp 149 csBundle(0).lsrc(0) := VCONFIG_IDX.U 150 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 151 csBundle(0).srcType(0) := SrcType.reg 152 csBundle(0).srcType(1) := SrcType.imm 153 csBundle(0).lsrc(1) := 0.U 154 csBundle(0).ldest := FP_TMP_REG_MV.U 155 csBundle(0).fuType := FuType.i2f.U 156 csBundle(0).rfWen := false.B 157 csBundle(0).fpWen := true.B 158 csBundle(0).vecWen := false.B 159 csBundle(0).fpu.isAddSub := false.B 160 csBundle(0).fpu.typeTagIn := FPU.D 161 csBundle(0).fpu.typeTagOut := FPU.D 162 csBundle(0).fpu.fromInt := true.B 163 csBundle(0).fpu.wflags := false.B 164 csBundle(0).fpu.fpWen := true.B 165 csBundle(0).fpu.div := false.B 166 csBundle(0).fpu.sqrt := false.B 167 csBundle(0).fpu.fcvt := false.B 168 csBundle(0).flushPipe := false.B 169 csBundle(1).fuType := FuType.vsetfwf.U 170 csBundle(1).srcType(0) := SrcType.vp 171 csBundle(1).lsrc(0) := VCONFIG_IDX.U 172 csBundle(1).srcType(1) := SrcType.fp 173 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 174 csBundle(1).ldest := VCONFIG_IDX.U 175 } 176 } 177 } 178 is(UopSplitType.VEC_VVV) { 179 for (i <- 0 until MAX_VLMUL) { 180 csBundle(i).lsrc(0) := src1 + i.U 181 csBundle(i).lsrc(1) := src2 + i.U 182 csBundle(i).lsrc(2) := dest + i.U 183 csBundle(i).ldest := dest + i.U 184 csBundle(i).uopIdx := i.U 185 } 186 } 187 is(UopSplitType.VEC_VFV) { 188 for (i <- 0 until MAX_VLMUL) { 189 csBundle(i).lsrc(1) := src2 + i.U 190 csBundle(i).lsrc(2) := dest + i.U 191 csBundle(i).ldest := dest + i.U 192 csBundle(i).uopIdx := i.U 193 } 194 } 195 is(UopSplitType.VEC_EXT2) { 196 for (i <- 0 until MAX_VLMUL / 2) { 197 csBundle(2 * i).lsrc(1) := src2 + i.U 198 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 199 csBundle(2 * i).ldest := dest + (2 * i).U 200 csBundle(2 * i).uopIdx := (2 * i).U 201 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 202 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 203 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 204 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 205 } 206 } 207 is(UopSplitType.VEC_EXT4) { 208 for (i <- 0 until MAX_VLMUL / 4) { 209 csBundle(4 * i).lsrc(1) := src2 + i.U 210 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 211 csBundle(4 * i).ldest := dest + (4 * i).U 212 csBundle(4 * i).uopIdx := (4 * i).U 213 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 214 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 215 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 216 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 217 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 218 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 219 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 220 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 221 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 222 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 223 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 224 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 225 } 226 } 227 is(UopSplitType.VEC_EXT8) { 228 for (i <- 0 until MAX_VLMUL) { 229 csBundle(i).lsrc(1) := src2 230 csBundle(i).lsrc(2) := dest + i.U 231 csBundle(i).ldest := dest + i.U 232 csBundle(i).uopIdx := i.U 233 } 234 } 235 is(UopSplitType.VEC_0XV) { 236 /* 237 FMV.D.X 238 */ 239 csBundle(0).srcType(0) := SrcType.reg 240 csBundle(0).srcType(1) := SrcType.imm 241 csBundle(0).lsrc(1) := 0.U 242 csBundle(0).ldest := FP_TMP_REG_MV.U 243 csBundle(0).fuType := FuType.i2f.U 244 csBundle(0).rfWen := false.B 245 csBundle(0).fpWen := true.B 246 csBundle(0).vecWen := false.B 247 csBundle(0).fpu.isAddSub := false.B 248 csBundle(0).fpu.typeTagIn := FPU.D 249 csBundle(0).fpu.typeTagOut := FPU.D 250 csBundle(0).fpu.fromInt := true.B 251 csBundle(0).fpu.wflags := false.B 252 csBundle(0).fpu.fpWen := true.B 253 csBundle(0).fpu.div := false.B 254 csBundle(0).fpu.sqrt := false.B 255 csBundle(0).fpu.fcvt := false.B 256 /* 257 vfmv.s.f 258 */ 259 csBundle(1).srcType(0) := SrcType.fp 260 csBundle(1).srcType(1) := SrcType.vp 261 csBundle(1).srcType(2) := SrcType.vp 262 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 263 csBundle(1).lsrc(1) := 0.U 264 csBundle(1).lsrc(2) := dest 265 csBundle(1).ldest := dest 266 csBundle(1).fuType := FuType.vppu.U 267 csBundle(1).fuOpType := VpermType.dummy 268 csBundle(1).rfWen := false.B 269 csBundle(1).fpWen := false.B 270 csBundle(1).vecWen := true.B 271 } 272 is(UopSplitType.VEC_VXV) { 273 /* 274 FMV.D.X 275 */ 276 csBundle(0).srcType(0) := SrcType.reg 277 csBundle(0).srcType(1) := SrcType.imm 278 csBundle(0).lsrc(1) := 0.U 279 csBundle(0).ldest := FP_TMP_REG_MV.U 280 csBundle(0).fuType := FuType.i2f.U 281 csBundle(0).rfWen := false.B 282 csBundle(0).fpWen := true.B 283 csBundle(0).vecWen := false.B 284 csBundle(0).fpu.isAddSub := false.B 285 csBundle(0).fpu.typeTagIn := FPU.D 286 csBundle(0).fpu.typeTagOut := FPU.D 287 csBundle(0).fpu.fromInt := true.B 288 csBundle(0).fpu.wflags := false.B 289 csBundle(0).fpu.fpWen := true.B 290 csBundle(0).fpu.div := false.B 291 csBundle(0).fpu.sqrt := false.B 292 csBundle(0).fpu.fcvt := false.B 293 /* 294 LMUL 295 */ 296 for (i <- 0 until MAX_VLMUL) { 297 csBundle(i + 1).srcType(0) := SrcType.fp 298 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 299 csBundle(i + 1).lsrc(1) := src2 + i.U 300 csBundle(i + 1).lsrc(2) := dest + i.U 301 csBundle(i + 1).ldest := dest + i.U 302 csBundle(i + 1).uopIdx := i.U 303 } 304 } 305 is(UopSplitType.VEC_VVW) { 306 for (i <- 0 until MAX_VLMUL / 2) { 307 csBundle(2 * i).lsrc(0) := src1 + i.U 308 csBundle(2 * i).lsrc(1) := src2 + i.U 309 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 310 csBundle(2 * i).ldest := dest + (2 * i).U 311 csBundle(2 * i).uopIdx := (2 * i).U 312 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 313 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 314 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 315 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 316 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 317 } 318 } 319 is(UopSplitType.VEC_VFW) { 320 for (i <- 0 until MAX_VLMUL / 2) { 321 csBundle(2 * i).lsrc(0) := src1 322 csBundle(2 * i).lsrc(1) := src2 + i.U 323 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 324 csBundle(2 * i).ldest := dest + (2 * i).U 325 csBundle(2 * i).uopIdx := (2 * i).U 326 csBundle(2 * i + 1).lsrc(0) := src1 327 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 328 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 329 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 331 } 332 } 333 is(UopSplitType.VEC_WVW) { 334 for (i <- 0 until MAX_VLMUL / 2) { 335 csBundle(2 * i).lsrc(0) := src1 + i.U 336 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 337 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 338 csBundle(2 * i).ldest := dest + (2 * i).U 339 csBundle(2 * i).uopIdx := (2 * i).U 340 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 341 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 342 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 343 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 345 } 346 } 347 is(UopSplitType.VEC_VXW) { 348 /* 349 FMV.D.X 350 */ 351 csBundle(0).srcType(0) := SrcType.reg 352 csBundle(0).srcType(1) := SrcType.imm 353 csBundle(0).lsrc(1) := 0.U 354 csBundle(0).ldest := FP_TMP_REG_MV.U 355 csBundle(0).fuType := FuType.i2f.U 356 csBundle(0).rfWen := false.B 357 csBundle(0).fpWen := true.B 358 csBundle(0).vecWen := false.B 359 csBundle(0).fpu.isAddSub := false.B 360 csBundle(0).fpu.typeTagIn := FPU.D 361 csBundle(0).fpu.typeTagOut := FPU.D 362 csBundle(0).fpu.fromInt := true.B 363 csBundle(0).fpu.wflags := false.B 364 csBundle(0).fpu.fpWen := true.B 365 csBundle(0).fpu.div := false.B 366 csBundle(0).fpu.sqrt := false.B 367 csBundle(0).fpu.fcvt := false.B 368 369 for (i <- 0 until MAX_VLMUL / 2) { 370 csBundle(2 * i + 1).srcType(0) := SrcType.fp 371 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 372 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 373 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 374 csBundle(2 * i + 1).ldest := dest + (2 * i).U 375 csBundle(2 * i + 1).uopIdx := (2 * i).U 376 csBundle(2 * i + 2).srcType(0) := SrcType.fp 377 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 378 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 379 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 380 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 382 } 383 } 384 is(UopSplitType.VEC_WXW) { 385 /* 386 FMV.D.X 387 */ 388 csBundle(0).srcType(0) := SrcType.reg 389 csBundle(0).srcType(1) := SrcType.imm 390 csBundle(0).lsrc(1) := 0.U 391 csBundle(0).ldest := FP_TMP_REG_MV.U 392 csBundle(0).fuType := FuType.i2f.U 393 csBundle(0).rfWen := false.B 394 csBundle(0).fpWen := true.B 395 csBundle(0).vecWen := false.B 396 csBundle(0).fpu.isAddSub := false.B 397 csBundle(0).fpu.typeTagIn := FPU.D 398 csBundle(0).fpu.typeTagOut := FPU.D 399 csBundle(0).fpu.fromInt := true.B 400 csBundle(0).fpu.wflags := false.B 401 csBundle(0).fpu.fpWen := true.B 402 csBundle(0).fpu.div := false.B 403 csBundle(0).fpu.sqrt := false.B 404 csBundle(0).fpu.fcvt := false.B 405 406 for (i <- 0 until MAX_VLMUL / 2) { 407 csBundle(2 * i + 1).srcType(0) := SrcType.fp 408 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 409 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 410 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 411 csBundle(2 * i + 1).ldest := dest + (2 * i).U 412 csBundle(2 * i + 1).uopIdx := (2 * i).U 413 csBundle(2 * i + 2).srcType(0) := SrcType.fp 414 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 415 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 416 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 417 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 419 } 420 } 421 is(UopSplitType.VEC_WVV) { 422 for (i <- 0 until MAX_VLMUL / 2) { 423 424 csBundle(2 * i).lsrc(0) := src1 + i.U 425 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 426 csBundle(2 * i).lsrc(2) := dest + i.U 427 csBundle(2 * i).ldest := dest + i.U 428 csBundle(2 * i).uopIdx := (2 * i).U 429 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 430 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 431 csBundle(2 * i + 1).lsrc(2) := dest + i.U 432 csBundle(2 * i + 1).ldest := dest + i.U 433 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 434 } 435 } 436 is(UopSplitType.VEC_WFW) { 437 for (i <- 0 until MAX_VLMUL / 2) { 438 csBundle(2 * i).lsrc(0) := src1 439 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 440 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 441 csBundle(2 * i).ldest := dest + (2 * i).U 442 csBundle(2 * i).uopIdx := (2 * i).U 443 csBundle(2 * i + 1).lsrc(0) := src1 444 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 445 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 446 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 447 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 448 } 449 } 450 is(UopSplitType.VEC_WXV) { 451 /* 452 FMV.D.X 453 */ 454 csBundle(0).srcType(0) := SrcType.reg 455 csBundle(0).srcType(1) := SrcType.imm 456 csBundle(0).lsrc(1) := 0.U 457 csBundle(0).ldest := FP_TMP_REG_MV.U 458 csBundle(0).fuType := FuType.i2f.U 459 csBundle(0).rfWen := false.B 460 csBundle(0).fpWen := true.B 461 csBundle(0).vecWen := false.B 462 csBundle(0).fpu.isAddSub := false.B 463 csBundle(0).fpu.typeTagIn := FPU.D 464 csBundle(0).fpu.typeTagOut := FPU.D 465 csBundle(0).fpu.fromInt := true.B 466 csBundle(0).fpu.wflags := false.B 467 csBundle(0).fpu.fpWen := true.B 468 csBundle(0).fpu.div := false.B 469 csBundle(0).fpu.sqrt := false.B 470 csBundle(0).fpu.fcvt := false.B 471 472 for (i <- 0 until MAX_VLMUL / 2) { 473 csBundle(2 * i + 1).srcType(0) := SrcType.fp 474 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 475 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 476 csBundle(2 * i + 1).lsrc(2) := dest + i.U 477 csBundle(2 * i + 1).ldest := dest + i.U 478 csBundle(2 * i + 1).uopIdx := (2 * i).U 479 csBundle(2 * i + 2).srcType(0) := SrcType.fp 480 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 481 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 482 csBundle(2 * i + 2).lsrc(2) := dest + i.U 483 csBundle(2 * i + 2).ldest := dest + i.U 484 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 485 } 486 } 487 is(UopSplitType.VEC_VVM) { 488 csBundle(0).lsrc(2) := dest 489 csBundle(0).ldest := dest 490 csBundle(0).uopIdx := 0.U 491 for (i <- 1 until MAX_VLMUL) { 492 csBundle(i).lsrc(0) := src1 + i.U 493 csBundle(i).lsrc(1) := src2 + i.U 494 csBundle(i).lsrc(2) := dest 495 csBundle(i).ldest := dest 496 csBundle(i).uopIdx := i.U 497 } 498 csBundle(numOfUop - 1.U).ldest := dest 499 } 500 is(UopSplitType.VEC_VFM) { 501 csBundle(0).lsrc(2) := dest 502 csBundle(0).ldest := dest 503 csBundle(0).uopIdx := 0.U 504 for (i <- 1 until MAX_VLMUL) { 505 csBundle(i).lsrc(0) := src1 506 csBundle(i).lsrc(1) := src2 + i.U 507 csBundle(i).lsrc(2) := dest 508 csBundle(i).ldest := dest 509 csBundle(i).uopIdx := i.U 510 } 511 csBundle(numOfUop - 1.U).ldest := dest 512 } 513 is(UopSplitType.VEC_VXM) { 514 /* 515 FMV.D.X 516 */ 517 csBundle(0).srcType(0) := SrcType.reg 518 csBundle(0).srcType(1) := SrcType.imm 519 csBundle(0).lsrc(1) := 0.U 520 csBundle(0).ldest := FP_TMP_REG_MV.U 521 csBundle(0).fuType := FuType.i2f.U 522 csBundle(0).rfWen := false.B 523 csBundle(0).fpWen := true.B 524 csBundle(0).vecWen := false.B 525 csBundle(0).fpu.isAddSub := false.B 526 csBundle(0).fpu.typeTagIn := FPU.D 527 csBundle(0).fpu.typeTagOut := FPU.D 528 csBundle(0).fpu.fromInt := true.B 529 csBundle(0).fpu.wflags := false.B 530 csBundle(0).fpu.fpWen := true.B 531 csBundle(0).fpu.div := false.B 532 csBundle(0).fpu.sqrt := false.B 533 csBundle(0).fpu.fcvt := false.B 534 //LMUL 535 csBundle(1).srcType(0) := SrcType.fp 536 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 537 csBundle(1).lsrc(2) := dest 538 csBundle(1).ldest := dest 539 csBundle(1).uopIdx := 0.U 540 for (i <- 1 until MAX_VLMUL) { 541 csBundle(i + 1).srcType(0) := SrcType.fp 542 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 543 csBundle(i + 1).lsrc(1) := src2 + i.U 544 csBundle(i + 1).lsrc(2) := dest 545 csBundle(i + 1).ldest := dest 546 csBundle(i + 1).uopIdx := i.U 547 } 548 csBundle(numOfUop - 1.U).ldest := dest 549 } 550 is(UopSplitType.VEC_SLIDE1UP) { 551 /* 552 FMV.D.X 553 */ 554 csBundle(0).srcType(0) := SrcType.reg 555 csBundle(0).srcType(1) := SrcType.imm 556 csBundle(0).lsrc(1) := 0.U 557 csBundle(0).ldest := FP_TMP_REG_MV.U 558 csBundle(0).fuType := FuType.i2f.U 559 csBundle(0).rfWen := false.B 560 csBundle(0).fpWen := true.B 561 csBundle(0).vecWen := false.B 562 csBundle(0).fpu.isAddSub := false.B 563 csBundle(0).fpu.typeTagIn := FPU.D 564 csBundle(0).fpu.typeTagOut := FPU.D 565 csBundle(0).fpu.fromInt := true.B 566 csBundle(0).fpu.wflags := false.B 567 csBundle(0).fpu.fpWen := true.B 568 csBundle(0).fpu.div := false.B 569 csBundle(0).fpu.sqrt := false.B 570 csBundle(0).fpu.fcvt := false.B 571 //LMUL 572 csBundle(1).srcType(0) := SrcType.fp 573 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 574 csBundle(1).lsrc(2) := dest 575 csBundle(1).ldest := dest 576 csBundle(1).uopIdx := 0.U 577 for (i <- 1 until MAX_VLMUL) { 578 csBundle(i + 1).srcType(0) := SrcType.vp 579 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 580 csBundle(i + 1).lsrc(1) := src2 + i.U 581 csBundle(i + 1).lsrc(2) := dest + i.U 582 csBundle(i + 1).ldest := dest + i.U 583 csBundle(i + 1).uopIdx := i.U 584 } 585 } 586 is(UopSplitType.VEC_FSLIDE1UP) { 587 //LMUL 588 csBundle(0).srcType(0) := SrcType.fp 589 csBundle(0).lsrc(0) := src1 590 csBundle(0).lsrc(1) := src2 591 csBundle(0).lsrc(2) := dest 592 csBundle(0).ldest := dest 593 csBundle(0).uopIdx := 0.U 594 for (i <- 1 until MAX_VLMUL) { 595 csBundle(i).srcType(0) := SrcType.vp 596 csBundle(i).lsrc(0) := src2 + (i - 1).U 597 csBundle(i).lsrc(1) := src2 + i.U 598 csBundle(i).lsrc(2) := dest + i.U 599 csBundle(i).ldest := dest + i.U 600 csBundle(i).uopIdx := i.U 601 } 602 } 603 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 604 /* 605 FMV.D.X 606 */ 607 csBundle(0).srcType(0) := SrcType.reg 608 csBundle(0).srcType(1) := SrcType.imm 609 csBundle(0).lsrc(1) := 0.U 610 csBundle(0).ldest := FP_TMP_REG_MV.U 611 csBundle(0).fuType := FuType.i2f.U 612 csBundle(0).rfWen := false.B 613 csBundle(0).fpWen := true.B 614 csBundle(0).vecWen := false.B 615 csBundle(0).fpu.isAddSub := false.B 616 csBundle(0).fpu.typeTagIn := FPU.D 617 csBundle(0).fpu.typeTagOut := FPU.D 618 csBundle(0).fpu.fromInt := true.B 619 csBundle(0).fpu.wflags := false.B 620 csBundle(0).fpu.fpWen := true.B 621 csBundle(0).fpu.div := false.B 622 csBundle(0).fpu.sqrt := false.B 623 csBundle(0).fpu.fcvt := false.B 624 //LMUL 625 for (i <- 0 until MAX_VLMUL) { 626 csBundle(2 * i + 1).srcType(0) := SrcType.vp 627 csBundle(2 * i + 1).srcType(1) := SrcType.vp 628 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 629 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 630 csBundle(2 * i + 1).lsrc(2) := dest + i.U 631 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 632 csBundle(2 * i + 1).uopIdx := (2 * i).U 633 if (2 * i + 2 < MAX_VLMUL * 2) { 634 csBundle(2 * i + 2).srcType(0) := SrcType.fp 635 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 636 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 637 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 638 csBundle(2 * i + 2).ldest := dest + i.U 639 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 640 } 641 } 642 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 643 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 644 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 645 } 646 is(UopSplitType.VEC_FSLIDE1DOWN) { 647 //LMUL 648 for (i <- 0 until MAX_VLMUL) { 649 csBundle(2 * i).srcType(0) := SrcType.vp 650 csBundle(2 * i).srcType(1) := SrcType.vp 651 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 652 csBundle(2 * i).lsrc(1) := src2 + i.U 653 csBundle(2 * i).lsrc(2) := dest + i.U 654 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 655 csBundle(2 * i).uopIdx := (2 * i).U 656 csBundle(2 * i + 1).srcType(0) := SrcType.fp 657 csBundle(2 * i + 1).lsrc(0) := src1 658 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 659 csBundle(2 * i + 1).ldest := dest + i.U 660 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 661 } 662 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 663 csBundle(numOfUop - 1.U).lsrc(0) := src1 664 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 665 } 666 is(UopSplitType.VEC_VRED) { 667 when(vlmulReg === "b001".U) { 668 csBundle(0).srcType(2) := SrcType.DC 669 csBundle(0).lsrc(0) := src2 + 1.U 670 csBundle(0).lsrc(1) := src2 671 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 672 csBundle(0).uopIdx := 0.U 673 } 674 when(vlmulReg === "b010".U) { 675 csBundle(0).srcType(2) := SrcType.DC 676 csBundle(0).lsrc(0) := src2 + 1.U 677 csBundle(0).lsrc(1) := src2 678 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 679 csBundle(0).uopIdx := 0.U 680 681 csBundle(1).srcType(2) := SrcType.DC 682 csBundle(1).lsrc(0) := src2 + 3.U 683 csBundle(1).lsrc(1) := src2 + 2.U 684 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 685 csBundle(1).uopIdx := 1.U 686 687 csBundle(2).srcType(2) := SrcType.DC 688 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 689 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 690 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 691 csBundle(2).uopIdx := 2.U 692 } 693 when(vlmulReg === "b011".U) { 694 for (i <- 0 until MAX_VLMUL) { 695 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 696 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 697 csBundle(i).lsrc(1) := src2 + (i * 2).U 698 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 699 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 700 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 701 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 702 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 703 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 704 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 705 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 706 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 707 } 708 csBundle(i).srcType(2) := SrcType.DC 709 csBundle(i).uopIdx := i.U 710 } 711 } 712 when(vlmulReg.orR) { 713 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 714 csBundle(numOfUop - 1.U).lsrc(0) := src1 715 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 716 csBundle(numOfUop - 1.U).lsrc(2) := dest 717 csBundle(numOfUop - 1.U).ldest := dest 718 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 719 } 720 } 721 is(UopSplitType.VEC_VFRED) { 722 val vlmul = vlmulReg 723 val vsew = vsewReg 724 when(vlmul === VLmul.m8){ 725 for (i <- 0 until 4) { 726 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 727 csBundle(i).lsrc(1) := src2 + (i * 2).U 728 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 729 csBundle(i).uopIdx := i.U 730 } 731 for (i <- 4 until 6) { 732 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 733 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 734 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 735 csBundle(i).uopIdx := i.U 736 } 737 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 738 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 739 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 740 csBundle(6).uopIdx := 6.U 741 when(vsew === VSew.e64) { 742 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 743 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 744 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 745 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 746 csBundle(7).uopIdx := 7.U 747 csBundle(8).lsrc(0) := src1 748 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 749 csBundle(8).ldest := dest 750 csBundle(8).uopIdx := 8.U 751 } 752 when(vsew === VSew.e32) { 753 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 754 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 755 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 756 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 757 csBundle(7).uopIdx := 7.U 758 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 759 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 760 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 761 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 762 csBundle(8).uopIdx := 8.U 763 csBundle(9).lsrc(0) := src1 764 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 765 csBundle(9).ldest := dest 766 csBundle(9).uopIdx := 9.U 767 } 768 when(vsew === VSew.e16) { 769 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 770 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 771 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 772 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 773 csBundle(7).uopIdx := 7.U 774 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 775 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 776 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 777 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 778 csBundle(8).uopIdx := 8.U 779 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 780 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 781 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 782 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 783 csBundle(9).uopIdx := 9.U 784 csBundle(10).lsrc(0) := src1 785 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 786 csBundle(10).ldest := dest 787 csBundle(10).uopIdx := 10.U 788 } 789 } 790 when(vlmul === VLmul.m4) { 791 for (i <- 0 until 2) { 792 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 793 csBundle(i).lsrc(1) := src2 + (i * 2).U 794 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 795 csBundle(i).uopIdx := i.U 796 } 797 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 798 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 799 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 800 csBundle(2).uopIdx := 2.U 801 when(vsew === VSew.e64) { 802 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 803 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 804 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 805 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 806 csBundle(3).uopIdx := 3.U 807 csBundle(4).lsrc(0) := src1 808 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 809 csBundle(4).ldest := dest 810 csBundle(4).uopIdx := 4.U 811 } 812 when(vsew === VSew.e32) { 813 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 814 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 815 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 816 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 817 csBundle(3).uopIdx := 3.U 818 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 819 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 820 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 821 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 822 csBundle(4).uopIdx := 4.U 823 csBundle(5).lsrc(0) := src1 824 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 825 csBundle(5).ldest := dest 826 csBundle(5).uopIdx := 5.U 827 } 828 when(vsew === VSew.e16) { 829 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 830 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 831 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 832 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 833 csBundle(3).uopIdx := 3.U 834 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 835 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 836 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 837 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 838 csBundle(4).uopIdx := 4.U 839 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 840 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 841 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 842 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 843 csBundle(5).uopIdx := 5.U 844 csBundle(6).lsrc(0) := src1 845 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 846 csBundle(6).ldest := dest 847 csBundle(6).uopIdx := 6.U 848 } 849 } 850 when(vlmul === VLmul.m2) { 851 csBundle(0).lsrc(0) := src2 + 1.U 852 csBundle(0).lsrc(1) := src2 + 0.U 853 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 854 csBundle(0).uopIdx := 0.U 855 when(vsew === VSew.e64) { 856 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 857 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 858 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 859 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 860 csBundle(1).uopIdx := 1.U 861 csBundle(2).lsrc(0) := src1 862 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 863 csBundle(2).ldest := dest 864 csBundle(2).uopIdx := 2.U 865 } 866 when(vsew === VSew.e32) { 867 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 868 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 869 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 870 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 871 csBundle(1).uopIdx := 1.U 872 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 873 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 874 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 875 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 876 csBundle(2).uopIdx := 2.U 877 csBundle(3).lsrc(0) := src1 878 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 879 csBundle(3).ldest := dest 880 csBundle(3).uopIdx := 3.U 881 } 882 when(vsew === VSew.e16) { 883 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 884 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 885 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 886 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 887 csBundle(1).uopIdx := 1.U 888 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 889 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 890 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 891 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 892 csBundle(2).uopIdx := 2.U 893 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 894 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 895 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 896 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 897 csBundle(3).uopIdx := 3.U 898 csBundle(4).lsrc(0) := src1 899 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 900 csBundle(4).ldest := dest 901 csBundle(4).uopIdx := 4.U 902 } 903 } 904 when(vlmul === VLmul.m1) { 905 when(vsew === VSew.e64) { 906 csBundle(0).lsrc(0) := src2 907 csBundle(0).lsrc(1) := src2 908 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 909 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 910 csBundle(0).uopIdx := 0.U 911 csBundle(1).lsrc(0) := src1 912 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 913 csBundle(1).ldest := dest 914 csBundle(1).uopIdx := 1.U 915 } 916 when(vsew === VSew.e32) { 917 csBundle(0).lsrc(0) := src2 918 csBundle(0).lsrc(1) := src2 919 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 920 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 921 csBundle(0).uopIdx := 0.U 922 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 923 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 924 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 925 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 926 csBundle(1).uopIdx := 1.U 927 csBundle(2).lsrc(0) := src1 928 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 929 csBundle(2).ldest := dest 930 csBundle(2).uopIdx := 2.U 931 } 932 when(vsew === VSew.e16) { 933 csBundle(0).lsrc(0) := src2 934 csBundle(0).lsrc(1) := src2 935 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 936 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 937 csBundle(0).uopIdx := 0.U 938 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 939 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 940 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 941 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 942 csBundle(1).uopIdx := 1.U 943 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 944 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 945 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 946 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 947 csBundle(2).uopIdx := 2.U 948 csBundle(3).lsrc(0) := src1 949 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 950 csBundle(3).ldest := dest 951 csBundle(3).uopIdx := 3.U 952 } 953 } 954 when(vlmul === VLmul.mf2) { 955 when(vsew === VSew.e32) { 956 csBundle(0).lsrc(0) := src2 957 csBundle(0).lsrc(1) := src2 958 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 959 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 960 csBundle(0).uopIdx := 0.U 961 csBundle(1).lsrc(0) := src1 962 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 963 csBundle(1).ldest := dest 964 csBundle(1).uopIdx := 1.U 965 } 966 when(vsew === VSew.e16) { 967 csBundle(0).lsrc(0) := src2 968 csBundle(0).lsrc(1) := src2 969 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 970 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 971 csBundle(0).uopIdx := 0.U 972 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 973 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 974 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 975 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 976 csBundle(1).uopIdx := 1.U 977 csBundle(2).lsrc(0) := src1 978 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 979 csBundle(2).ldest := dest 980 csBundle(2).uopIdx := 2.U 981 } 982 } 983 when(vlmul === VLmul.mf4) { 984 when(vsew === VSew.e16) { 985 csBundle(0).lsrc(0) := src2 986 csBundle(0).lsrc(1) := src2 987 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 988 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 989 csBundle(0).uopIdx := 0.U 990 csBundle(1).lsrc(0) := src1 991 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 992 csBundle(1).ldest := dest 993 csBundle(1).uopIdx := 1.U 994 } 995 } 996 } 997 998 is(UopSplitType.VEC_VFREDOSUM) { 999 import yunsuan.VfaluType 1000 val vlmul = vlmulReg 1001 val vsew = vsewReg 1002 val isWiden = decodedInstsSimple.fuOpType === VfaluType.vfwredosum 1003 when(vlmul === VLmul.m8) { 1004 when(vsew === VSew.e64) { 1005 val vlmax = 16 1006 for (i <- 0 until vlmax) { 1007 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1008 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1009 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1010 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1011 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1012 csBundle(i).uopIdx := i.U 1013 } 1014 } 1015 when(vsew === VSew.e32) { 1016 val vlmax = 32 1017 for (i <- 0 until vlmax) { 1018 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1019 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1020 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1021 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1022 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1023 csBundle(i).uopIdx := i.U 1024 } 1025 } 1026 when(vsew === VSew.e16) { 1027 val vlmax = 64 1028 for (i <- 0 until vlmax) { 1029 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1030 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1031 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1032 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1033 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1034 csBundle(i).uopIdx := i.U 1035 } 1036 } 1037 } 1038 when(vlmul === VLmul.m4) { 1039 when(vsew === VSew.e64) { 1040 val vlmax = 8 1041 for (i <- 0 until vlmax) { 1042 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1043 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1044 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1045 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1046 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1047 csBundle(i).uopIdx := i.U 1048 } 1049 } 1050 when(vsew === VSew.e32) { 1051 val vlmax = 16 1052 for (i <- 0 until vlmax) { 1053 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1054 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1055 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1056 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1057 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1058 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1059 csBundle(i).uopIdx := i.U 1060 } 1061 } 1062 when(vsew === VSew.e16) { 1063 val vlmax = 32 1064 for (i <- 0 until vlmax) { 1065 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1066 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1067 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1068 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1069 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1070 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1071 csBundle(i).uopIdx := i.U 1072 } 1073 } 1074 } 1075 when(vlmul === VLmul.m2) { 1076 when(vsew === VSew.e64) { 1077 val vlmax = 4 1078 for (i <- 0 until vlmax) { 1079 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1080 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1081 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1082 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1083 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1084 csBundle(i).uopIdx := i.U 1085 } 1086 } 1087 when(vsew === VSew.e32) { 1088 val vlmax = 8 1089 for (i <- 0 until vlmax) { 1090 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1091 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1092 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1093 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1094 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1095 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1096 csBundle(i).uopIdx := i.U 1097 } 1098 } 1099 when(vsew === VSew.e16) { 1100 val vlmax = 16 1101 for (i <- 0 until vlmax) { 1102 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1103 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1104 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1105 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1106 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1107 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1108 csBundle(i).uopIdx := i.U 1109 } 1110 } 1111 } 1112 when(vlmul === VLmul.m1) { 1113 when(vsew === VSew.e64) { 1114 val vlmax = 2 1115 for (i <- 0 until vlmax) { 1116 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1117 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1118 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1119 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1120 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1121 csBundle(i).uopIdx := i.U 1122 } 1123 } 1124 when(vsew === VSew.e32) { 1125 val vlmax = 4 1126 for (i <- 0 until vlmax) { 1127 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1128 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1129 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1130 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1131 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1132 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1133 csBundle(i).uopIdx := i.U 1134 } 1135 } 1136 when(vsew === VSew.e16) { 1137 val vlmax = 8 1138 for (i <- 0 until vlmax) { 1139 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1140 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1141 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1142 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1143 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1144 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1145 csBundle(i).uopIdx := i.U 1146 } 1147 } 1148 } 1149 when(vlmul === VLmul.mf2) { 1150 when(vsew === VSew.e32) { 1151 val vlmax = 2 1152 for (i <- 0 until vlmax) { 1153 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1154 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1155 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1156 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1157 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1158 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1159 csBundle(i).uopIdx := i.U 1160 } 1161 } 1162 when(vsew === VSew.e16) { 1163 val vlmax = 4 1164 for (i <- 0 until vlmax) { 1165 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1166 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1167 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1168 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1169 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1170 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1171 csBundle(i).uopIdx := i.U 1172 } 1173 } 1174 } 1175 when(vlmul === VLmul.mf4) { 1176 when(vsew === VSew.e16) { 1177 val vlmax = 2 1178 for (i <- 0 until vlmax) { 1179 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1180 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1181 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1182 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1183 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1184 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1185 csBundle(i).uopIdx := i.U 1186 } 1187 } 1188 } 1189 } 1190 is(UopSplitType.VEC_SLIDEUP) { 1191 // FMV.D.X 1192 csBundle(0).srcType(0) := SrcType.reg 1193 csBundle(0).srcType(1) := SrcType.imm 1194 csBundle(0).lsrc(1) := 0.U 1195 csBundle(0).ldest := FP_TMP_REG_MV.U 1196 csBundle(0).fuType := FuType.i2f.U 1197 csBundle(0).rfWen := false.B 1198 csBundle(0).fpWen := true.B 1199 csBundle(0).vecWen := false.B 1200 csBundle(0).fpu.isAddSub := false.B 1201 csBundle(0).fpu.typeTagIn := FPU.D 1202 csBundle(0).fpu.typeTagOut := FPU.D 1203 csBundle(0).fpu.fromInt := true.B 1204 csBundle(0).fpu.wflags := false.B 1205 csBundle(0).fpu.fpWen := true.B 1206 csBundle(0).fpu.div := false.B 1207 csBundle(0).fpu.sqrt := false.B 1208 csBundle(0).fpu.fcvt := false.B 1209 // LMUL 1210 for (i <- 0 until MAX_VLMUL) 1211 for (j <- 0 to i) { 1212 val old_vd = if (j == 0) { 1213 dest + i.U 1214 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1215 val vd = if (j == i) { 1216 dest + i.U 1217 } else (VECTOR_TMP_REG_LMUL + j).U 1218 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 1219 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 1220 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1221 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1222 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1223 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1224 } 1225 } 1226 1227 is(UopSplitType.VEC_ISLIDEUP) { 1228 // LMUL 1229 for (i <- 0 until MAX_VLMUL) 1230 for (j <- 0 to i) { 1231 val old_vd = if (j == 0) { 1232 dest + i.U 1233 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1234 val vd = if (j == i) { 1235 dest + i.U 1236 } else (VECTOR_TMP_REG_LMUL + j).U 1237 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 1238 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 1239 csBundle(i * (i + 1) / 2 + j).ldest := vd 1240 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 1241 } 1242 } 1243 1244 is(UopSplitType.VEC_SLIDEDOWN) { 1245 // FMV.D.X 1246 csBundle(0).srcType(0) := SrcType.reg 1247 csBundle(0).srcType(1) := SrcType.imm 1248 csBundle(0).lsrc(1) := 0.U 1249 csBundle(0).ldest := FP_TMP_REG_MV.U 1250 csBundle(0).fuType := FuType.i2f.U 1251 csBundle(0).rfWen := false.B 1252 csBundle(0).fpWen := true.B 1253 csBundle(0).vecWen := false.B 1254 csBundle(0).fpu.isAddSub := false.B 1255 csBundle(0).fpu.typeTagIn := FPU.D 1256 csBundle(0).fpu.typeTagOut := FPU.D 1257 csBundle(0).fpu.fromInt := true.B 1258 csBundle(0).fpu.wflags := false.B 1259 csBundle(0).fpu.fpWen := true.B 1260 csBundle(0).fpu.div := false.B 1261 csBundle(0).fpu.sqrt := false.B 1262 csBundle(0).fpu.fcvt := false.B 1263 // LMUL 1264 for (i <- 0 until MAX_VLMUL) 1265 for (j <- (0 to i).reverse) { 1266 when(i.U < lmul) { 1267 val old_vd = if (j == 0) { 1268 dest + lmul - 1.U - i.U 1269 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1270 val vd = if (j == i) { 1271 dest + lmul - 1.U - i.U 1272 } else (VECTOR_TMP_REG_LMUL + j).U 1273 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 1274 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 1275 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1276 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1277 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1278 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1279 } 1280 } 1281 } 1282 1283 is(UopSplitType.VEC_ISLIDEDOWN) { 1284 // LMUL 1285 for (i <- 0 until MAX_VLMUL) 1286 for (j <- (0 to i).reverse) { 1287 when(i.U < lmul) { 1288 val old_vd = if (j == 0) { 1289 dest + lmul - 1.U - i.U 1290 } else (VECTOR_TMP_REG_LMUL + j - 1).U 1291 val vd = if (j == i) { 1292 dest + lmul - 1.U - i.U 1293 } else (VECTOR_TMP_REG_LMUL + j).U 1294 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1295 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1296 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1297 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 1298 } 1299 } 1300 } 1301 1302 is(UopSplitType.VEC_M0X) { 1303 // LMUL 1304 for (i <- 0 until MAX_VLMUL) { 1305 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1306 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1307 csBundle(i).srcType(0) := srcType0 1308 csBundle(i).srcType(1) := SrcType.vp 1309 csBundle(i).rfWen := false.B 1310 csBundle(i).vecWen := true.B 1311 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1312 csBundle(i).lsrc(1) := src2 1313 // csBundle(i).lsrc(2) := dest + i.U DontCare 1314 csBundle(i).ldest := ldest 1315 csBundle(i).uopIdx := i.U 1316 } 1317 csBundle(lmul - 1.U).vecWen := false.B 1318 csBundle(lmul - 1.U).fpWen := true.B 1319 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 1320 // FMV_X_D 1321 csBundle(lmul).srcType(0) := SrcType.fp 1322 csBundle(lmul).srcType(1) := SrcType.imm 1323 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 1324 csBundle(lmul).lsrc(1) := 0.U 1325 csBundle(lmul).ldest := dest 1326 csBundle(lmul).fuType := FuType.fmisc.U 1327 csBundle(lmul).rfWen := true.B 1328 csBundle(lmul).fpWen := false.B 1329 csBundle(lmul).vecWen := false.B 1330 csBundle(lmul).fpu.isAddSub := false.B 1331 csBundle(lmul).fpu.typeTagIn := FPU.D 1332 csBundle(lmul).fpu.typeTagOut := FPU.D 1333 csBundle(lmul).fpu.fromInt := false.B 1334 csBundle(lmul).fpu.wflags := false.B 1335 csBundle(lmul).fpu.fpWen := false.B 1336 csBundle(lmul).fpu.div := false.B 1337 csBundle(lmul).fpu.sqrt := false.B 1338 csBundle(lmul).fpu.fcvt := false.B 1339 } 1340 1341 is(UopSplitType.VEC_MVV) { 1342 // LMUL 1343 for (i <- 0 until MAX_VLMUL) { 1344 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1345 csBundle(i * 2 + 0).srcType(0) := srcType0 1346 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1347 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1348 csBundle(i * 2 + 0).lsrc(1) := src2 1349 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1350 csBundle(i * 2 + 0).ldest := dest + i.U 1351 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1352 1353 csBundle(i * 2 + 1).srcType(0) := srcType0 1354 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1355 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1356 csBundle(i * 2 + 1).lsrc(1) := src2 1357 // csBundle(i).lsrc(2) := dest + i.U DontCare 1358 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1359 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1360 } 1361 } 1362 1363 is(UopSplitType.VEC_M0X_VFIRST) { 1364 // LMUL 1365 csBundle(0).rfWen := false.B 1366 csBundle(0).fpWen := true.B 1367 csBundle(0).ldest := FP_TMP_REG_MV.U 1368 // FMV_X_D 1369 csBundle(1).srcType(0) := SrcType.fp 1370 csBundle(1).srcType(1) := SrcType.imm 1371 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 1372 csBundle(1).lsrc(1) := 0.U 1373 csBundle(1).ldest := dest 1374 csBundle(1).fuType := FuType.fmisc.U 1375 csBundle(1).rfWen := true.B 1376 csBundle(1).fpWen := false.B 1377 csBundle(1).vecWen := false.B 1378 csBundle(1).fpu.isAddSub := false.B 1379 csBundle(1).fpu.typeTagIn := FPU.D 1380 csBundle(1).fpu.typeTagOut := FPU.D 1381 csBundle(1).fpu.fromInt := false.B 1382 csBundle(1).fpu.wflags := false.B 1383 csBundle(1).fpu.fpWen := false.B 1384 csBundle(1).fpu.div := false.B 1385 csBundle(1).fpu.sqrt := false.B 1386 csBundle(1).fpu.fcvt := false.B 1387 } 1388 is(UopSplitType.VEC_VWW) { 1389 for (i <- 0 until MAX_VLMUL*2) { 1390 when(i.U < lmul){ 1391 csBundle(i).srcType(2) := SrcType.DC 1392 csBundle(i).lsrc(0) := src2 + i.U 1393 csBundle(i).lsrc(1) := src2 + i.U 1394 // csBundle(i).lsrc(2) := dest + (2 * i).U 1395 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1396 csBundle(i).uopIdx := i.U 1397 } otherwise { 1398 csBundle(i).srcType(2) := SrcType.DC 1399 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1400 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1401 // csBundle(i).lsrc(2) := dest + (2 * i).U 1402 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1403 csBundle(i).uopIdx := i.U 1404 } 1405 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1406 csBundle(numOfUop-1.U).lsrc(0) := src1 1407 csBundle(numOfUop-1.U).lsrc(2) := dest 1408 csBundle(numOfUop-1.U).ldest := dest 1409 } 1410 } 1411 is(UopSplitType.VEC_RGATHER) { 1412 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1413 for (i <- 0 until len) 1414 for (j <- 0 until len) { 1415 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1416 // csBundle(i * len + j).srcType(1) := SrcType.vp 1417 // csBundle(i * len + j).srcType(2) := SrcType.vp 1418 csBundle(i * len + j).lsrc(0) := src1 + i.U 1419 csBundle(i * len + j).lsrc(1) := src2 + j.U 1420 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1421 csBundle(i * len + j).lsrc(2) := vd_old 1422 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1423 csBundle(i * len + j).ldest := vd 1424 csBundle(i * len + j).uopIdx := (i * len + j).U 1425 } 1426 } 1427 switch(vlmulReg) { 1428 is("b001".U ){ 1429 genCsBundle_VEC_RGATHER(2) 1430 } 1431 is("b010".U ){ 1432 genCsBundle_VEC_RGATHER(4) 1433 } 1434 is("b011".U ){ 1435 genCsBundle_VEC_RGATHER(8) 1436 } 1437 } 1438 } 1439 is(UopSplitType.VEC_RGATHER_VX) { 1440 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1441 for (i <- 0 until len) 1442 for (j <- 0 until len) { 1443 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 1444 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1445 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1446 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 1447 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1448 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1449 csBundle(i * len + j + 1).lsrc(2) := vd_old 1450 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1451 csBundle(i * len + j + 1).ldest := vd 1452 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1453 } 1454 } 1455 // FMV.D.X 1456 csBundle(0).srcType(0) := SrcType.reg 1457 csBundle(0).srcType(1) := SrcType.imm 1458 csBundle(0).lsrc(1) := 0.U 1459 csBundle(0).ldest := FP_TMP_REG_MV.U 1460 csBundle(0).fuType := FuType.i2f.U 1461 csBundle(0).rfWen := false.B 1462 csBundle(0).fpWen := true.B 1463 csBundle(0).vecWen := false.B 1464 csBundle(0).fpu.isAddSub := false.B 1465 csBundle(0).fpu.typeTagIn := FPU.D 1466 csBundle(0).fpu.typeTagOut := FPU.D 1467 csBundle(0).fpu.fromInt := true.B 1468 csBundle(0).fpu.wflags := false.B 1469 csBundle(0).fpu.fpWen := true.B 1470 csBundle(0).fpu.div := false.B 1471 csBundle(0).fpu.sqrt := false.B 1472 csBundle(0).fpu.fcvt := false.B 1473 switch(vlmulReg) { 1474 is("b000".U ){ 1475 genCsBundle_RGATHER_VX(1) 1476 } 1477 is("b001".U ){ 1478 genCsBundle_RGATHER_VX(2) 1479 } 1480 is("b010".U ){ 1481 genCsBundle_RGATHER_VX(4) 1482 } 1483 is("b011".U ){ 1484 genCsBundle_RGATHER_VX(8) 1485 } 1486 } 1487 } 1488 is(UopSplitType.VEC_RGATHEREI16) { 1489 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1490 for (i <- 0 until len) 1491 for (j <- 0 until len) { 1492 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1493 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1494 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1495 // csBundle(i * len + j).srcType(1) := SrcType.vp 1496 // csBundle(i * len + j).srcType(2) := SrcType.vp 1497 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1498 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1499 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1500 csBundle((i * len + j)*2+0).ldest := vd0 1501 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1502 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1503 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1504 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1505 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1506 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1507 csBundle((i * len + j)*2+1).ldest := vd1 1508 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1509 } 1510 } 1511 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1512 for (i <- 0 until len) 1513 for (j <- 0 until len) { 1514 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1515 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1516 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1517 // csBundle(i * len + j).srcType(1) := SrcType.vp 1518 // csBundle(i * len + j).srcType(2) := SrcType.vp 1519 csBundle(i * len + j).lsrc(0) := src1 + i.U 1520 csBundle(i * len + j).lsrc(1) := src2 + j.U 1521 csBundle(i * len + j).lsrc(2) := vd_old 1522 csBundle(i * len + j).ldest := vd 1523 csBundle(i * len + j).uopIdx := (i * len + j).U 1524 } 1525 } 1526 switch(vlmulReg) { 1527 is("b000".U ){ 1528 when(!vsewReg.orR){ 1529 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1530 } .otherwise{ 1531 genCsBundle_VEC_RGATHEREI16(1) 1532 } 1533 } 1534 is("b001".U) { 1535 when(!vsewReg.orR) { 1536 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1537 }.otherwise { 1538 genCsBundle_VEC_RGATHEREI16(2) 1539 } 1540 } 1541 is("b010".U) { 1542 when(!vsewReg.orR) { 1543 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1544 }.otherwise { 1545 genCsBundle_VEC_RGATHEREI16(4) 1546 } 1547 } 1548 is("b011".U) { 1549 genCsBundle_VEC_RGATHEREI16(8) 1550 } 1551 } 1552 } 1553 is(UopSplitType.VEC_COMPRESS) { 1554 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1555 for (i <- 0 until len){ 1556 val jlen = if (i == len-1) i+1 else i+2 1557 for (j <- 0 until jlen) { 1558 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1559 val vd = if(i==len-1) (dest + j.U) else{ 1560 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1561 } 1562 val src23Type = if (j == i+1) DontCare else SrcType.vp 1563 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1564 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1565 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1566 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1567 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1568 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1569 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1570 csBundle(i*(i+3)/2 + j).ldest := vd 1571 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1572 } 1573 } 1574 } 1575 switch(vlmulReg) { 1576 is("b001".U ){ 1577 genCsBundle_VEC_COMPRESS(2) 1578 } 1579 is("b010".U ){ 1580 genCsBundle_VEC_COMPRESS(4) 1581 } 1582 is("b011".U ){ 1583 genCsBundle_VEC_COMPRESS(8) 1584 } 1585 } 1586 } 1587 is(UopSplitType.VEC_US_LD) { 1588 /* 1589 FMV.D.X 1590 */ 1591 csBundle(0).srcType(0) := SrcType.reg 1592 csBundle(0).srcType(1) := SrcType.imm 1593 csBundle(0).lsrc(1) := 0.U 1594 csBundle(0).ldest := FP_TMP_REG_MV.U 1595 csBundle(0).fuType := FuType.i2f.U 1596 csBundle(0).rfWen := false.B 1597 csBundle(0).fpWen := true.B 1598 csBundle(0).vecWen := false.B 1599 csBundle(0).fpu.isAddSub := false.B 1600 csBundle(0).fpu.typeTagIn := FPU.D 1601 csBundle(0).fpu.typeTagOut := FPU.D 1602 csBundle(0).fpu.fromInt := true.B 1603 csBundle(0).fpu.wflags := false.B 1604 csBundle(0).fpu.fpWen := true.B 1605 csBundle(0).fpu.div := false.B 1606 csBundle(0).fpu.sqrt := false.B 1607 csBundle(0).fpu.fcvt := false.B 1608 //LMUL 1609 for (i <- 0 until MAX_VLMUL) { 1610 csBundle(i + 1).srcType(0) := SrcType.fp 1611 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1612 csBundle(i + 1).ldest := dest + i.U 1613 csBundle(i + 1).uopIdx := i.U 1614 } 1615 } 1616 } 1617 1618 //uops dispatch 1619 val s_normal :: s_ext :: Nil = Enum(2) 1620 val state = RegInit(s_normal) 1621 val state_next = WireDefault(state) 1622 val uopRes = RegInit(0.U) 1623 1624 //readyFromRename Counter 1625 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1626 1627 switch(state) { 1628 is(s_normal) { 1629 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1630 } 1631 is(s_ext) { 1632 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1633 } 1634 } 1635 1636 state := state_next 1637 1638 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1639 val uopResJudge = Mux(state === s_normal, 1640 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1641 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1642 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1643 1644 for(i <- 0 until RenameWidth) { 1645 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1646 (state === s_normal) -> csBundle(i), 1647 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1648 ).toSeq) 1649 } 1650 1651 val validSimple = Wire(Vec(DecodeWidth, Bool())) 1652 validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1653 val notInf = Wire(Vec(DecodeWidth, Bool())) 1654 notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1655 notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1656 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1657 notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1658 1659 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1660 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1661 0.U) 1662 validToRename.zipWithIndex.foreach{ 1663 case(dst, i) => 1664 val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1665 dst := MuxCase(false.B, Seq( 1666 (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1667 (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1668 ).toSeq) 1669 } 1670 1671 readyToIBuf.zipWithIndex.foreach { 1672 case (dst, i) => 1673 val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1674 dst := MuxCase(true.B, Seq( 1675 (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1676 (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1677 ).toSeq) 1678 } 1679 1680 io.deq.decodedInsts := decodedInsts 1681 io.deq.isVset := isVsetSimple 1682 io.deq.complexNum := complexNum 1683 io.deq.validToRename := validToRename 1684 io.deq.readyToIBuf := readyToIBuf 1685 1686} 1687