1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import yunsuan.VpermType 33 34import scala.collection.Seq 35 36trait VectorConstants { 37 val MAX_VLMUL = 8 38 val FP_TMP_REG_MV = 32 39 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 40 val VECTOR_VCONFIG = 39 41} 42 43class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 44 val enq = new Bundle { val staticInst = Input(new StaticInst) } 45 val vtype = Input(new VType) 46 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 47 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 48 val readyFromRename = Input(Vec(RenameWidth, Bool())) 49 val deq = new Bundle { 50 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 51 val isVset = Output(Bool()) 52 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 53 val validToRename = Output(Vec(RenameWidth, Bool())) 54 val complexNum = Output(UInt(3.W)) 55 } 56 val csrCtrl = Input(new CustomCSRCtrlIO) 57} 58/** 59 * @author zly 60 */ 61class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 62 val io = IO(new DecodeUnitCompIO) 63 64 val maxUopSize = MaxUopSize 65 //input bits 66 val staticInst = Wire(new StaticInst) 67 68 staticInst := io.enq.staticInst 69 70 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 71 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 72 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 73 74 //output bits 75 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 76 val validToRename = Wire(Vec(RenameWidth, Bool())) 77 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 78 val complexNum = Wire(UInt(3.W)) 79 80 //output of DecodeUnit 81 val decodedInsts_u = Wire(new DecodedInst) 82 val isVset_u = Wire(Bool()) 83 84 //pre decode 85 val simple = Module(new DecodeUnit) 86 simple.io.enq.ctrlFlow := staticInst 87 simple.io.enq.vtype := io.vtype 88 simple.io.csrCtrl := io.csrCtrl 89 decodedInsts_u := simple.io.deq.decodedInst 90 isVset_u := simple.io.deq.decodedInst.isVset 91 when(isVset_u) { 92 when(dest === 0.U && src1 === 0.U) { 93 decodedInsts_u.fuOpType := VSETOpType.convert2oldvl(simple.io.deq.decodedInst.fuOpType) 94 }.elsewhen(src1 === 0.U) { 95 decodedInsts_u.fuOpType := VSETOpType.convert2vlmax(simple.io.deq.decodedInst.fuOpType) 96 } 97 } 98 //Type of uop Div 99 val typeOfDiv = decodedInsts_u.uopDivType 100 101 //LMUL 102 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 103 "b001".U -> 2.U, 104 "b010".U -> 4.U, 105 "b011".U -> 8.U 106 )) 107 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 108 "b001".U -> 3.U, 109 "b010".U -> 10.U, 110 "b011".U -> 36.U 111 )) 112 //number of uop 113 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 114 UopDivType.VEC_0XV -> 2.U, 115 UopDivType.DIR -> Mux(dest =/= 0.U, 2.U, 116 Mux(src1 =/= 0.U, 1.U, 117 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 118 UopDivType.VEC_VVV -> lmul, 119 UopDivType.VEC_EXT2 -> lmul, 120 UopDivType.VEC_EXT4 -> lmul, 121 UopDivType.VEC_EXT8 -> lmul, 122 UopDivType.VEC_VVM -> lmul, 123 UopDivType.VEC_VXM -> (lmul +& 1.U), 124 UopDivType.VEC_VXV -> (lmul +& 1.U), 125 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 126 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 127 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 128 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 129 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 130 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 131 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 132 UopDivType.VEC_FSLIDE1UP -> lmul, 133 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 134 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 135 UopDivType.VEC_VRED -> lmul, 136 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 137 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 138 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 139 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 140 UopDivType.VEC_M0X -> (lmul +& 1.U), 141 UopDivType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 142 UopDivType.VEC_M0X_VFIRST -> 2.U, 143 )) 144 145 //uop div up to maxUopSize 146 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 147 csBundle.map { case dst => 148 dst := decodedInsts_u 149 dst.firstUop := false.B 150 dst.lastUop := false.B 151 } 152 153 csBundle(0).firstUop := true.B 154 csBundle(numOfUop - 1.U).lastUop := true.B 155 156 switch(typeOfDiv) { 157 is(UopDivType.DIR) { 158 when(isVset_u) { 159 when(dest =/= 0.U) { 160 csBundle(0).fuType := FuType.vsetiwi.U 161 csBundle(0).fuOpType := VSETOpType.convert2uvsetvl(decodedInsts_u.fuOpType) 162 csBundle(0).flushPipe := false.B 163 csBundle(0).rfWen := true.B 164 csBundle(0).vecWen := false.B 165 csBundle(1).ldest := VECTOR_VCONFIG.U 166 }.elsewhen(src1 =/= 0.U) { 167 csBundle(0).ldest := VECTOR_VCONFIG.U 168 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 169 csBundle(0).fuType := FuType.vsetfwf.U 170 csBundle(0).srcType(0) := SrcType.vp 171 csBundle(0).lsrc(0) := VECTOR_VCONFIG.U 172 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 173 csBundle(0).srcType(0) := SrcType.reg 174 csBundle(0).srcType(1) := SrcType.imm 175 csBundle(0).lsrc(1) := 0.U 176 csBundle(0).ldest := FP_TMP_REG_MV.U 177 csBundle(0).fuType := FuType.i2f.U 178 csBundle(0).rfWen := false.B 179 csBundle(0).fpWen := true.B 180 csBundle(0).vecWen := false.B 181 csBundle(0).fpu.isAddSub := false.B 182 csBundle(0).fpu.typeTagIn := FPU.D 183 csBundle(0).fpu.typeTagOut := FPU.D 184 csBundle(0).fpu.fromInt := true.B 185 csBundle(0).fpu.wflags := false.B 186 csBundle(0).fpu.fpWen := true.B 187 csBundle(0).fpu.div := false.B 188 csBundle(0).fpu.sqrt := false.B 189 csBundle(0).fpu.fcvt := false.B 190 csBundle(0).flushPipe := false.B 191 csBundle(1).fuType := FuType.vsetfwf.U 192 csBundle(1).srcType(0) := SrcType.vp 193 csBundle(1).lsrc(0) := VECTOR_VCONFIG.U 194 csBundle(1).srcType(1) := SrcType.fp 195 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 196 csBundle(1).ldest := VECTOR_VCONFIG.U 197 } 198 } 199 } 200 is(UopDivType.VEC_VVV) { 201 for (i <- 0 until MAX_VLMUL) { 202 csBundle(i).lsrc(0) := src1 + i.U 203 csBundle(i).lsrc(1) := src2 + i.U 204 csBundle(i).lsrc(2) := dest + i.U 205 csBundle(i).ldest := dest + i.U 206 csBundle(i).uopIdx := i.U 207 } 208 } 209 is(UopDivType.VEC_EXT2) { 210 for (i <- 0 until MAX_VLMUL / 2) { 211 csBundle(2 * i).lsrc(1) := src2 + i.U 212 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 213 csBundle(2 * i).ldest := dest + (2 * i).U 214 csBundle(2 * i).uopIdx := (2 * i).U 215 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 216 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 217 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 218 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 219 } 220 } 221 is(UopDivType.VEC_EXT4) { 222 for (i <- 0 until MAX_VLMUL / 4) { 223 csBundle(4 * i).lsrc(1) := src2 + i.U 224 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 225 csBundle(4 * i).ldest := dest + (4 * i).U 226 csBundle(4 * i).uopIdx := (4 * i).U 227 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 228 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 229 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 230 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 231 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 232 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 233 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 234 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 235 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 236 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 237 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 238 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 239 } 240 } 241 is(UopDivType.VEC_EXT8) { 242 for (i <- 0 until MAX_VLMUL) { 243 csBundle(i).lsrc(1) := src2 244 csBundle(i).lsrc(2) := dest + i.U 245 csBundle(i).ldest := dest + i.U 246 csBundle(i).uopIdx := i.U 247 } 248 } 249 is(UopDivType.VEC_0XV) { 250 /* 251 FMV.D.X 252 */ 253 csBundle(0).srcType(0) := SrcType.reg 254 csBundle(0).srcType(1) := SrcType.imm 255 csBundle(0).lsrc(1) := 0.U 256 csBundle(0).ldest := FP_TMP_REG_MV.U 257 csBundle(0).fuType := FuType.i2f.U 258 csBundle(0).rfWen := false.B 259 csBundle(0).fpWen := true.B 260 csBundle(0).vecWen := false.B 261 csBundle(0).fpu.isAddSub := false.B 262 csBundle(0).fpu.typeTagIn := FPU.D 263 csBundle(0).fpu.typeTagOut := FPU.D 264 csBundle(0).fpu.fromInt := true.B 265 csBundle(0).fpu.wflags := false.B 266 csBundle(0).fpu.fpWen := true.B 267 csBundle(0).fpu.div := false.B 268 csBundle(0).fpu.sqrt := false.B 269 csBundle(0).fpu.fcvt := false.B 270 /* 271 vfmv.s.f 272 */ 273 csBundle(1).srcType(0) := SrcType.fp 274 csBundle(1).srcType(1) := SrcType.vp 275 csBundle(1).srcType(2) := SrcType.vp 276 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 277 csBundle(1).lsrc(1) := 0.U 278 csBundle(1).lsrc(2) := dest 279 csBundle(1).ldest := dest 280 csBundle(1).fuType := FuType.vppu.U 281 csBundle(1).fuOpType := VpermType.vfmv_s_f 282 csBundle(1).rfWen := false.B 283 csBundle(1).fpWen := false.B 284 csBundle(1).vecWen := true.B 285 } 286 is(UopDivType.VEC_VXV) { 287 /* 288 FMV.D.X 289 */ 290 csBundle(0).srcType(0) := SrcType.reg 291 csBundle(0).srcType(1) := SrcType.imm 292 csBundle(0).lsrc(1) := 0.U 293 csBundle(0).ldest := FP_TMP_REG_MV.U 294 csBundle(0).fuType := FuType.i2f.U 295 csBundle(0).rfWen := false.B 296 csBundle(0).fpWen := true.B 297 csBundle(0).vecWen := false.B 298 csBundle(0).fpu.isAddSub := false.B 299 csBundle(0).fpu.typeTagIn := FPU.D 300 csBundle(0).fpu.typeTagOut := FPU.D 301 csBundle(0).fpu.fromInt := true.B 302 csBundle(0).fpu.wflags := false.B 303 csBundle(0).fpu.fpWen := true.B 304 csBundle(0).fpu.div := false.B 305 csBundle(0).fpu.sqrt := false.B 306 csBundle(0).fpu.fcvt := false.B 307 /* 308 LMUL 309 */ 310 for (i <- 0 until MAX_VLMUL) { 311 csBundle(i + 1).srcType(0) := SrcType.fp 312 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 313 csBundle(i + 1).lsrc(1) := src2 + i.U 314 csBundle(i + 1).lsrc(2) := dest + i.U 315 csBundle(i + 1).ldest := dest + i.U 316 csBundle(i + 1).uopIdx := i.U 317 } 318 } 319 is(UopDivType.VEC_VVW) { 320 for (i <- 0 until MAX_VLMUL / 2) { 321 csBundle(2 * i).lsrc(0) := src1 + i.U 322 csBundle(2 * i).lsrc(1) := src2 + i.U 323 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 324 csBundle(2 * i).ldest := dest + (2 * i).U 325 csBundle(2 * i).uopIdx := (2 * i).U 326 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 327 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 328 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 329 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 331 } 332 } 333 is(UopDivType.VEC_WVW) { 334 for (i <- 0 until MAX_VLMUL / 2) { 335 csBundle(2 * i).lsrc(0) := src1 + i.U 336 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 337 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 338 csBundle(2 * i).ldest := dest + (2 * i).U 339 csBundle(2 * i).uopIdx := (2 * i).U 340 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 341 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 342 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 343 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 345 } 346 } 347 is(UopDivType.VEC_VXW) { 348 /* 349 FMV.D.X 350 */ 351 csBundle(0).srcType(0) := SrcType.reg 352 csBundle(0).srcType(1) := SrcType.imm 353 csBundle(0).lsrc(1) := 0.U 354 csBundle(0).ldest := FP_TMP_REG_MV.U 355 csBundle(0).fuType := FuType.i2f.U 356 csBundle(0).rfWen := false.B 357 csBundle(0).fpWen := true.B 358 csBundle(0).vecWen := false.B 359 csBundle(0).fpu.isAddSub := false.B 360 csBundle(0).fpu.typeTagIn := FPU.D 361 csBundle(0).fpu.typeTagOut := FPU.D 362 csBundle(0).fpu.fromInt := true.B 363 csBundle(0).fpu.wflags := false.B 364 csBundle(0).fpu.fpWen := true.B 365 csBundle(0).fpu.div := false.B 366 csBundle(0).fpu.sqrt := false.B 367 csBundle(0).fpu.fcvt := false.B 368 369 for (i <- 0 until MAX_VLMUL / 2) { 370 csBundle(2 * i + 1).srcType(0) := SrcType.fp 371 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 372 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 373 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 374 csBundle(2 * i + 1).ldest := dest + (2 * i).U 375 csBundle(2 * i + 1).uopIdx := (2 * i).U 376 csBundle(2 * i + 2).srcType(0) := SrcType.fp 377 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 378 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 379 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 380 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 382 } 383 } 384 is(UopDivType.VEC_WXW) { 385 /* 386 FMV.D.X 387 */ 388 csBundle(0).srcType(0) := SrcType.reg 389 csBundle(0).srcType(1) := SrcType.imm 390 csBundle(0).lsrc(1) := 0.U 391 csBundle(0).ldest := FP_TMP_REG_MV.U 392 csBundle(0).fuType := FuType.i2f.U 393 csBundle(0).rfWen := false.B 394 csBundle(0).fpWen := true.B 395 csBundle(0).vecWen := false.B 396 csBundle(0).fpu.isAddSub := false.B 397 csBundle(0).fpu.typeTagIn := FPU.D 398 csBundle(0).fpu.typeTagOut := FPU.D 399 csBundle(0).fpu.fromInt := true.B 400 csBundle(0).fpu.wflags := false.B 401 csBundle(0).fpu.fpWen := true.B 402 csBundle(0).fpu.div := false.B 403 csBundle(0).fpu.sqrt := false.B 404 csBundle(0).fpu.fcvt := false.B 405 406 for (i <- 0 until MAX_VLMUL / 2) { 407 csBundle(2 * i + 1).srcType(0) := SrcType.fp 408 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 409 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 410 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 411 csBundle(2 * i + 1).ldest := dest + (2 * i).U 412 csBundle(2 * i + 1).uopIdx := (2 * i).U 413 csBundle(2 * i + 2).srcType(0) := SrcType.fp 414 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 415 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 416 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 417 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 419 } 420 } 421 is(UopDivType.VEC_WVV) { 422 for (i <- 0 until MAX_VLMUL / 2) { 423 424 csBundle(2 * i).lsrc(0) := src1 + i.U 425 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 426 csBundle(2 * i).lsrc(2) := dest + i.U 427 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 428 csBundle(2 * i).uopIdx := (2 * i).U 429 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 430 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 431 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 432 csBundle(2 * i + 1).ldest := dest + i.U 433 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 434 } 435 } 436 is(UopDivType.VEC_WXV) { 437 /* 438 FMV.D.X 439 */ 440 csBundle(0).srcType(0) := SrcType.reg 441 csBundle(0).srcType(1) := SrcType.imm 442 csBundle(0).lsrc(1) := 0.U 443 csBundle(0).ldest := FP_TMP_REG_MV.U 444 csBundle(0).fuType := FuType.i2f.U 445 csBundle(0).rfWen := false.B 446 csBundle(0).fpWen := true.B 447 csBundle(0).vecWen := false.B 448 csBundle(0).fpu.isAddSub := false.B 449 csBundle(0).fpu.typeTagIn := FPU.D 450 csBundle(0).fpu.typeTagOut := FPU.D 451 csBundle(0).fpu.fromInt := true.B 452 csBundle(0).fpu.wflags := false.B 453 csBundle(0).fpu.fpWen := true.B 454 csBundle(0).fpu.div := false.B 455 csBundle(0).fpu.sqrt := false.B 456 csBundle(0).fpu.fcvt := false.B 457 458 for (i <- 0 until MAX_VLMUL / 2) { 459 csBundle(2 * i + 1).srcType(0) := SrcType.fp 460 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 461 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 462 csBundle(2 * i + 1).lsrc(2) := dest + i.U 463 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 464 csBundle(2 * i + 1).uopIdx := (2 * i).U 465 csBundle(2 * i + 2).srcType(0) := SrcType.fp 466 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 467 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 468 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 469 csBundle(2 * i + 2).ldest := dest + i.U 470 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 471 } 472 } 473 is(UopDivType.VEC_VVM) { 474 csBundle(0).lsrc(2) := dest 475 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 476 csBundle(0).uopIdx := 0.U 477 for(i <- 1 until MAX_VLMUL) { 478 csBundle(i).lsrc(0) := src1 + i.U 479 csBundle(i).lsrc(1) := src2 + i.U 480 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 481 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 482 csBundle(i).uopIdx := i.U 483 } 484 csBundle(numOfUop - 1.U).ldest := dest 485 } 486 is(UopDivType.VEC_VXM) { 487 /* 488 FMV.D.X 489 */ 490 csBundle(0).srcType(0) := SrcType.reg 491 csBundle(0).srcType(1) := SrcType.imm 492 csBundle(0).lsrc(1) := 0.U 493 csBundle(0).ldest := FP_TMP_REG_MV.U 494 csBundle(0).fuType := FuType.i2f.U 495 csBundle(0).rfWen := false.B 496 csBundle(0).fpWen := true.B 497 csBundle(0).vecWen := false.B 498 csBundle(0).fpu.isAddSub := false.B 499 csBundle(0).fpu.typeTagIn := FPU.D 500 csBundle(0).fpu.typeTagOut := FPU.D 501 csBundle(0).fpu.fromInt := true.B 502 csBundle(0).fpu.wflags := false.B 503 csBundle(0).fpu.fpWen := true.B 504 csBundle(0).fpu.div := false.B 505 csBundle(0).fpu.sqrt := false.B 506 csBundle(0).fpu.fcvt := false.B 507 //LMUL 508 csBundle(1).srcType(0) := SrcType.fp 509 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 510 csBundle(1).lsrc(2) := dest 511 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 512 csBundle(1).uopIdx := 0.U 513 for (i <- 1 until MAX_VLMUL) { 514 csBundle(i + 1).srcType(0) := SrcType.fp 515 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 516 csBundle(i + 1).lsrc(1) := src2 + i.U 517 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 518 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 519 csBundle(i + 1).uopIdx := i.U 520 } 521 csBundle(numOfUop - 1.U).ldest := dest 522 } 523 is(UopDivType.VEC_SLIDE1UP) { 524 /* 525 FMV.D.X 526 */ 527 csBundle(0).srcType(0) := SrcType.reg 528 csBundle(0).srcType(1) := SrcType.imm 529 csBundle(0).lsrc(1) := 0.U 530 csBundle(0).ldest := FP_TMP_REG_MV.U 531 csBundle(0).fuType := FuType.i2f.U 532 csBundle(0).rfWen := false.B 533 csBundle(0).fpWen := true.B 534 csBundle(0).vecWen := false.B 535 csBundle(0).fpu.isAddSub := false.B 536 csBundle(0).fpu.typeTagIn := FPU.D 537 csBundle(0).fpu.typeTagOut := FPU.D 538 csBundle(0).fpu.fromInt := true.B 539 csBundle(0).fpu.wflags := false.B 540 csBundle(0).fpu.fpWen := true.B 541 csBundle(0).fpu.div := false.B 542 csBundle(0).fpu.sqrt := false.B 543 csBundle(0).fpu.fcvt := false.B 544 //LMUL 545 csBundle(1).srcType(0) := SrcType.fp 546 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 547 csBundle(1).lsrc(2) := dest 548 csBundle(1).ldest := dest 549 csBundle(1).uopIdx := 0.U 550 for (i <- 1 until MAX_VLMUL) { 551 csBundle(i + 1).srcType(0) := SrcType.vp 552 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 553 csBundle(i + 1).lsrc(1) := src2 + i.U 554 csBundle(i + 1).lsrc(2) := dest + i.U 555 csBundle(i + 1).ldest := dest + i.U 556 csBundle(i + 1).uopIdx := i.U 557 } 558 } 559 is(UopDivType.VEC_FSLIDE1UP) { 560 //LMUL 561 csBundle(0).srcType(0) := SrcType.fp 562 csBundle(0).lsrc(0) := src1 563 csBundle(0).lsrc(1) := src2 564 csBundle(0).lsrc(2) := dest 565 csBundle(0).ldest := dest 566 csBundle(0).uopIdx := 0.U 567 for (i <- 1 until MAX_VLMUL) { 568 csBundle(i).srcType(0) := SrcType.vp 569 csBundle(i).lsrc(0) := src2 + (i - 1).U 570 csBundle(i).lsrc(1) := src2 + i.U 571 csBundle(i).lsrc(2) := dest + i.U 572 csBundle(i).ldest := dest + i.U 573 csBundle(i).uopIdx := i.U 574 } 575 } 576 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 577 /* 578 FMV.D.X 579 */ 580 csBundle(0).srcType(0) := SrcType.reg 581 csBundle(0).srcType(1) := SrcType.imm 582 csBundle(0).lsrc(1) := 0.U 583 csBundle(0).ldest := FP_TMP_REG_MV.U 584 csBundle(0).fuType := FuType.i2f.U 585 csBundle(0).rfWen := false.B 586 csBundle(0).fpWen := true.B 587 csBundle(0).vecWen := false.B 588 csBundle(0).fpu.isAddSub := false.B 589 csBundle(0).fpu.typeTagIn := FPU.D 590 csBundle(0).fpu.typeTagOut := FPU.D 591 csBundle(0).fpu.fromInt := true.B 592 csBundle(0).fpu.wflags := false.B 593 csBundle(0).fpu.fpWen := true.B 594 csBundle(0).fpu.div := false.B 595 csBundle(0).fpu.sqrt := false.B 596 csBundle(0).fpu.fcvt := false.B 597 //LMUL 598 for (i <- 0 until MAX_VLMUL) { 599 csBundle(2 * i + 1).srcType(0) := SrcType.vp 600 csBundle(2 * i + 1).srcType(1) := SrcType.vp 601 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 602 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 603 csBundle(2 * i + 1).lsrc(2) := dest + i.U 604 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 605 csBundle(2 * i + 1).uopIdx := (2 * i).U 606 if (2 * i + 2 < MAX_VLMUL * 2 ){ 607 csBundle(2 * i + 2).srcType(0) := SrcType.fp 608 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 609 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 610 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 611 csBundle(2 * i + 2).ldest := dest + i.U 612 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 613 } 614 } 615 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 616 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 617 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 618 } 619 is(UopDivType.VEC_FSLIDE1DOWN) { 620 //LMUL 621 for (i <- 0 until MAX_VLMUL) { 622 csBundle(2 * i).srcType(0) := SrcType.vp 623 csBundle(2 * i).srcType(1) := SrcType.vp 624 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 625 csBundle(2 * i).lsrc(1) := src2 + i.U 626 csBundle(2 * i).lsrc(2) := dest + i.U 627 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 628 csBundle(2 * i).uopIdx := (2 * i).U 629 csBundle(2 * i + 1).srcType(0) := SrcType.fp 630 csBundle(2 * i + 1).lsrc(0) := src1 631 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 632 csBundle(2 * i + 1).ldest := dest + i.U 633 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 634 } 635 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 636 csBundle(numOfUop - 1.U).lsrc(0) := src1 637 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 638 } 639 is(UopDivType.VEC_VRED) { 640 when(simple.io.enq.vtype.vlmul === "b001".U){ 641 csBundle(0).srcType(2) := SrcType.DC 642 csBundle(0).lsrc(0) := src2 + 1.U 643 csBundle(0).lsrc(1) := src2 644 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 645 csBundle(0).uopIdx := 0.U 646 } 647 when(simple.io.enq.vtype.vlmul === "b010".U) { 648 csBundle(0).srcType(2) := SrcType.DC 649 csBundle(0).lsrc(0) := src2 + 1.U 650 csBundle(0).lsrc(1) := src2 651 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 652 csBundle(0).uopIdx := 0.U 653 654 csBundle(1).srcType(2) := SrcType.DC 655 csBundle(1).lsrc(0) := src2 + 3.U 656 csBundle(1).lsrc(1) := src2 + 2.U 657 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 658 csBundle(1).uopIdx := 1.U 659 660 csBundle(2).srcType(2) := SrcType.DC 661 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 662 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 663 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 664 csBundle(2).uopIdx := 2.U 665 } 666 when(simple.io.enq.vtype.vlmul === "b011".U) { 667 for(i <- 0 until MAX_VLMUL){ 668 if(i < MAX_VLMUL - MAX_VLMUL/2){ 669 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 670 csBundle(i).lsrc(1) := src2 + (i * 2).U 671 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 672 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 673 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 674 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 675 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 676 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 677 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 678 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 679 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 680 } 681 csBundle(i).srcType(2) := SrcType.DC 682 csBundle(i).uopIdx := i.U 683 } 684 } 685 when (simple.io.enq.vtype.vlmul.orR()){ 686 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 687 csBundle(numOfUop - 1.U).lsrc(0) := src1 688 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 689 csBundle(numOfUop - 1.U).lsrc(2) := dest 690 csBundle(numOfUop - 1.U).ldest := dest 691 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 692 } 693 } 694 695 is(UopDivType.VEC_SLIDEUP) { 696 // FMV.D.X 697 csBundle(0).srcType(0) := SrcType.reg 698 csBundle(0).srcType(1) := SrcType.imm 699 csBundle(0).lsrc(1) := 0.U 700 csBundle(0).ldest := FP_TMP_REG_MV.U 701 csBundle(0).fuType := FuType.i2f.U 702 csBundle(0).rfWen := false.B 703 csBundle(0).fpWen := true.B 704 csBundle(0).vecWen := false.B 705 csBundle(0).fpu.isAddSub := false.B 706 csBundle(0).fpu.typeTagIn := FPU.D 707 csBundle(0).fpu.typeTagOut := FPU.D 708 csBundle(0).fpu.fromInt := true.B 709 csBundle(0).fpu.wflags := false.B 710 csBundle(0).fpu.fpWen := true.B 711 csBundle(0).fpu.div := false.B 712 csBundle(0).fpu.sqrt := false.B 713 csBundle(0).fpu.fcvt := false.B 714 // LMUL 715 for(i <- 0 until MAX_VLMUL) 716 for(j <- 0 to i){ 717 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 718 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 719 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 720 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 721 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 722 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 723 csBundle(i*(i+1)/2+j+1).ldest := vd 724 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 725 } 726 } 727 728 is(UopDivType.VEC_ISLIDEUP) { 729 // LMUL 730 for(i <- 0 until MAX_VLMUL) 731 for(j <- 0 to i){ 732 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 733 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 734 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 735 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 736 csBundle(i*(i+1)/2+j).ldest := vd 737 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 738 } 739 } 740 741 is(UopDivType.VEC_SLIDEDOWN) { 742 // FMV.D.X 743 csBundle(0).srcType(0) := SrcType.reg 744 csBundle(0).srcType(1) := SrcType.imm 745 csBundle(0).lsrc(1) := 0.U 746 csBundle(0).ldest := FP_TMP_REG_MV.U 747 csBundle(0).fuType := FuType.i2f.U 748 csBundle(0).rfWen := false.B 749 csBundle(0).fpWen := true.B 750 csBundle(0).vecWen := false.B 751 csBundle(0).fpu.isAddSub := false.B 752 csBundle(0).fpu.typeTagIn := FPU.D 753 csBundle(0).fpu.typeTagOut := FPU.D 754 csBundle(0).fpu.fromInt := true.B 755 csBundle(0).fpu.wflags := false.B 756 csBundle(0).fpu.fpWen := true.B 757 csBundle(0).fpu.div := false.B 758 csBundle(0).fpu.sqrt := false.B 759 csBundle(0).fpu.fcvt := false.B 760 // LMUL 761 for(i <- 0 until MAX_VLMUL) 762 for(j <- (0 to i).reverse){ 763 when(i.U < lmul){ 764 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 765 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 766 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 767 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 768 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 769 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 770 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 771 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 772 } 773 } 774 } 775 776 is(UopDivType.VEC_ISLIDEDOWN) { 777 // LMUL 778 for(i <- 0 until MAX_VLMUL) 779 for(j <- (0 to i).reverse){ 780 when(i.U < lmul){ 781 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 782 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 783 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 784 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 785 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 786 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 787 } 788 } 789 } 790 791 is(UopDivType.VEC_M0X) { 792 // LMUL 793 for (i <- 0 until MAX_VLMUL) { 794 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 795 val ldest = (VECTOR_TMP_REG_LMUL + i).U 796 csBundle(i).srcType(0) := srcType0 797 csBundle(i).srcType(1) := SrcType.vp 798 csBundle(i).rfWen := false.B 799 csBundle(i).vecWen := true.B 800 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 801 csBundle(i).lsrc(1) := src2 802 // csBundle(i).lsrc(2) := dest + i.U DontCare 803 csBundle(i).ldest := ldest 804 csBundle(i).uopIdx := i.U 805 } 806 csBundle(lmul-1.U).vecWen := false.B 807 csBundle(lmul-1.U).fpWen := true.B 808 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 809 // FMV_X_D 810 csBundle(lmul).srcType(0) := SrcType.fp 811 csBundle(lmul).srcType(1) := SrcType.imm 812 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 813 csBundle(lmul).lsrc(1) := 0.U 814 csBundle(lmul).ldest := dest 815 csBundle(lmul).fuType := FuType.fmisc.U 816 csBundle(lmul).rfWen := true.B 817 csBundle(lmul).fpWen := false.B 818 csBundle(lmul).vecWen := false.B 819 csBundle(lmul).fpu.isAddSub := false.B 820 csBundle(lmul).fpu.typeTagIn := FPU.D 821 csBundle(lmul).fpu.typeTagOut := FPU.D 822 csBundle(lmul).fpu.fromInt := false.B 823 csBundle(lmul).fpu.wflags := false.B 824 csBundle(lmul).fpu.fpWen := false.B 825 csBundle(lmul).fpu.div := false.B 826 csBundle(lmul).fpu.sqrt := false.B 827 csBundle(lmul).fpu.fcvt := false.B 828 } 829 830 is(UopDivType.VEC_MVV) { 831 // LMUL 832 for (i <- 0 until MAX_VLMUL) { 833 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 834 csBundle(i*2+0).srcType(0) := srcType0 835 csBundle(i*2+0).srcType(1) := SrcType.vp 836 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 837 csBundle(i*2+0).lsrc(1) := src2 838 csBundle(i*2+0).lsrc(2) := dest + i.U 839 csBundle(i*2+0).ldest := dest + i.U 840 csBundle(i*2+0).uopIdx := (i*2+0).U 841 842 csBundle(i*2+1).srcType(0) := srcType0 843 csBundle(i*2+1).srcType(1) := SrcType.vp 844 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 845 csBundle(i*2+1).lsrc(1) := src2 846 // csBundle(i).lsrc(2) := dest + i.U DontCare 847 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 848 csBundle(i*2+1).uopIdx := (i*2+1).U 849 } 850 } 851 852 is(UopDivType.VEC_M0X_VFIRST) { 853 // LMUL 854 csBundle(0).rfWen := false.B 855 csBundle(0).fpWen := true.B 856 csBundle(0).ldest := FP_TMP_REG_MV.U 857 // FMV_X_D 858 csBundle(1).srcType(0) := SrcType.fp 859 csBundle(1).srcType(1) := SrcType.imm 860 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 861 csBundle(1).lsrc(1) := 0.U 862 csBundle(1).ldest := dest 863 csBundle(1).fuType := FuType.fmisc.U 864 csBundle(1).rfWen := true.B 865 csBundle(1).fpWen := false.B 866 csBundle(1).vecWen := false.B 867 csBundle(1).fpu.isAddSub := false.B 868 csBundle(1).fpu.typeTagIn := FPU.D 869 csBundle(1).fpu.typeTagOut := FPU.D 870 csBundle(1).fpu.fromInt := false.B 871 csBundle(1).fpu.wflags := false.B 872 csBundle(1).fpu.fpWen := false.B 873 csBundle(1).fpu.div := false.B 874 csBundle(1).fpu.sqrt := false.B 875 csBundle(1).fpu.fcvt := false.B 876 } 877 } 878 879 //uops dispatch 880 val normal :: ext :: Nil = Enum(2) 881 val stateReg = RegInit(normal) 882 val uopRes = RegInit(0.U) 883 884 //readyFromRename Counter 885 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 886 887 switch(stateReg) { 888 is(normal) { 889 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 890 } 891 is(ext) { 892 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 893 } 894 } 895 896 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 897 val uopResJudge = Mux(stateReg === normal, 898 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 899 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 900 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 901 902 for(i <- 0 until RenameWidth) { 903 decodedInsts(i) := MuxCase(csBundle(i), Seq( 904 (stateReg === normal) -> csBundle(i), 905 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 906 )) 907 } 908 909 910 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 911 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 912 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 913 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 914 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 915 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 916 notInfVec(0) := true.B 917 918 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 919 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 920 1.U) 921 validToRename.zipWithIndex.foreach{ 922 case(dst, i) => 923 dst := MuxCase(false.B, Seq( 924 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 925 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 926 )) 927 } 928 929 readyToIBuf.zipWithIndex.foreach { 930 case (dst, i) => 931 dst := MuxCase(true.B, Seq( 932 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 933 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 934 )) 935 } 936 937 io.deq.decodedInsts := decodedInsts 938 io.deq.isVset := isVset_u 939 io.deq.complexNum := complexNum 940 io.deq.validToRename := validToRename 941 io.deq.readyToIBuf := readyToIBuf 942 943} 944 945