1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41} 42 43class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 44 val enq = new Bundle { val staticInst = Input(new StaticInst) } 45 val vtype = Input(new VType) 46 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 47 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 48 val readyFromRename = Input(Vec(RenameWidth, Bool())) 49 val deq = new Bundle { 50 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 51 val isVset = Output(Bool()) 52 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 53 val validToRename = Output(Vec(RenameWidth, Bool())) 54 val complexNum = Output(UInt(3.W)) 55 } 56 val csrCtrl = Input(new CustomCSRCtrlIO) 57} 58 59/** 60 * @author zly 61 */ 62class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 63 val io = IO(new DecodeUnitCompIO) 64 65 val maxUopSize = MaxUopSize 66 //input bits 67 val staticInst = Wire(new StaticInst) 68 69 staticInst := io.enq.staticInst 70 71 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 72 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 73 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 74 75 //output bits 76 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 77 val validToRename = Wire(Vec(RenameWidth, Bool())) 78 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 79 val complexNum = Wire(UInt(3.W)) 80 81 //output of DecodeUnit 82 val decodedInsts_u = Wire(new DecodedInst) 83 val isVset_u = Wire(Bool()) 84 85 //pre decode 86 val simple = Module(new DecodeUnit) 87 simple.io.enq.ctrlFlow := staticInst 88 simple.io.enq.vtype := io.vtype 89 simple.io.csrCtrl := io.csrCtrl 90 decodedInsts_u := simple.io.deq.decodedInst 91 isVset_u := simple.io.deq.decodedInst.isVset 92 when(isVset_u) { 93 when(dest === 0.U && src1 === 0.U) { 94 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 95 }.elsewhen(src1 === 0.U) { 96 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 97 } 98 when(io.vtype.illegal){ 99 decodedInsts_u.flushPipe := true.B 100 } 101 } 102 //Type of uop Div 103 val typeOfDiv = decodedInsts_u.uopSplitType 104 105 //LMUL 106 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 107 "b001".U -> 2.U, 108 "b010".U -> 4.U, 109 "b011".U -> 8.U 110 )) 111 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 112 "b001".U -> 3.U, 113 "b010".U -> 10.U, 114 "b011".U -> 36.U 115 )) 116 //number of uop 117 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 118 UopSplitType.VEC_0XV -> 2.U, 119 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 120 Mux(src1 =/= 0.U, 1.U, 121 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 122 UopSplitType.VEC_VVV -> lmul, 123 UopSplitType.VEC_EXT2 -> lmul, 124 UopSplitType.VEC_EXT4 -> lmul, 125 UopSplitType.VEC_EXT8 -> lmul, 126 UopSplitType.VEC_VVM -> lmul, 127 UopSplitType.VEC_VXM -> (lmul +& 1.U), 128 UopSplitType.VEC_VXV -> (lmul +& 1.U), 129 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 130 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 131 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 132 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 133 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 134 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 135 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 136 UopSplitType.VEC_FSLIDE1UP -> lmul, 137 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 138 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 139 UopSplitType.VEC_VRED -> lmul, 140 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 141 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 142 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 143 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 144 UopSplitType.VEC_M0X -> (lmul +& 1.U), 145 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 146 UopSplitType.VEC_M0X_VFIRST -> 2.U, 147 )) 148 149 //uop div up to maxUopSize 150 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 151 csBundle.map { case dst => 152 dst := decodedInsts_u 153 dst.firstUop := false.B 154 dst.lastUop := false.B 155 } 156 157 csBundle(0).firstUop := true.B 158 csBundle(numOfUop - 1.U).lastUop := true.B 159 160 switch(typeOfDiv) { 161 is(UopSplitType.DIR) { 162 when(isVset_u) { 163 when(dest =/= 0.U) { 164 csBundle(0).fuType := FuType.vsetiwi.U 165 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 166 csBundle(0).flushPipe := false.B 167 csBundle(0).rfWen := true.B 168 csBundle(0).vecWen := false.B 169 csBundle(1).ldest := VCONFIG_IDX.U 170 csBundle(1).rfWen := false.B 171 csBundle(1).vecWen := true.B 172 }.elsewhen(src1 =/= 0.U) { 173 csBundle(0).ldest := VCONFIG_IDX.U 174 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 175 csBundle(0).fuType := FuType.vsetfwf.U 176 csBundle(0).srcType(0) := SrcType.vp 177 csBundle(0).lsrc(0) := VCONFIG_IDX.U 178 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 179 csBundle(0).srcType(0) := SrcType.reg 180 csBundle(0).srcType(1) := SrcType.imm 181 csBundle(0).lsrc(1) := 0.U 182 csBundle(0).ldest := FP_TMP_REG_MV.U 183 csBundle(0).fuType := FuType.i2f.U 184 csBundle(0).rfWen := false.B 185 csBundle(0).fpWen := true.B 186 csBundle(0).vecWen := false.B 187 csBundle(0).fpu.isAddSub := false.B 188 csBundle(0).fpu.typeTagIn := FPU.D 189 csBundle(0).fpu.typeTagOut := FPU.D 190 csBundle(0).fpu.fromInt := true.B 191 csBundle(0).fpu.wflags := false.B 192 csBundle(0).fpu.fpWen := true.B 193 csBundle(0).fpu.div := false.B 194 csBundle(0).fpu.sqrt := false.B 195 csBundle(0).fpu.fcvt := false.B 196 csBundle(0).flushPipe := false.B 197 csBundle(1).fuType := FuType.vsetfwf.U 198 csBundle(1).srcType(0) := SrcType.vp 199 csBundle(1).lsrc(0) := VCONFIG_IDX.U 200 csBundle(1).srcType(1) := SrcType.fp 201 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 202 csBundle(1).ldest := VCONFIG_IDX.U 203 } 204 } 205 } 206 is(UopSplitType.VEC_VVV) { 207 for (i <- 0 until MAX_VLMUL) { 208 csBundle(i).lsrc(0) := src1 + i.U 209 csBundle(i).lsrc(1) := src2 + i.U 210 csBundle(i).lsrc(2) := dest + i.U 211 csBundle(i).ldest := dest + i.U 212 csBundle(i).uopIdx := i.U 213 } 214 } 215 is(UopSplitType.VEC_EXT2) { 216 for (i <- 0 until MAX_VLMUL / 2) { 217 csBundle(2 * i).lsrc(1) := src2 + i.U 218 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 219 csBundle(2 * i).ldest := dest + (2 * i).U 220 csBundle(2 * i).uopIdx := (2 * i).U 221 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 222 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 223 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 224 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 225 } 226 } 227 is(UopSplitType.VEC_EXT4) { 228 for (i <- 0 until MAX_VLMUL / 4) { 229 csBundle(4 * i).lsrc(1) := src2 + i.U 230 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 231 csBundle(4 * i).ldest := dest + (4 * i).U 232 csBundle(4 * i).uopIdx := (4 * i).U 233 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 234 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 235 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 236 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 237 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 238 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 239 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 240 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 241 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 242 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 243 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 244 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 245 } 246 } 247 is(UopSplitType.VEC_EXT8) { 248 for (i <- 0 until MAX_VLMUL) { 249 csBundle(i).lsrc(1) := src2 250 csBundle(i).lsrc(2) := dest + i.U 251 csBundle(i).ldest := dest + i.U 252 csBundle(i).uopIdx := i.U 253 } 254 } 255 is(UopSplitType.VEC_0XV) { 256 /* 257 FMV.D.X 258 */ 259 csBundle(0).srcType(0) := SrcType.reg 260 csBundle(0).srcType(1) := SrcType.imm 261 csBundle(0).lsrc(1) := 0.U 262 csBundle(0).ldest := FP_TMP_REG_MV.U 263 csBundle(0).fuType := FuType.i2f.U 264 csBundle(0).rfWen := false.B 265 csBundle(0).fpWen := true.B 266 csBundle(0).vecWen := false.B 267 csBundle(0).fpu.isAddSub := false.B 268 csBundle(0).fpu.typeTagIn := FPU.D 269 csBundle(0).fpu.typeTagOut := FPU.D 270 csBundle(0).fpu.fromInt := true.B 271 csBundle(0).fpu.wflags := false.B 272 csBundle(0).fpu.fpWen := true.B 273 csBundle(0).fpu.div := false.B 274 csBundle(0).fpu.sqrt := false.B 275 csBundle(0).fpu.fcvt := false.B 276 /* 277 vfmv.s.f 278 */ 279 csBundle(1).srcType(0) := SrcType.fp 280 csBundle(1).srcType(1) := SrcType.vp 281 csBundle(1).srcType(2) := SrcType.vp 282 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 283 csBundle(1).lsrc(1) := 0.U 284 csBundle(1).lsrc(2) := dest 285 csBundle(1).ldest := dest 286 csBundle(1).fuType := FuType.vppu.U 287 csBundle(1).fuOpType := VpermType.dummy 288 csBundle(1).rfWen := false.B 289 csBundle(1).fpWen := false.B 290 csBundle(1).vecWen := true.B 291 } 292 is(UopSplitType.VEC_VXV) { 293 /* 294 FMV.D.X 295 */ 296 csBundle(0).srcType(0) := SrcType.reg 297 csBundle(0).srcType(1) := SrcType.imm 298 csBundle(0).lsrc(1) := 0.U 299 csBundle(0).ldest := FP_TMP_REG_MV.U 300 csBundle(0).fuType := FuType.i2f.U 301 csBundle(0).rfWen := false.B 302 csBundle(0).fpWen := true.B 303 csBundle(0).vecWen := false.B 304 csBundle(0).fpu.isAddSub := false.B 305 csBundle(0).fpu.typeTagIn := FPU.D 306 csBundle(0).fpu.typeTagOut := FPU.D 307 csBundle(0).fpu.fromInt := true.B 308 csBundle(0).fpu.wflags := false.B 309 csBundle(0).fpu.fpWen := true.B 310 csBundle(0).fpu.div := false.B 311 csBundle(0).fpu.sqrt := false.B 312 csBundle(0).fpu.fcvt := false.B 313 /* 314 LMUL 315 */ 316 for (i <- 0 until MAX_VLMUL) { 317 csBundle(i + 1).srcType(0) := SrcType.fp 318 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 319 csBundle(i + 1).lsrc(1) := src2 + i.U 320 csBundle(i + 1).lsrc(2) := dest + i.U 321 csBundle(i + 1).ldest := dest + i.U 322 csBundle(i + 1).uopIdx := i.U 323 } 324 } 325 is(UopSplitType.VEC_VVW) { 326 for (i <- 0 until MAX_VLMUL / 2) { 327 csBundle(2 * i).lsrc(0) := src1 + i.U 328 csBundle(2 * i).lsrc(1) := src2 + i.U 329 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 330 csBundle(2 * i).ldest := dest + (2 * i).U 331 csBundle(2 * i).uopIdx := (2 * i).U 332 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 333 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 334 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 335 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 336 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 337 } 338 } 339 is(UopSplitType.VEC_WVW) { 340 for (i <- 0 until MAX_VLMUL / 2) { 341 csBundle(2 * i).lsrc(0) := src1 + i.U 342 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 343 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 344 csBundle(2 * i).ldest := dest + (2 * i).U 345 csBundle(2 * i).uopIdx := (2 * i).U 346 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 347 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 348 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 349 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 350 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 351 } 352 } 353 is(UopSplitType.VEC_VXW) { 354 /* 355 FMV.D.X 356 */ 357 csBundle(0).srcType(0) := SrcType.reg 358 csBundle(0).srcType(1) := SrcType.imm 359 csBundle(0).lsrc(1) := 0.U 360 csBundle(0).ldest := FP_TMP_REG_MV.U 361 csBundle(0).fuType := FuType.i2f.U 362 csBundle(0).rfWen := false.B 363 csBundle(0).fpWen := true.B 364 csBundle(0).vecWen := false.B 365 csBundle(0).fpu.isAddSub := false.B 366 csBundle(0).fpu.typeTagIn := FPU.D 367 csBundle(0).fpu.typeTagOut := FPU.D 368 csBundle(0).fpu.fromInt := true.B 369 csBundle(0).fpu.wflags := false.B 370 csBundle(0).fpu.fpWen := true.B 371 csBundle(0).fpu.div := false.B 372 csBundle(0).fpu.sqrt := false.B 373 csBundle(0).fpu.fcvt := false.B 374 375 for (i <- 0 until MAX_VLMUL / 2) { 376 csBundle(2 * i + 1).srcType(0) := SrcType.fp 377 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 378 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 379 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 380 csBundle(2 * i + 1).ldest := dest + (2 * i).U 381 csBundle(2 * i + 1).uopIdx := (2 * i).U 382 csBundle(2 * i + 2).srcType(0) := SrcType.fp 383 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 384 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 385 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 386 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 387 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 388 } 389 } 390 is(UopSplitType.VEC_WXW) { 391 /* 392 FMV.D.X 393 */ 394 csBundle(0).srcType(0) := SrcType.reg 395 csBundle(0).srcType(1) := SrcType.imm 396 csBundle(0).lsrc(1) := 0.U 397 csBundle(0).ldest := FP_TMP_REG_MV.U 398 csBundle(0).fuType := FuType.i2f.U 399 csBundle(0).rfWen := false.B 400 csBundle(0).fpWen := true.B 401 csBundle(0).vecWen := false.B 402 csBundle(0).fpu.isAddSub := false.B 403 csBundle(0).fpu.typeTagIn := FPU.D 404 csBundle(0).fpu.typeTagOut := FPU.D 405 csBundle(0).fpu.fromInt := true.B 406 csBundle(0).fpu.wflags := false.B 407 csBundle(0).fpu.fpWen := true.B 408 csBundle(0).fpu.div := false.B 409 csBundle(0).fpu.sqrt := false.B 410 csBundle(0).fpu.fcvt := false.B 411 412 for (i <- 0 until MAX_VLMUL / 2) { 413 csBundle(2 * i + 1).srcType(0) := SrcType.fp 414 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 415 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 416 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 417 csBundle(2 * i + 1).ldest := dest + (2 * i).U 418 csBundle(2 * i + 1).uopIdx := (2 * i).U 419 csBundle(2 * i + 2).srcType(0) := SrcType.fp 420 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 421 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 422 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 423 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 424 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 425 } 426 } 427 is(UopSplitType.VEC_WVV) { 428 for (i <- 0 until MAX_VLMUL / 2) { 429 430 csBundle(2 * i).lsrc(0) := src1 + i.U 431 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 432 csBundle(2 * i).lsrc(2) := dest + i.U 433 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 434 csBundle(2 * i).uopIdx := (2 * i).U 435 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 436 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 437 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 438 csBundle(2 * i + 1).ldest := dest + i.U 439 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 440 } 441 } 442 is(UopSplitType.VEC_WXV) { 443 /* 444 FMV.D.X 445 */ 446 csBundle(0).srcType(0) := SrcType.reg 447 csBundle(0).srcType(1) := SrcType.imm 448 csBundle(0).lsrc(1) := 0.U 449 csBundle(0).ldest := FP_TMP_REG_MV.U 450 csBundle(0).fuType := FuType.i2f.U 451 csBundle(0).rfWen := false.B 452 csBundle(0).fpWen := true.B 453 csBundle(0).vecWen := false.B 454 csBundle(0).fpu.isAddSub := false.B 455 csBundle(0).fpu.typeTagIn := FPU.D 456 csBundle(0).fpu.typeTagOut := FPU.D 457 csBundle(0).fpu.fromInt := true.B 458 csBundle(0).fpu.wflags := false.B 459 csBundle(0).fpu.fpWen := true.B 460 csBundle(0).fpu.div := false.B 461 csBundle(0).fpu.sqrt := false.B 462 csBundle(0).fpu.fcvt := false.B 463 464 for (i <- 0 until MAX_VLMUL / 2) { 465 csBundle(2 * i + 1).srcType(0) := SrcType.fp 466 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 467 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 468 csBundle(2 * i + 1).lsrc(2) := dest + i.U 469 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 470 csBundle(2 * i + 1).uopIdx := (2 * i).U 471 csBundle(2 * i + 2).srcType(0) := SrcType.fp 472 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 473 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 474 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 475 csBundle(2 * i + 2).ldest := dest + i.U 476 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 477 } 478 } 479 is(UopSplitType.VEC_VVM) { 480 csBundle(0).lsrc(2) := dest 481 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 482 csBundle(0).uopIdx := 0.U 483 for(i <- 1 until MAX_VLMUL) { 484 csBundle(i).lsrc(0) := src1 + i.U 485 csBundle(i).lsrc(1) := src2 + i.U 486 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 487 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 488 csBundle(i).uopIdx := i.U 489 } 490 csBundle(numOfUop - 1.U).ldest := dest 491 } 492 is(UopSplitType.VEC_VXM) { 493 /* 494 FMV.D.X 495 */ 496 csBundle(0).srcType(0) := SrcType.reg 497 csBundle(0).srcType(1) := SrcType.imm 498 csBundle(0).lsrc(1) := 0.U 499 csBundle(0).ldest := FP_TMP_REG_MV.U 500 csBundle(0).fuType := FuType.i2f.U 501 csBundle(0).rfWen := false.B 502 csBundle(0).fpWen := true.B 503 csBundle(0).vecWen := false.B 504 csBundle(0).fpu.isAddSub := false.B 505 csBundle(0).fpu.typeTagIn := FPU.D 506 csBundle(0).fpu.typeTagOut := FPU.D 507 csBundle(0).fpu.fromInt := true.B 508 csBundle(0).fpu.wflags := false.B 509 csBundle(0).fpu.fpWen := true.B 510 csBundle(0).fpu.div := false.B 511 csBundle(0).fpu.sqrt := false.B 512 csBundle(0).fpu.fcvt := false.B 513 //LMUL 514 csBundle(1).srcType(0) := SrcType.fp 515 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 516 csBundle(1).lsrc(2) := dest 517 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 518 csBundle(1).uopIdx := 0.U 519 for (i <- 1 until MAX_VLMUL) { 520 csBundle(i + 1).srcType(0) := SrcType.fp 521 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 522 csBundle(i + 1).lsrc(1) := src2 + i.U 523 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 524 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 525 csBundle(i + 1).uopIdx := i.U 526 } 527 csBundle(numOfUop - 1.U).ldest := dest 528 } 529 is(UopSplitType.VEC_SLIDE1UP) { 530 /* 531 FMV.D.X 532 */ 533 csBundle(0).srcType(0) := SrcType.reg 534 csBundle(0).srcType(1) := SrcType.imm 535 csBundle(0).lsrc(1) := 0.U 536 csBundle(0).ldest := FP_TMP_REG_MV.U 537 csBundle(0).fuType := FuType.i2f.U 538 csBundle(0).rfWen := false.B 539 csBundle(0).fpWen := true.B 540 csBundle(0).vecWen := false.B 541 csBundle(0).fpu.isAddSub := false.B 542 csBundle(0).fpu.typeTagIn := FPU.D 543 csBundle(0).fpu.typeTagOut := FPU.D 544 csBundle(0).fpu.fromInt := true.B 545 csBundle(0).fpu.wflags := false.B 546 csBundle(0).fpu.fpWen := true.B 547 csBundle(0).fpu.div := false.B 548 csBundle(0).fpu.sqrt := false.B 549 csBundle(0).fpu.fcvt := false.B 550 //LMUL 551 csBundle(1).srcType(0) := SrcType.fp 552 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 553 csBundle(1).lsrc(2) := dest 554 csBundle(1).ldest := dest 555 csBundle(1).uopIdx := 0.U 556 for (i <- 1 until MAX_VLMUL) { 557 csBundle(i + 1).srcType(0) := SrcType.vp 558 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 559 csBundle(i + 1).lsrc(1) := src2 + i.U 560 csBundle(i + 1).lsrc(2) := dest + i.U 561 csBundle(i + 1).ldest := dest + i.U 562 csBundle(i + 1).uopIdx := i.U 563 } 564 } 565 is(UopSplitType.VEC_FSLIDE1UP) { 566 //LMUL 567 csBundle(0).srcType(0) := SrcType.fp 568 csBundle(0).lsrc(0) := src1 569 csBundle(0).lsrc(1) := src2 570 csBundle(0).lsrc(2) := dest 571 csBundle(0).ldest := dest 572 csBundle(0).uopIdx := 0.U 573 for (i <- 1 until MAX_VLMUL) { 574 csBundle(i).srcType(0) := SrcType.vp 575 csBundle(i).lsrc(0) := src2 + (i - 1).U 576 csBundle(i).lsrc(1) := src2 + i.U 577 csBundle(i).lsrc(2) := dest + i.U 578 csBundle(i).ldest := dest + i.U 579 csBundle(i).uopIdx := i.U 580 } 581 } 582 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 583 /* 584 FMV.D.X 585 */ 586 csBundle(0).srcType(0) := SrcType.reg 587 csBundle(0).srcType(1) := SrcType.imm 588 csBundle(0).lsrc(1) := 0.U 589 csBundle(0).ldest := FP_TMP_REG_MV.U 590 csBundle(0).fuType := FuType.i2f.U 591 csBundle(0).rfWen := false.B 592 csBundle(0).fpWen := true.B 593 csBundle(0).vecWen := false.B 594 csBundle(0).fpu.isAddSub := false.B 595 csBundle(0).fpu.typeTagIn := FPU.D 596 csBundle(0).fpu.typeTagOut := FPU.D 597 csBundle(0).fpu.fromInt := true.B 598 csBundle(0).fpu.wflags := false.B 599 csBundle(0).fpu.fpWen := true.B 600 csBundle(0).fpu.div := false.B 601 csBundle(0).fpu.sqrt := false.B 602 csBundle(0).fpu.fcvt := false.B 603 //LMUL 604 for (i <- 0 until MAX_VLMUL) { 605 csBundle(2 * i + 1).srcType(0) := SrcType.vp 606 csBundle(2 * i + 1).srcType(1) := SrcType.vp 607 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 608 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 609 csBundle(2 * i + 1).lsrc(2) := dest + i.U 610 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 611 csBundle(2 * i + 1).uopIdx := (2 * i).U 612 if (2 * i + 2 < MAX_VLMUL * 2 ){ 613 csBundle(2 * i + 2).srcType(0) := SrcType.fp 614 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 615 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 616 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 617 csBundle(2 * i + 2).ldest := dest + i.U 618 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 619 } 620 } 621 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 622 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 623 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 624 } 625 is(UopSplitType.VEC_FSLIDE1DOWN) { 626 //LMUL 627 for (i <- 0 until MAX_VLMUL) { 628 csBundle(2 * i).srcType(0) := SrcType.vp 629 csBundle(2 * i).srcType(1) := SrcType.vp 630 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 631 csBundle(2 * i).lsrc(1) := src2 + i.U 632 csBundle(2 * i).lsrc(2) := dest + i.U 633 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 634 csBundle(2 * i).uopIdx := (2 * i).U 635 csBundle(2 * i + 1).srcType(0) := SrcType.fp 636 csBundle(2 * i + 1).lsrc(0) := src1 637 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 638 csBundle(2 * i + 1).ldest := dest + i.U 639 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 640 } 641 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 642 csBundle(numOfUop - 1.U).lsrc(0) := src1 643 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 644 } 645 is(UopSplitType.VEC_VRED) { 646 when(simple.io.enq.vtype.vlmul === "b001".U){ 647 csBundle(0).srcType(2) := SrcType.DC 648 csBundle(0).lsrc(0) := src2 + 1.U 649 csBundle(0).lsrc(1) := src2 650 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 651 csBundle(0).uopIdx := 0.U 652 } 653 when(simple.io.enq.vtype.vlmul === "b010".U) { 654 csBundle(0).srcType(2) := SrcType.DC 655 csBundle(0).lsrc(0) := src2 + 1.U 656 csBundle(0).lsrc(1) := src2 657 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 658 csBundle(0).uopIdx := 0.U 659 660 csBundle(1).srcType(2) := SrcType.DC 661 csBundle(1).lsrc(0) := src2 + 3.U 662 csBundle(1).lsrc(1) := src2 + 2.U 663 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 664 csBundle(1).uopIdx := 1.U 665 666 csBundle(2).srcType(2) := SrcType.DC 667 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 668 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 669 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 670 csBundle(2).uopIdx := 2.U 671 } 672 when(simple.io.enq.vtype.vlmul === "b011".U) { 673 for(i <- 0 until MAX_VLMUL){ 674 if(i < MAX_VLMUL - MAX_VLMUL/2){ 675 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 676 csBundle(i).lsrc(1) := src2 + (i * 2).U 677 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 678 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 679 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 680 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 681 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 682 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 683 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 684 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 685 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 686 } 687 csBundle(i).srcType(2) := SrcType.DC 688 csBundle(i).uopIdx := i.U 689 } 690 } 691 when (simple.io.enq.vtype.vlmul.orR()){ 692 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 693 csBundle(numOfUop - 1.U).lsrc(0) := src1 694 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 695 csBundle(numOfUop - 1.U).lsrc(2) := dest 696 csBundle(numOfUop - 1.U).ldest := dest 697 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 698 } 699 } 700 701 is(UopSplitType.VEC_SLIDEUP) { 702 // FMV.D.X 703 csBundle(0).srcType(0) := SrcType.reg 704 csBundle(0).srcType(1) := SrcType.imm 705 csBundle(0).lsrc(1) := 0.U 706 csBundle(0).ldest := FP_TMP_REG_MV.U 707 csBundle(0).fuType := FuType.i2f.U 708 csBundle(0).rfWen := false.B 709 csBundle(0).fpWen := true.B 710 csBundle(0).vecWen := false.B 711 csBundle(0).fpu.isAddSub := false.B 712 csBundle(0).fpu.typeTagIn := FPU.D 713 csBundle(0).fpu.typeTagOut := FPU.D 714 csBundle(0).fpu.fromInt := true.B 715 csBundle(0).fpu.wflags := false.B 716 csBundle(0).fpu.fpWen := true.B 717 csBundle(0).fpu.div := false.B 718 csBundle(0).fpu.sqrt := false.B 719 csBundle(0).fpu.fcvt := false.B 720 // LMUL 721 for(i <- 0 until MAX_VLMUL) 722 for(j <- 0 to i){ 723 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 724 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 725 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 726 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 727 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 728 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 729 csBundle(i*(i+1)/2+j+1).ldest := vd 730 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 731 } 732 } 733 734 is(UopSplitType.VEC_ISLIDEUP) { 735 // LMUL 736 for(i <- 0 until MAX_VLMUL) 737 for(j <- 0 to i){ 738 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 739 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 740 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 741 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 742 csBundle(i*(i+1)/2+j).ldest := vd 743 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 744 } 745 } 746 747 is(UopSplitType.VEC_SLIDEDOWN) { 748 // FMV.D.X 749 csBundle(0).srcType(0) := SrcType.reg 750 csBundle(0).srcType(1) := SrcType.imm 751 csBundle(0).lsrc(1) := 0.U 752 csBundle(0).ldest := FP_TMP_REG_MV.U 753 csBundle(0).fuType := FuType.i2f.U 754 csBundle(0).rfWen := false.B 755 csBundle(0).fpWen := true.B 756 csBundle(0).vecWen := false.B 757 csBundle(0).fpu.isAddSub := false.B 758 csBundle(0).fpu.typeTagIn := FPU.D 759 csBundle(0).fpu.typeTagOut := FPU.D 760 csBundle(0).fpu.fromInt := true.B 761 csBundle(0).fpu.wflags := false.B 762 csBundle(0).fpu.fpWen := true.B 763 csBundle(0).fpu.div := false.B 764 csBundle(0).fpu.sqrt := false.B 765 csBundle(0).fpu.fcvt := false.B 766 // LMUL 767 for(i <- 0 until MAX_VLMUL) 768 for(j <- (0 to i).reverse){ 769 when(i.U < lmul){ 770 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 771 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 772 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 773 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 774 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 775 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 776 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 777 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 778 } 779 } 780 } 781 782 is(UopSplitType.VEC_ISLIDEDOWN) { 783 // LMUL 784 for(i <- 0 until MAX_VLMUL) 785 for(j <- (0 to i).reverse){ 786 when(i.U < lmul){ 787 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 788 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 789 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 790 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 791 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 792 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 793 } 794 } 795 } 796 797 is(UopSplitType.VEC_M0X) { 798 // LMUL 799 for (i <- 0 until MAX_VLMUL) { 800 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 801 val ldest = (VECTOR_TMP_REG_LMUL + i).U 802 csBundle(i).srcType(0) := srcType0 803 csBundle(i).srcType(1) := SrcType.vp 804 csBundle(i).rfWen := false.B 805 csBundle(i).vecWen := true.B 806 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 807 csBundle(i).lsrc(1) := src2 808 // csBundle(i).lsrc(2) := dest + i.U DontCare 809 csBundle(i).ldest := ldest 810 csBundle(i).uopIdx := i.U 811 } 812 csBundle(lmul-1.U).vecWen := false.B 813 csBundle(lmul-1.U).fpWen := true.B 814 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 815 // FMV_X_D 816 csBundle(lmul).srcType(0) := SrcType.fp 817 csBundle(lmul).srcType(1) := SrcType.imm 818 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 819 csBundle(lmul).lsrc(1) := 0.U 820 csBundle(lmul).ldest := dest 821 csBundle(lmul).fuType := FuType.fmisc.U 822 csBundle(lmul).rfWen := true.B 823 csBundle(lmul).fpWen := false.B 824 csBundle(lmul).vecWen := false.B 825 csBundle(lmul).fpu.isAddSub := false.B 826 csBundle(lmul).fpu.typeTagIn := FPU.D 827 csBundle(lmul).fpu.typeTagOut := FPU.D 828 csBundle(lmul).fpu.fromInt := false.B 829 csBundle(lmul).fpu.wflags := false.B 830 csBundle(lmul).fpu.fpWen := false.B 831 csBundle(lmul).fpu.div := false.B 832 csBundle(lmul).fpu.sqrt := false.B 833 csBundle(lmul).fpu.fcvt := false.B 834 } 835 836 is(UopSplitType.VEC_MVV) { 837 // LMUL 838 for (i <- 0 until MAX_VLMUL) { 839 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 840 csBundle(i*2+0).srcType(0) := srcType0 841 csBundle(i*2+0).srcType(1) := SrcType.vp 842 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 843 csBundle(i*2+0).lsrc(1) := src2 844 csBundle(i*2+0).lsrc(2) := dest + i.U 845 csBundle(i*2+0).ldest := dest + i.U 846 csBundle(i*2+0).uopIdx := (i*2+0).U 847 848 csBundle(i*2+1).srcType(0) := srcType0 849 csBundle(i*2+1).srcType(1) := SrcType.vp 850 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 851 csBundle(i*2+1).lsrc(1) := src2 852 // csBundle(i).lsrc(2) := dest + i.U DontCare 853 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 854 csBundle(i*2+1).uopIdx := (i*2+1).U 855 } 856 } 857 858 is(UopSplitType.VEC_M0X_VFIRST) { 859 // LMUL 860 csBundle(0).rfWen := false.B 861 csBundle(0).fpWen := true.B 862 csBundle(0).ldest := FP_TMP_REG_MV.U 863 // FMV_X_D 864 csBundle(1).srcType(0) := SrcType.fp 865 csBundle(1).srcType(1) := SrcType.imm 866 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 867 csBundle(1).lsrc(1) := 0.U 868 csBundle(1).ldest := dest 869 csBundle(1).fuType := FuType.fmisc.U 870 csBundle(1).rfWen := true.B 871 csBundle(1).fpWen := false.B 872 csBundle(1).vecWen := false.B 873 csBundle(1).fpu.isAddSub := false.B 874 csBundle(1).fpu.typeTagIn := FPU.D 875 csBundle(1).fpu.typeTagOut := FPU.D 876 csBundle(1).fpu.fromInt := false.B 877 csBundle(1).fpu.wflags := false.B 878 csBundle(1).fpu.fpWen := false.B 879 csBundle(1).fpu.div := false.B 880 csBundle(1).fpu.sqrt := false.B 881 csBundle(1).fpu.fcvt := false.B 882 } 883 } 884 885 //uops dispatch 886 val normal :: ext :: Nil = Enum(2) 887 val stateReg = RegInit(normal) 888 val uopRes = RegInit(0.U) 889 890 //readyFromRename Counter 891 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 892 893 switch(stateReg) { 894 is(normal) { 895 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 896 } 897 is(ext) { 898 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 899 } 900 } 901 902 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 903 val uopResJudge = Mux(stateReg === normal, 904 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 905 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 906 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 907 908 for(i <- 0 until RenameWidth) { 909 decodedInsts(i) := MuxCase(csBundle(i), Seq( 910 (stateReg === normal) -> csBundle(i), 911 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 912 )) 913 } 914 915 916 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 917 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 918 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 919 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 920 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 921 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 922 notInfVec(0) := true.B 923 924 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 925 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 926 1.U) 927 validToRename.zipWithIndex.foreach{ 928 case(dst, i) => 929 dst := MuxCase(false.B, Seq( 930 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 931 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 932 )) 933 } 934 935 readyToIBuf.zipWithIndex.foreach { 936 case (dst, i) => 937 dst := MuxCase(true.B, Seq( 938 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 939 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 940 )) 941 } 942 943 io.deq.decodedInsts := decodedInsts 944 io.deq.isVset := isVset_u 945 io.deq.complexNum := complexNum 946 io.deq.validToRename := validToRename 947 io.deq.readyToIBuf := readyToIBuf 948 949} 950