1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.DelayN 8import utils._ 9import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 10import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 11import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 12import xiangshan.backend.datapath.WbConfig.{PregWB, _} 13 14class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 15 val flush = Flipped(ValidIO(new Redirect())) 16 val in = Flipped(DecoupledIO(new ExuInput(params))) 17 val out = DecoupledIO(new ExuOutput(params)) 18 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 19 val fenceio = if (params.hasFence) Some(new FenceIO) else None 20 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 21} 22 23class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 24 lazy val module = new ExeUnitImp(this)(p, exuParams) 25} 26 27class ExeUnitImp( 28 override val wrapper: ExeUnit 29)(implicit 30 p: Parameters, exuParams: ExeUnitParams 31) extends LazyModuleImp(wrapper) with HasXSParameter{ 32 private val fuCfgs = exuParams.fuConfigs 33 34 val io = IO(new ExeUnitIO(exuParams)) 35 36 val funcUnits = fuCfgs.map(cfg => { 37 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 38 val module = cfg.fuGen(p, cfg) 39 module 40 }) 41 42 val busy = RegInit(false.B) 43 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 44 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 45 busy := false.B 46 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 47 busy := false.B 48 }.elsewhen(io.out.fire) { 49 busy := false.B 50 }.elsewhen(io.in.fire) { 51 busy := true.B 52 } 53 54 if (exuParams.latencyCertain){ 55 busy := false.B 56 } 57 58 exuParams.wbPortConfigs.map{ 59 x => x match { 60 case IntWB(port, priority) => assert((priority == 0) || (priority == 1), 61 s"${exuParams.name}: WbPort must priority=0 or priority=1") 62 case VfWB (port, priority) => assert((priority == 0) || (priority == 1), 63 s"${exuParams.name}: WbPort must priority=0 or priority=1") 64 case _ => 65 } 66 } 67 val intWbPort = exuParams.getIntWBPort 68 if (intWbPort.isDefined){ 69 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 70 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 71 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 72 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 73 samePort.wbPortConfigs.map( 74 x => x match { 75 case IntWB(port, priority) => { 76 if (!samePort.latencyCertain) assert(priority == 1, 77 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 78 else assert(priority == 0, 79 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 80 } 81 case _ => 82 } 83 ) 84 ) 85 } 86 val vfWbPort = exuParams.getVfWBPort 87 if (vfWbPort.isDefined) { 88 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 89 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 90 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 91 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 92 samePort.wbPortConfigs.map( 93 x => x match { 94 case VfWB(port, priority) => { 95 if (!samePort.latencyCertain) assert(priority == 1, 96 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 97 else assert(priority == 0, 98 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=1") 99 } 100 case _ => 101 } 102 ) 103 ) 104 } 105 dontTouch(io.out.ready) 106 // rob flush --> funcUnits 107 funcUnits.zipWithIndex.foreach { case (fu, i) => 108 fu.io.flush <> io.flush 109 } 110 111 def acceptCond(input: ExuInput): Seq[Bool] = { 112 input.params.fuConfigs.map(_.fuSel(input)) 113 } 114 115 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 116 117 // ExeUnit.in <---> Dispatcher.in 118 in1ToN.io.in.valid := io.in.valid && !busy 119 in1ToN.io.in.bits := io.in.bits 120 io.in.ready := !busy && in1ToN.io.in.ready 121 122 // Dispatcher.out <---> FunctionUnits 123 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 124 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 125 sink.valid := source.valid 126 source.ready := sink.ready 127 128 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 129 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 130 sink.bits.data.imm := source.bits.imm 131 sink.bits.ctrl.fuOpType := source.bits.fuOpType 132 sink.bits.ctrl.robIdx := source.bits.robIdx 133 sink.bits.ctrl.pdest := source.bits.pdest 134 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 135 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 136 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 137 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 138 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 139 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 140 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 141 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 142 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 143 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 144 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 145 } 146 147 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 148 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 149 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 150 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 151 152 // Assume that one fu can only write int or fp or vec, 153 // otherwise, wenVec should be assigned to wen in fu. 154 private val fuIntWenVec = funcUnits.map(x => x.cfg.writeIntRf.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 155 private val fuFpWenVec = funcUnits.map(x => x.cfg.writeFpRf.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 156 private val fuVecWenVec = funcUnits.map(x => x.cfg.writeVecRf.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 157 // FunctionUnits <---> ExeUnit.out 158 io.out.valid := Cat(fuOutValidOH).orR 159 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 160 161 // select one fu's result 162 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 163 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 164 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 165 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 166 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 167 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 168 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 169 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 170 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 171 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 172 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 173 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 174 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 175 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 176 177 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 178 fuio => 179 exuio <> fuio 180 fuio.exception := DelayN(exuio.exception, 2) 181 })) 182 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 183 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 184 185 // debug info 186 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 187 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 188 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 189} 190 191class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 192 val in = Flipped(DecoupledIO(gen)) 193 194 val out = Vec(n, DecoupledIO(gen)) 195} 196 197class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 198 (implicit p: Parameters) 199 extends Module { 200 201 val io = IO(new DispatcherIO(gen, n)) 202 203 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 204 205 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 206 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 207 208 io.out.zipWithIndex.foreach { case (out, i) => 209 out.valid := acceptVec(i) && io.in.valid 210 out.bits := io.in.bits 211 } 212 213 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 214} 215 216class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 217 val flush = Flipped(ValidIO(new Redirect())) 218 val in = Flipped(DecoupledIO(new MemExuInput())) 219 val out = DecoupledIO(new MemExuOutput()) 220} 221 222class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 223 val io = IO(new MemExeUnitIO) 224 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 225 fu.io.flush := io.flush 226 fu.io.in.valid := io.in.valid 227 io.in.ready := fu.io.in.ready 228 229 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 230 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 231 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 232 fu.io.in.bits.data.imm := io.in.bits.uop.imm 233 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 234 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 235 236 io.out.valid := fu.io.out.valid 237 fu.io.out.ready := io.out.ready 238 239 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 240 io.out.bits.data := fu.io.out.bits.res.data 241 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 242 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 243 io.out.bits.uop.fuType := io.in.bits.uop.fuType 244 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 245 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 246 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 247 248 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 249} 250