1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31 32class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 33 val flush = Flipped(ValidIO(new Redirect())) 34 val in = Flipped(DecoupledIO(new ExuInput(params))) 35 val out = DecoupledIO(new ExuOutput(params)) 36 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 37 val fenceio = if (params.hasFence) Some(new FenceIO) else None 38 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 39 val vxrm = if (params.needSrcVxrm) Some(Input(UInt(2.W))) else None 40 val vlIsZero = OptionWrapper(params.writeVConfig, Output(Bool())) 41 val vlIsVlmax = OptionWrapper(params.writeVConfig, Output(Bool())) 42} 43 44class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 45 override def shouldBeInlined: Boolean = false 46 47 lazy val module = new ExeUnitImp(this)(p, exuParams) 48} 49 50class ExeUnitImp( 51 override val wrapper: ExeUnit 52)(implicit 53 p: Parameters, exuParams: ExeUnitParams 54) extends LazyModuleImp(wrapper) with HasXSParameter{ 55 private val fuCfgs = exuParams.fuConfigs 56 57 val io = IO(new ExeUnitIO(exuParams)) 58 59 val funcUnits = fuCfgs.map(cfg => { 60 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 61 val module = cfg.fuGen(p, cfg) 62 module 63 }) 64 65 if (EnableClockGate) { 66 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 67 val clk_en = WireInit(false.B) 68 val fuVld_en = WireInit(false.B) 69 val fuVld_en_reg = RegInit(false.B) 70 val uncer_en_reg = RegInit(false.B) 71 72 val lat0 = FuType.isLat0(io.in.bits.fuType) 73 val latN = FuType.isLatN(io.in.bits.fuType) 74 val uncerLat = FuType.isUncerLat(io.in.bits.fuType) 75 76 def lat: Int = cfg.latency.latencyVal.getOrElse(0) 77 78 val fuVldVec = (io.in.valid && latN) +: Seq.fill(lat)(RegInit(false.B)) 79 val fuRdyVec = Seq.fill(lat)(Wire(Bool())) :+ io.out.ready 80 81 for (i <- 0 until lat) { 82 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 83 } 84 85 for (i <- 1 to lat) { 86 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 87 fuVldVec(i) := fuVldVec(i - 1) 88 }.elsewhen(fuRdyVec(i)) { 89 fuVldVec(i) := false.B 90 } 91 } 92 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 93 fuVld_en_reg := fuVld_en 94 95 when(uncerLat && io.in.fire) { 96 uncer_en_reg := true.B 97 }.elsewhen(uncerLat && io.out.fire) { 98 uncer_en_reg := false.B 99 } 100 101 when(lat0 && io.in.fire) { 102 clk_en := true.B 103 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 104 clk_en := true.B 105 }.elsewhen(uncerLat && io.in.fire || uncer_en_reg) { 106 clk_en := true.B 107 } 108 109 if (cfg.ckAlwaysEn) { 110 clk_en := true.B 111 } 112 113 val clk_gate = Module(new ClockGate) 114 clk_gate.io.TE := false.B 115 clk_gate.io.E := clk_en 116 clk_gate.io.CK := clock 117 fu.clock := clk_gate.io.Q 118 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 119 } 120 } 121 122 val busy = RegInit(false.B) 123 if (exuParams.latencyCertain){ 124 busy := false.B 125 } 126 else { 127 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 128 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 129 busy := false.B 130 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 131 busy := false.B 132 }.elsewhen(io.out.fire) { 133 busy := false.B 134 }.elsewhen(io.in.fire) { 135 busy := true.B 136 } 137 } 138 139 exuParams.wbPortConfigs.map{ 140 x => x match { 141 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 142 s"${exuParams.name}: WbPort must priority=0 or priority=1") 143 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 144 s"${exuParams.name}: WbPort must priority=0 or priority=1") 145 case _ => 146 } 147 } 148 val intWbPort = exuParams.getIntWBPort 149 if (intWbPort.isDefined){ 150 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 151 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 152 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 153 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 154 samePort.wbPortConfigs.map( 155 x => x match { 156 case IntWB(port, priority) => { 157 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 158 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 159 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 160 } 161 case _ => 162 } 163 ) 164 ) 165 } 166 val vfWbPort = exuParams.getVfWBPort 167 if (vfWbPort.isDefined) { 168 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 169 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 170 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 171 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 172 samePort.wbPortConfigs.map( 173 x => x match { 174 case VfWB(port, priority) => { 175 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 176 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 177 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 178 } 179 case _ => 180 } 181 ) 182 ) 183 } 184 if(backendParams.debugEn) { 185 dontTouch(io.out.ready) 186 } 187 // rob flush --> funcUnits 188 funcUnits.zipWithIndex.foreach { case (fu, i) => 189 fu.io.flush <> io.flush 190 } 191 192 def acceptCond(input: ExuInput): Seq[Bool] = { 193 input.params.fuConfigs.map(_.fuSel(input)) 194 } 195 196 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 197 198 // ExeUnit.in <---> Dispatcher.in 199 in1ToN.io.in.valid := io.in.valid && !busy 200 in1ToN.io.in.bits := io.in.bits 201 io.in.ready := !busy && in1ToN.io.in.ready 202 203 // Dispatcher.out <---> FunctionUnits 204 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 205 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 206 sink.valid := source.valid 207 source.ready := sink.ready 208 209 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 210 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 211 sink.bits.data.imm := source.bits.imm 212 sink.bits.ctrl.fuOpType := source.bits.fuOpType 213 sink.bits.ctrl.robIdx := source.bits.robIdx 214 sink.bits.ctrl.pdest := source.bits.pdest 215 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 216 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 217 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 218 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 219 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 220 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 221 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 222 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 223 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 224 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 225 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 226 } 227 228 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 229 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 230 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 231 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 232 233 // Assume that one fu can only write int or fp or vec, 234 // otherwise, wenVec should be assigned to wen in fu. 235 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 236 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 237 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 238 // FunctionUnits <---> ExeUnit.out 239 io.out.valid := Cat(fuOutValidOH).orR 240 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 241 242 // select one fu's result 243 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 244 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 245 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 246 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 247 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 248 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 249 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 250 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 251 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 252 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 253 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 254 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 255 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 256 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 257 258 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 259 fuio => 260 exuio <> fuio 261 fuio.exception := DelayN(exuio.exception, 2) 262 })) 263 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 264 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 265 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 266 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 267 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 268 269 // debug info 270 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 271 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 272 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 273} 274 275class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 276 val in = Flipped(DecoupledIO(gen)) 277 278 val out = Vec(n, DecoupledIO(gen)) 279} 280 281class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 282 (implicit p: Parameters) 283 extends Module { 284 285 val io = IO(new DispatcherIO(gen, n)) 286 287 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 288 289 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 290 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 291 292 io.out.zipWithIndex.foreach { case (out, i) => 293 out.valid := acceptVec(i) && io.in.valid 294 out.bits := io.in.bits 295 } 296 297 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 298} 299 300class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 301 val flush = Flipped(ValidIO(new Redirect())) 302 val in = Flipped(DecoupledIO(new MemExuInput())) 303 val out = DecoupledIO(new MemExuOutput()) 304} 305 306class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 307 val io = IO(new MemExeUnitIO) 308 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 309 fu.io.flush := io.flush 310 fu.io.in.valid := io.in.valid 311 io.in.ready := fu.io.in.ready 312 313 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 314 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 315 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 316 fu.io.in.bits.data.imm := io.in.bits.uop.imm 317 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 318 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 319 320 io.out.valid := fu.io.out.valid 321 fu.io.out.ready := io.out.ready 322 323 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 324 io.out.bits.data := fu.io.out.bits.res.data 325 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 326 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 327 io.out.bits.uop.fuType := io.in.bits.uop.fuType 328 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 329 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 330 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 331 332 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 333} 334