1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils._ 8import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 9import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 10import xiangshan.{Redirect, XSBundle, XSModule} 11 12class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 13 val flush = Flipped(ValidIO(new Redirect())) 14 val in = Flipped(DecoupledIO(new ExuInput(params))) 15 val out = DecoupledIO(new ExuOutput(params)) 16 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 17 val fenceio = if (params.hasFence) Some(new FenceIO) else None 18 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 19} 20 21class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 22 lazy val module = new ExeUnitImp(this)(p, exuParams) 23} 24 25class ExeUnitImp( 26 override val wrapper: ExeUnit 27)(implicit 28 p: Parameters, exuParams: ExeUnitParams 29) extends LazyModuleImp(wrapper) { 30 private val fuCfgs = exuParams.fuConfigs 31 32 val io = IO(new ExeUnitIO(exuParams)) 33 34 val funcUnits = fuCfgs.map(cfg => { 35 val module = cfg.fuGen(p, cfg) 36 module 37 }) 38 39 val busy = RegInit(false.B) 40 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 41 when (robIdx.needFlush(io.flush)) { 42 busy := false.B 43 }.elsewhen(io.out.fire) { 44 busy := false.B 45 }.elsewhen(io.in.fire) { 46 busy := true.B 47 } 48 49 // rob flush --> funcUnits 50 funcUnits.zipWithIndex.foreach { case (fu, i) => 51 fu.io.flush <> io.flush 52 } 53 54 def acceptCond(input: ExuInput): Seq[Bool] = { 55 input.params.fuConfigs.map(_.fuSel(input)) 56 } 57 58 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 59 60 // ExeUnit.in <---> Dispatcher.in 61 in1ToN.io.in.valid := io.in.valid && !busy 62 in1ToN.io.in.bits := io.in.bits 63 io.in.ready := !busy 64 65 // Dispatcher.out <---> FunctionUnits 66 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 67 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 68 sink.valid := source.valid 69 source.ready := sink.ready 70 71 sink.bits.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 72 sink.bits.fuOpType := source.bits.fuOpType 73 sink.bits.imm := source.bits.imm 74 sink.bits.robIdx := source.bits.robIdx 75 sink.bits.pdest := source.bits.pdest 76 sink.bits.rfWen .foreach(x => x := source.bits.rfWen.get) 77 sink.bits.fpWen .foreach(x => x := source.bits.fpWen.get) 78 sink.bits.vecWen .foreach(x => x := source.bits.vecWen.get) 79 sink.bits.fpu .foreach(x => x := source.bits.fpu.get) 80 sink.bits.flushPipe .foreach(x => x := source.bits.flushPipe.get) 81 sink.bits.pc .foreach(x => x := source.bits.pc.get) 82 sink.bits.preDecode .foreach(x => x := source.bits.preDecode.get) 83 sink.bits.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 84 sink.bits.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 85 sink.bits.predictInfo .foreach(x => x := source.bits.predictInfo.get) 86 } 87 88 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 89 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 90 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.redirect) 91 92 // Assume that one fu can only write int or fp or vec, 93 // otherwise, wenVec should be assigned to wen in fu. 94 private val fuIntWenVec = funcUnits.map(_.cfg.writeIntRf.B) 95 private val fuFpWenVec = funcUnits.map(_.cfg.writeFpRf.B) 96 private val fuVecWenVec = funcUnits.map(_.cfg.writeVecRf.B) 97 // FunctionUnits <---> ExeUnit.out 98 io.out.valid := Cat(fuOutValidOH).orR 99 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 100 101 // select one fu's result 102 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.data)) 103 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.robIdx)) 104 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.pdest)) 105 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 106 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 107 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 108 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 109 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 110 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 111 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 112 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 113 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 114 115 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach(fuio => exuio <> fuio))) 116 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 117 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 118 119 // debug info 120 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 121 io.out.bits.debugInfo := 0.U.asTypeOf(io.out.bits.debugInfo) 122} 123 124class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 125 val in = Flipped(DecoupledIO(gen)) 126 127 val out = Vec(n, DecoupledIO(gen)) 128} 129 130class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 131 (implicit p: Parameters) 132 extends Module { 133 134 val io = IO(new DispatcherIO(gen, n)) 135 136 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 137 138 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 139 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 140 141 io.out.zipWithIndex.foreach { case (out, i) => 142 out.valid := acceptVec(i) && io.in.valid && out.ready 143 out.bits := io.in.bits 144 } 145 146 io.in.ready := Cat(io.out.map(_.ready)).orR 147} 148 149class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 150 val flush = Flipped(ValidIO(new Redirect())) 151 val in = Flipped(DecoupledIO(new MemExuInput())) 152 val out = DecoupledIO(new MemExuOutput()) 153} 154 155class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 156 val io = IO(new MemExeUnitIO) 157 require(exuParams.fuConfigs.size == 1, "[MemExeUnit] only support one fu yet") 158 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 159 fu.io.flush := io.flush 160 fu.io.in.valid := io.in.valid 161 io.in.ready := fu.io.in.ready 162 163 fu.io.in.bits.robIdx := io.in.bits.uop.robIdx 164 fu.io.in.bits.pdest := io.in.bits.uop.pdest 165 fu.io.in.bits.fuOpType := io.in.bits.uop.fuOpType 166 fu.io.in.bits.imm := io.in.bits.uop.imm 167 fu.io.in.bits.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 168 169 io.out.valid := fu.io.out.valid 170 fu.io.out.ready := io.out.ready 171 172 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 173 io.out.bits.data := fu.io.out.bits.data 174 io.out.bits.uop.robIdx := fu.io.out.bits.robIdx 175 io.out.bits.uop.pdest := fu.io.out.bits.pdest 176 io.out.bits.uop.fuType := io.in.bits.uop.fuType 177 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 178 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 179 180 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 181} 182