1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.{ClockGate, DelayN} 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 32import xiangshan.backend.fu.fpu.Bundles.Frm 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrio = OptionWrapper(params.hasCSR, new CSRFileIO) 39 val fenceio = OptionWrapper(params.hasFence, new FenceIO) 40 val frm = OptionWrapper(params.needSrcFrm, Input(Frm())) 41 val vxrm = OptionWrapper(params.needSrcVxrm, Input(Vxrm())) 42 val vtype = OptionWrapper(params.writeVConfig, (Valid(new VType))) 43 val vlIsZero = OptionWrapper(params.writeVConfig, Output(Bool())) 44 val vlIsVlmax = OptionWrapper(params.writeVConfig, Output(Bool())) 45} 46 47class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 48 override def shouldBeInlined: Boolean = false 49 50 lazy val module = new ExeUnitImp(this)(p, exuParams) 51} 52 53class ExeUnitImp( 54 override val wrapper: ExeUnit 55)(implicit 56 p: Parameters, exuParams: ExeUnitParams 57) extends LazyModuleImp(wrapper) with HasXSParameter{ 58 private val fuCfgs = exuParams.fuConfigs 59 60 val io = IO(new ExeUnitIO(exuParams)) 61 62 val funcUnits = fuCfgs.map(cfg => { 63 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 64 val module = cfg.fuGen(p, cfg) 65 module 66 }) 67 68 if (EnableClockGate) { 69 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 70 val clk_en = WireInit(false.B) 71 val fuVld_en = WireInit(false.B) 72 val fuVld_en_reg = RegInit(false.B) 73 val uncer_en_reg = RegInit(false.B) 74 75 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 76 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 77 78 val uncerLat = cfg.latency.uncertainEnable.nonEmpty 79 val lat0 = (latReal == 0 && !uncerLat).asBool 80 val latN = (latReal > 0 && !uncerLat).asBool 81 82 val fuVldVec = (io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 83 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ io.out.ready 84 85 for (i <- 0 until latReal) { 86 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 87 } 88 89 for (i <- 1 to latReal) { 90 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 91 fuVldVec(i) := fuVldVec(i - 1) 92 }.elsewhen(fuRdyVec(i)) { 93 fuVldVec(i) := false.B 94 } 95 } 96 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 97 fuVld_en_reg := fuVld_en 98 99 when(uncerLat.asBool && io.in.fire) { 100 uncer_en_reg := true.B 101 }.elsewhen(uncerLat.asBool && io.out.fire) { 102 uncer_en_reg := false.B 103 } 104 105 when(lat0 && io.in.fire) { 106 clk_en := true.B 107 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 108 clk_en := true.B 109 }.elsewhen(uncerLat.asBool && io.in.fire || uncer_en_reg) { 110 clk_en := true.B 111 } 112 113 if (cfg.ckAlwaysEn) { 114 clk_en := true.B 115 } 116 117 fu.clock := ClockGate(false.B, clk_en, clock) 118 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 119 } 120 } 121 122 val busy = RegInit(false.B) 123 if (exuParams.latencyCertain){ 124 busy := false.B 125 } 126 else { 127 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 128 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 129 busy := false.B 130 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 131 busy := false.B 132 }.elsewhen(io.out.fire) { 133 busy := false.B 134 }.elsewhen(io.in.fire) { 135 busy := true.B 136 } 137 } 138 139 exuParams.wbPortConfigs.map{ 140 x => x match { 141 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 142 s"${exuParams.name}: WbPort must priority=0 or priority=1") 143 case FpWB(port, priority) => assert(priority >= 0 && priority <= 2, 144 s"${exuParams.name}: WbPort must priority=0 or priority=1") 145 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 146 s"${exuParams.name}: WbPort must priority=0 or priority=1") 147 case _ => 148 } 149 } 150 val intWbPort = exuParams.getIntWBPort 151 if (intWbPort.isDefined){ 152 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 153 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 154 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 155 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 156 samePort.wbPortConfigs.map( 157 x => x match { 158 case IntWB(port, priority) => { 159 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 160 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 161 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 162 } 163 case _ => 164 } 165 ) 166 ) 167 } 168 val fpWbPort = exuParams.getFpWBPort 169 if (fpWbPort.isDefined) { 170 val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined) 171 .filter(_.getFpWBPort.get.port == fpWbPort.get.port) 172 val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false) 173 if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort => 174 samePort.wbPortConfigs.map( 175 x => x match { 176 case FpWB(port, priority) => { 177 if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1, 178 s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})") 179 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 180 } 181 case _ => 182 } 183 ) 184 ) 185 } 186 val vfWbPort = exuParams.getVfWBPort 187 if (vfWbPort.isDefined) { 188 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 189 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 190 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 191 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 192 samePort.wbPortConfigs.map( 193 x => x match { 194 case VfWB(port, priority) => { 195 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 196 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 197 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 198 } 199 case _ => 200 } 201 ) 202 ) 203 } 204 if(backendParams.debugEn) { 205 dontTouch(io.out.ready) 206 } 207 // rob flush --> funcUnits 208 funcUnits.zipWithIndex.foreach { case (fu, i) => 209 fu.io.flush <> io.flush 210 } 211 212 def acceptCond(input: ExuInput): Seq[Bool] = { 213 input.params.fuConfigs.map(_.fuSel(input)) 214 } 215 216 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 217 218 // ExeUnit.in <---> Dispatcher.in 219 in1ToN.io.in.valid := io.in.valid && !busy 220 in1ToN.io.in.bits := io.in.bits 221 io.in.ready := !busy && in1ToN.io.in.ready 222 223 // Dispatcher.out <---> FunctionUnits 224 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 225 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 226 sink.valid := source.valid 227 source.ready := sink.ready 228 229 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 230 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 231 sink.bits.data.imm := source.bits.imm 232 sink.bits.ctrl.fuOpType := source.bits.fuOpType 233 sink.bits.ctrl.robIdx := source.bits.robIdx 234 sink.bits.ctrl.pdest := source.bits.pdest 235 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 236 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 237 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 238 sink.bits.ctrl.v0Wen .foreach(x => x := source.bits.v0Wen.get) 239 sink.bits.ctrl.vlWen .foreach(x => x := source.bits.vlWen.get) 240 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 241 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 242 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 243 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 244 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 245 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 246 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 247 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFpToVecInst := 0.U) 248 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP32Instr := 0.U) 249 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP64Instr := 0.U) 250 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 251 } 252 253 private val OutresVecs = funcUnits.map { fu => 254 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 255 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 256 for (i <- 1 to latDiff) { 257 OutresVec(i) := OutresVec(i - 1) 258 } 259 OutresVec 260 } 261 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 262 263 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 264 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 265 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 266 private val fuOutresVec = OutresVecs.map(_.last) 267 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 268 269 // Assume that one fu can only write int or fp or vec, 270 // otherwise, wenVec should be assigned to wen in fu. 271 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 272 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 273 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 274 private val fuV0WenVec = funcUnits.map(x => x.cfg.needV0Wen.B && x.io.out.bits.ctrl.v0Wen.getOrElse(false.B)) 275 private val fuVlWenVec = funcUnits.map(x => x.cfg.needVlWen.B && x.io.out.bits.ctrl.vlWen.getOrElse(false.B)) 276 // FunctionUnits <---> ExeUnit.out 277 278 private val outDataVec = Seq( 279 Some(fuOutresVec.map(_.data)), 280 OptionWrapper(funcUnits.exists(_.cfg.writeIntRf), 281 funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuout) => fuout.data}), 282 OptionWrapper(funcUnits.exists(_.cfg.writeFpRf), 283 funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuout) => fuout.data}), 284 OptionWrapper(funcUnits.exists(_.cfg.writeVecRf), 285 funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuout) => fuout.data}), 286 OptionWrapper(funcUnits.exists(_.cfg.writeV0Rf), 287 funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuout) => fuout.data}), 288 OptionWrapper(funcUnits.exists(_.cfg.writeVlRf), 289 funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuout) => fuout.data}), 290 ).flatten 291 private val outDataValidOH = Seq( 292 Some(fuOutValidOH), 293 OptionWrapper(funcUnits.exists(_.cfg.writeIntRf), 294 funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuoutOH) => fuoutOH}), 295 OptionWrapper(funcUnits.exists(_.cfg.writeFpRf), 296 funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuoutOH) => fuoutOH}), 297 OptionWrapper(funcUnits.exists(_.cfg.writeVecRf), 298 funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuoutOH) => fuoutOH}), 299 OptionWrapper(funcUnits.exists(_.cfg.writeV0Rf), 300 funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuoutOH) => fuoutOH}), 301 OptionWrapper(funcUnits.exists(_.cfg.writeVlRf), 302 funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuoutOH) => fuoutOH}), 303 ).flatten 304 305 io.out.valid := Cat(fuOutValidOH).orR 306 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 307 308 // select one fu's result 309 io.out.bits.data := VecInit(outDataVec.zip(outDataValidOH).map{ case(data, validOH) => Mux1H(validOH, data)}) 310 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 311 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 312 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 313 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 314 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 315 io.out.bits.v0Wen.foreach(x => x := Mux1H(fuOutValidOH, fuV0WenVec)) 316 io.out.bits.vlWen.foreach(x => x := Mux1H(fuOutValidOH, fuVlWenVec)) 317 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 318 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 319 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 320 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 321 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 322 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 323 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 324 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 325 326 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 327 fuio => 328 exuio <> fuio 329 fuio.exception := DelayN(exuio.exception, 2) 330 })) 331 332 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 333 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 334 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 335 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 336 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 337 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 338 339 // debug info 340 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 341 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 342 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 343} 344 345class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 346 val in = Flipped(DecoupledIO(gen)) 347 348 val out = Vec(n, DecoupledIO(gen)) 349} 350 351class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 352 (implicit p: Parameters) 353 extends Module { 354 355 val io = IO(new DispatcherIO(gen, n)) 356 357 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 358 359 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 360 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 361 362 io.out.zipWithIndex.foreach { case (out, i) => 363 out.valid := acceptVec(i) && io.in.valid 364 out.bits := io.in.bits 365 } 366 367 io.in.ready := Cat(io.out.map(_.ready)).andR 368} 369 370class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 371 val flush = Flipped(ValidIO(new Redirect())) 372 val in = Flipped(DecoupledIO(new MemExuInput())) 373 val out = DecoupledIO(new MemExuOutput()) 374} 375 376class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 377 val io = IO(new MemExeUnitIO) 378 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 379 fu.io.flush := io.flush 380 fu.io.in.valid := io.in.valid 381 io.in.ready := fu.io.in.ready 382 383 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 384 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 385 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 386 fu.io.in.bits.data.imm := io.in.bits.uop.imm 387 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 388 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 389 390 io.out.valid := fu.io.out.valid 391 fu.io.out.ready := io.out.ready 392 393 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 394 io.out.bits.data := fu.io.out.bits.res.data 395 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 396 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 397 io.out.bits.uop.fuType := io.in.bits.uop.fuType 398 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 399 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 400 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 401 402 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 403}