1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.DelayN 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31 32class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 33 val flush = Flipped(ValidIO(new Redirect())) 34 val in = Flipped(DecoupledIO(new ExuInput(params))) 35 val out = DecoupledIO(new ExuOutput(params)) 36 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 37 val fenceio = if (params.hasFence) Some(new FenceIO) else None 38 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 39} 40 41class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 42 override def shouldBeInlined: Boolean = false 43 44 lazy val module = new ExeUnitImp(this)(p, exuParams) 45} 46 47class ExeUnitImp( 48 override val wrapper: ExeUnit 49)(implicit 50 p: Parameters, exuParams: ExeUnitParams 51) extends LazyModuleImp(wrapper) with HasXSParameter{ 52 private val fuCfgs = exuParams.fuConfigs 53 54 val io = IO(new ExeUnitIO(exuParams)) 55 56 val funcUnit = fuCfgs.map(cfg => { 57 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 58 val module = cfg.fuGen(p, cfg) 59 module 60 }) 61 62 val funcUnits = fuCfgs.zip(funcUnit).map{case(cfg, fu) => 63 val clk_en = WireInit(false.B) 64 val fuVld_en = WireInit(false.B) 65 val fuVld_en_reg = RegInit(false.B) 66 val uncer_en_reg = RegInit(false.B) 67 68 val lat0 = FuType.isLat0(io.in.bits.fuType) 69 val latN = FuType.isLatN(io.in.bits.fuType) 70 val uncerLat = FuType.isUncerLat(io.in.bits.fuType) 71 72 def lat: Int = cfg.latency.latencyVal.getOrElse(0) 73 74 val fuVldVec = (io.in.valid && latN) +: Seq.fill(lat)(RegInit(false.B)) 75 val fuRdyVec = Seq.fill(lat)(Wire(Bool())) :+ io.out.ready 76 77 for (i <- 0 until lat) { 78 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 79 } 80 81 for (i <- 1 to lat) { 82 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 83 fuVldVec(i) := fuVldVec(i - 1) 84 }.elsewhen(fuRdyVec(i)) { 85 fuVldVec(i) := false.B 86 } 87 } 88 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 89 fuVld_en_reg := fuVld_en 90 91 when(uncerLat && io.in.fire) { 92 uncer_en_reg := true.B 93 }.elsewhen(uncerLat && io.out.fire) { 94 uncer_en_reg := false.B 95 } 96 97 when(lat0 && io.in.fire) { 98 clk_en := true.B 99 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 100 clk_en := true.B 101 }.elsewhen(uncerLat && io.in.fire || uncer_en_reg) { 102 clk_en := true.B 103 } 104 105 if (cfg.ckAlwaysEn) { 106 clk_en := true.B 107 } 108 109 val clk_gate = Module(new ClockGate) 110 clk_gate.io.TE := false.B 111 clk_gate.io.E := clk_en 112 clk_gate.io.CK := clock 113 fu.clock := clk_gate.io.Q 114 fu 115 } 116 117 val busy = RegInit(false.B) 118 if (exuParams.latencyCertain){ 119 busy := false.B 120 } 121 else { 122 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 123 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 124 busy := false.B 125 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 126 busy := false.B 127 }.elsewhen(io.out.fire) { 128 busy := false.B 129 }.elsewhen(io.in.fire) { 130 busy := true.B 131 } 132 } 133 134 exuParams.wbPortConfigs.map{ 135 x => x match { 136 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 137 s"${exuParams.name}: WbPort must priority=0 or priority=1") 138 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 139 s"${exuParams.name}: WbPort must priority=0 or priority=1") 140 case _ => 141 } 142 } 143 val intWbPort = exuParams.getIntWBPort 144 if (intWbPort.isDefined){ 145 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 146 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 147 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 148 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 149 samePort.wbPortConfigs.map( 150 x => x match { 151 case IntWB(port, priority) => { 152 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 153 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 154 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 155 } 156 case _ => 157 } 158 ) 159 ) 160 } 161 val vfWbPort = exuParams.getVfWBPort 162 if (vfWbPort.isDefined) { 163 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 164 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 165 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 166 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 167 samePort.wbPortConfigs.map( 168 x => x match { 169 case VfWB(port, priority) => { 170 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 171 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 172 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 173 } 174 case _ => 175 } 176 ) 177 ) 178 } 179 if(backendParams.debugEn) { 180 dontTouch(io.out.ready) 181 } 182 // rob flush --> funcUnits 183 funcUnits.zipWithIndex.foreach { case (fu, i) => 184 fu.io.flush <> io.flush 185 } 186 187 def acceptCond(input: ExuInput): Seq[Bool] = { 188 input.params.fuConfigs.map(_.fuSel(input)) 189 } 190 191 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 192 193 // ExeUnit.in <---> Dispatcher.in 194 in1ToN.io.in.valid := io.in.valid && !busy 195 in1ToN.io.in.bits := io.in.bits 196 io.in.ready := !busy && in1ToN.io.in.ready 197 198 // Dispatcher.out <---> FunctionUnits 199 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 200 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 201 sink.valid := source.valid 202 source.ready := sink.ready 203 204 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 205 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 206 sink.bits.data.imm := source.bits.imm 207 sink.bits.ctrl.fuOpType := source.bits.fuOpType 208 sink.bits.ctrl.robIdx := source.bits.robIdx 209 sink.bits.ctrl.pdest := source.bits.pdest 210 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 211 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 212 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 213 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 214 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 215 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 216 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 217 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 218 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 219 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 220 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 221 } 222 223 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 224 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 225 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 226 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.res.redirect) 227 228 // Assume that one fu can only write int or fp or vec, 229 // otherwise, wenVec should be assigned to wen in fu. 230 private val fuIntWenVec = funcUnits.map(x => x.cfg.writeIntRf.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 231 private val fuFpWenVec = funcUnits.map(x => x.cfg.writeFpRf.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 232 private val fuVecWenVec = funcUnits.map(x => x.cfg.writeVecRf.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 233 // FunctionUnits <---> ExeUnit.out 234 io.out.valid := Cat(fuOutValidOH).orR 235 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 236 237 // select one fu's result 238 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.data)) 239 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 240 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 241 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 242 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 243 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 244 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 245 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 246 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 247 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.res.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 248 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 249 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 250 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 251 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 252 253 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 254 fuio => 255 exuio <> fuio 256 fuio.exception := DelayN(exuio.exception, 2) 257 })) 258 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 259 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 260 261 // debug info 262 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 263 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 264 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 265} 266 267class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 268 val in = Flipped(DecoupledIO(gen)) 269 270 val out = Vec(n, DecoupledIO(gen)) 271} 272 273class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 274 (implicit p: Parameters) 275 extends Module { 276 277 val io = IO(new DispatcherIO(gen, n)) 278 279 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 280 281 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 282 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 283 284 io.out.zipWithIndex.foreach { case (out, i) => 285 out.valid := acceptVec(i) && io.in.valid 286 out.bits := io.in.bits 287 } 288 289 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 290} 291 292class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 293 val flush = Flipped(ValidIO(new Redirect())) 294 val in = Flipped(DecoupledIO(new MemExuInput())) 295 val out = DecoupledIO(new MemExuOutput()) 296} 297 298class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 299 val io = IO(new MemExeUnitIO) 300 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 301 fu.io.flush := io.flush 302 fu.io.in.valid := io.in.valid 303 io.in.ready := fu.io.in.ready 304 305 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 306 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 307 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 308 fu.io.in.bits.data.imm := io.in.bits.uop.imm 309 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 310 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 311 312 io.out.valid := fu.io.out.valid 313 fu.io.out.ready := io.out.ready 314 315 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 316 io.out.bits.data := fu.io.out.bits.res.data 317 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 318 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 319 io.out.bits.uop.fuType := io.in.bits.uop.fuType 320 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 321 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 322 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 323 324 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 325} 326