xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala (revision 694b0180118f79a40a1d26af0ea93ead726ab5e4) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import xiangshan.backend.FenceOpType
8
9class FenceToSbuffer extends XSBundle {
10  val flushSb = Output(Bool())
11  val sbIsEmpty = Input(Bool())
12}
13
14class Fence extends FunctionUnit{
15
16  val sfence = IO(Output(new SfenceBundle))
17  val fencei = IO(Output(Bool()))
18  val toSbuffer = IO(new FenceToSbuffer)
19
20  val (valid, src1, uop, func, lsrc1, lsrc2) = (
21    io.in.valid,
22    io.in.bits.src(0),
23    io.in.bits.uop,
24    io.in.bits.uop.ctrl.fuOpType,
25    io.in.bits.uop.ctrl.lsrc1,
26    io.in.bits.uop.ctrl.lsrc2
27  )
28
29  val s_sb :: s_tlb :: s_icache :: s_none :: Nil = Enum(4)
30  val state = RegInit(s_sb)
31
32  val sbuffer = toSbuffer.flushSb
33  val sbEmpty = toSbuffer.sbIsEmpty
34
35  // NOTE: icache & tlb & sbuffer must receive flush signal at any time
36  sbuffer      := valid && state === s_sb && !sbEmpty
37  fencei       := (state === s_icache && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.fencei)
38  sfence.valid := (state === s_tlb && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.sfence)
39  sfence.bits.rs1  := Mux(state === s_sb, lsrc1 === 0.U, RegEnable(lsrc1 === 0.U, io.in.fire()))
40  sfence.bits.rs2  := Mux(state === s_sb, lsrc2 === 0.U, RegEnable(lsrc2 === 0.U, io.in.fire()))
41  sfence.bits.addr := Mux(state === s_sb, src1,          RegEnable(src1, io.in.fire()))
42
43  when (state === s_sb && valid && func === FenceOpType.fencei && !sbEmpty) { state := s_icache }
44  when (state === s_sb && valid && func === FenceOpType.sfence && !sbEmpty) { state := s_tlb }
45  when (state === s_sb && valid && func === FenceOpType.fence  && !sbEmpty) { state := s_none }
46  when (state =/= s_sb && sbEmpty) { state := s_sb }
47
48  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
49  io.in.ready := state === s_sb
50  io.out.valid := (state =/= s_sb && sbEmpty) || (state === s_sb && sbEmpty && valid)
51  io.out.bits.data := DontCare
52  io.out.bits.uop := Mux(state === s_sb, uop, RegEnable(uop, io.in.fire()))
53
54  assert(!(valid || state =/= s_sb) || io.out.ready) // NOTE: fence instr must be the first(only one) instr, so io.out.ready must be true
55
56  XSDebug(valid || state=/=s_sb || io.out.valid, p"In(${io.in.valid} ${io.in.ready}) Out(${io.out.valid} ${io.out.ready}) state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
57}
58