1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 138 139 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 140 141 // predict info 142 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 143 144 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 145 146 def needFPUCtrl: Boolean = { 147 import FuType._ 148 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 149 } 150 151 def needVecCtrl: Boolean = { 152 import FuType._ 153 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 154 } 155 156 def isMul: Boolean = fuType == FuType.mul 157 158 def isDiv: Boolean = fuType == FuType.div 159 160 def isCsr: Boolean = fuType == FuType.csr 161 162 def isFence: Boolean = fuType == FuType.fence 163 164 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 165 fuType == FuType.vppu || fuType == FuType.vipu || 166 fuType == FuType.vfalu || fuType == FuType.vfma || 167 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 168 fuType == FuType.vidiv 169 170 def isSta: Boolean = name.contains("sta") 171 172 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 173 fuType == FuType.fmisc || fuType == FuType.div || 174 fuType == FuType.vfdiv || fuType == FuType.vidiv 175 176 /** 177 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 178 * @param data [[DataConfig]] 179 * @param tips tips if get failed 180 * @return the index of special src data 181 */ 182 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 183 val srcIdxVec = srcData.map(x => x.indexOf(data)) 184 val idx0 = srcIdxVec.head 185 for (idx <- srcIdxVec) { 186 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 187 } 188 idx0 189 } 190 191 override def toString: String = { 192 var str = s"${this.name}: " 193 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 194 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 195 str += s"latency($latency)" 196 str += s"src($srcData)" 197 str 198 } 199} 200 201object FuConfig { 202 val JmpCfg: FuConfig = FuConfig ( 203 name = "jmp", 204 fuType = FuType.jmp, 205 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 206 srcData = Seq( 207 Seq(IntData()), // jal 208 ), 209 piped = true, 210 writeIntRf = true, 211 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 212 ) 213 214 val BrhCfg: FuConfig = FuConfig ( 215 name = "brh", 216 fuType = FuType.brh, 217 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 218 srcData = Seq( 219 Seq(IntData(), IntData()), 220 ), 221 piped = true, 222 immType = Set(SelImm.IMM_SB), 223 ) 224 225 val I2fCfg: FuConfig = FuConfig ( 226 name = "i2f", 227 FuType.i2f, 228 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 229 srcData = Seq( 230 Seq(IntData()), 231 ), 232 piped = true, 233 writeFpRf = true, 234 writeFflags = true, 235 latency = CertainLatency(2), 236 needSrcFrm = true, 237 ) 238 239 val I2vCfg: FuConfig = FuConfig ( 240 name = "i2v", 241 FuType.i2v, 242 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 243 srcData = Seq( 244 Seq(IntData(), IntData()), 245 ), 246 piped = true, 247 writeVecRf = true, 248 latency = CertainLatency(0), 249 dataBits = 128, 250 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 251 ) 252 253 val F2vCfg: FuConfig = FuConfig ( 254 name = "f2v", 255 FuType.f2v, 256 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 257 srcData = Seq( 258 Seq(FpData(), FpData()), 259 Seq(FpData()), 260 ), 261 piped = true, 262 writeVecRf = true, 263 latency = CertainLatency(0), 264 dataBits = 128, 265 ) 266 267 val CsrCfg: FuConfig = FuConfig ( 268 name = "csr", 269 fuType = FuType.csr, 270 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 271 srcData = Seq( 272 Seq(IntData()), 273 ), 274 piped = true, 275 writeIntRf = true, 276 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 277 flushPipe = true, 278 ) 279 280 val AluCfg: FuConfig = FuConfig ( 281 name = "alu", 282 fuType = FuType.alu, 283 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 284 srcData = Seq( 285 Seq(IntData(), IntData()), 286 ), 287 piped = true, 288 writeIntRf = true, 289 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 290 ) 291 292 val MulCfg: FuConfig = FuConfig ( 293 name = "mul", 294 fuType = FuType.mul, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 296 srcData = Seq( 297 Seq(IntData(), IntData()), 298 ), 299 piped = true, 300 writeIntRf = true, 301 latency = CertainLatency(2), 302 ) 303 304 val DivCfg: FuConfig = FuConfig ( 305 name = "div", 306 fuType = FuType.div, 307 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 308 srcData = Seq( 309 Seq(IntData(), IntData()), 310 ), 311 piped = false, 312 writeIntRf = true, 313 latency = UncertainLatency(), 314 hasInputBuffer = (true, 4, true) 315 ) 316 317 val FenceCfg: FuConfig = FuConfig ( 318 name = "fence", 319 FuType.fence, 320 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 321 srcData = Seq( 322 Seq(IntData(), IntData()), 323 ), 324 piped = true, 325 latency = CertainLatency(0), 326 exceptionOut = Seq(illegalInstr), 327 flushPipe = true 328 ) 329 330 // Todo: split it to simple bitmap exu and complex bku 331 val BkuCfg: FuConfig = FuConfig ( 332 name = "bku", 333 fuType = FuType.bku, 334 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 335 srcData = Seq( 336 Seq(IntData(), IntData()), 337 ), 338 piped = true, 339 writeIntRf = true, 340 latency = CertainLatency(2), 341 ) 342 343 val VSetRvfWvfCfg: FuConfig = FuConfig( 344 name = "vsetrvfwvf", 345 fuType = FuType.vsetfwf, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 347 srcData = Seq( 348 Seq(FpData(), FpData()), 349 ), 350 piped = true, 351 writeVecRf = true, 352 latency = CertainLatency(0), 353 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 354 ) 355 356 val VSetRiWvfCfg: FuConfig = FuConfig( 357 name = "vsetriwvf", 358 fuType = FuType.vsetiwf, 359 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 360 srcData = Seq( 361 Seq(IntData(), IntData()), 362 ), 363 piped = true, 364 writeVecRf = true, 365 latency = CertainLatency(0), 366 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 367 ) 368 369 val VSetRiWiCfg: FuConfig = FuConfig( 370 name = "vsetriwi", 371 fuType = FuType.vsetiwi, 372 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 373 srcData = Seq( 374 Seq(IntData(), IntData()), 375 ), 376 piped = true, 377 writeIntRf = true, 378 latency = CertainLatency(0), 379 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 380 ) 381 382 val FmacCfg: FuConfig = FuConfig ( 383 name = "fmac", 384 fuType = FuType.fmac, 385 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 386 srcData = Seq( 387 Seq(FpData(), FpData()), 388 Seq(FpData(), FpData(), FpData()), 389 ), 390 piped = false, 391 writeFpRf = true, 392 writeFflags = true, 393 latency = UncertainLatency(), 394 needSrcFrm = true, 395 ) 396 397 val F2iCfg: FuConfig = FuConfig ( 398 name = "f2i", 399 fuType = FuType.fmisc, 400 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 401 srcData = Seq( 402 Seq(FpData(), FpData()), 403 Seq(FpData()), 404 ), 405 piped = true, 406 writeIntRf = true, 407 writeFflags = true, 408 latency = CertainLatency(2), 409 needSrcFrm = true, 410 ) 411 412 val F2fCfg: FuConfig = FuConfig ( 413 name = "f2f", 414 fuType = FuType.fmisc, 415 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 416 srcData = Seq( 417 Seq(FpData(), FpData()), 418 Seq(FpData()), 419 ), 420 piped = true, 421 writeFpRf = true, 422 writeFflags = true, 423 latency = CertainLatency(2), 424 needSrcFrm = true, 425 ) 426 427 val FDivSqrtCfg: FuConfig = FuConfig ( 428 name = "fDivSqrt", 429 fuType = FuType.fDivSqrt, 430 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 431 srcData = Seq( 432 Seq(FpData(), FpData()), 433 ), 434 piped = false, 435 writeFpRf = true, 436 writeFflags = true, 437 latency = UncertainLatency(), 438 hasInputBuffer = (true, 8, true), 439 needSrcFrm = true, 440 ) 441 442 val LduCfg: FuConfig = FuConfig ( 443 name = "ldu", 444 fuType = FuType.ldu, 445 fuGen = null, // Todo 446 srcData = Seq( 447 Seq(IntData()), 448 ), 449 piped = false, // Todo: check it 450 writeIntRf = true, 451 writeFpRf = true, 452 latency = UncertainLatency(3), 453 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 454 flushPipe = true, 455 replayInst = true, 456 hasLoadError = true, 457 trigger = true, 458 immType = Set(SelImm.IMM_I), 459 ) 460 461 val StaCfg: FuConfig = FuConfig ( 462 name = "sta", 463 fuType = FuType.stu, 464 fuGen = null, // Todo 465 srcData = Seq( 466 Seq(IntData()), 467 ), 468 piped = false, 469 latency = UncertainLatency(), 470 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 471 trigger = true, 472 immType = Set(SelImm.IMM_S), 473 ) 474 475 val StdCfg: FuConfig = FuConfig ( 476 name = "std", 477 fuType = FuType.stu, 478 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 479 srcData = Seq( 480 Seq(IntData()), 481 Seq(FpData()), 482 ), 483 piped = true, 484 latency = CertainLatency(0) 485 ) 486 487 val HyldaCfg = FuConfig ( 488 name = "hylda", 489 fuType = FuType.ldu, 490 fuGen = null, // Todo 491 srcData = Seq( 492 Seq(IntData()), 493 ), 494 piped = false, // Todo: check it 495 writeIntRf = true, 496 writeFpRf = true, 497 latency = UncertainLatency(3), 498 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 499 flushPipe = true, 500 replayInst = true, 501 hasLoadError = true, 502 immType = Set(SelImm.IMM_I), 503 ) 504 505 val HystaCfg = FuConfig ( 506 name = "hysta", 507 fuType = FuType.stu, 508 fuGen = null, // Todo 509 srcData = Seq( 510 Seq(IntData()), 511 ), 512 piped = false, 513 latency = UncertainLatency(), 514 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 515 immType = Set(SelImm.IMM_S), 516 ) 517 518 val FakeHystaCfg = FuConfig ( 519 name = "hysta", 520 fuType = FuType.stu, 521 fuGen = null, // Todo 522 srcData = Seq(), 523 piped = false, 524 latency = UncertainLatency(), 525 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 526 immType = Set(), 527 ) 528 529 val MouCfg: FuConfig = FuConfig ( 530 name = "mou", 531 fuType = FuType.mou, 532 fuGen = null, // Todo 533 srcData = Seq( 534 Seq(IntData()), 535 ), 536 piped = false, // Todo: check it 537 writeIntRf = true, 538 latency = UncertainLatency(), 539 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 540 trigger = true, 541 ) 542 543 val MoudCfg: FuConfig = FuConfig ( 544 name = "moud", 545 fuType = FuType.mou, 546 fuGen = null, // Todo 547 srcData = Seq( 548 Seq(IntData()), 549 ), 550 piped = true, 551 latency = CertainLatency(0), 552 ) 553 554 val VialuCfg = FuConfig ( 555 name = "vialuFix", 556 fuType = FuType.vialuF, 557 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 558 srcData = Seq( 559 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 560 ), 561 piped = true, 562 writeVecRf = true, 563 writeVxsat = true, 564 latency = CertainLatency(1), 565 vconfigWakeUp = true, 566 maskWakeUp = true, 567 dataBits = 128, 568 exceptionOut = Seq(illegalInstr), 569 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 570 ) 571 572 val VimacCfg = FuConfig ( 573 name = "vimac", 574 fuType = FuType.vimac, 575 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 576 srcData = Seq( 577 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 578 ), 579 piped = true, 580 writeVecRf = true, 581 writeVxsat = true, 582 latency = CertainLatency(2), 583 vconfigWakeUp = true, 584 maskWakeUp = true, 585 dataBits = 128, 586 exceptionOut = Seq(illegalInstr), 587 ) 588 589 val VidivCfg = FuConfig ( 590 name = "vidiv", 591 fuType = FuType.vidiv, 592 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 593 srcData = Seq( 594 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 595 ), 596 piped = false, 597 writeVecRf = true, 598 latency = UncertainLatency(), 599 vconfigWakeUp = true, 600 maskWakeUp = true, 601 dataBits = 128, 602 exceptionOut = Seq(illegalInstr), 603 ) 604 605 val VppuCfg = FuConfig ( 606 name = "vppu", 607 fuType = FuType.vppu, 608 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 609 srcData = Seq( 610 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 611 ), 612 piped = true, 613 writeVecRf = true, 614 latency = CertainLatency(1), 615 vconfigWakeUp = true, 616 maskWakeUp = true, 617 dataBits = 128, 618 exceptionOut = Seq(illegalInstr), 619 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 620 ) 621 622 val VipuCfg: FuConfig = FuConfig ( 623 name = "vipu", 624 fuType = FuType.vipu, 625 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 626 srcData = Seq( 627 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 628 ), 629 piped = true, 630 writeIntRf = true, 631 writeVecRf = true, 632 latency = CertainLatency(1), 633 vconfigWakeUp = true, 634 maskWakeUp = true, 635 dataBits = 128, 636 exceptionOut = Seq(illegalInstr), 637 ) 638 639 val VfaluCfg = FuConfig ( 640 name = "vfalu", 641 fuType = FuType.vfalu, 642 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 643 srcData = Seq( 644 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 645 ), 646 piped = true, 647 writeVecRf = true, 648 writeFpRf = true, 649 writeIntRf = true, 650 writeFflags = true, 651 latency = CertainLatency(1), 652 vconfigWakeUp = true, 653 maskWakeUp = true, 654 dataBits = 128, 655 exceptionOut = Seq(illegalInstr), 656 ) 657 658 val VfmaCfg = FuConfig ( 659 name = "vfma", 660 fuType = FuType.vfma, 661 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 662 srcData = Seq( 663 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 664 ), 665 piped = true, 666 writeVecRf = true, 667 writeFpRf = true, 668 writeFflags = true, 669 latency = CertainLatency(3), 670 vconfigWakeUp = true, 671 maskWakeUp = true, 672 dataBits = 128, 673 exceptionOut = Seq(illegalInstr), 674 ) 675 676 val VfdivCfg = FuConfig( 677 name = "vfdiv", 678 fuType = FuType.vfdiv, 679 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 680 srcData = Seq( 681 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 682 ), 683 piped = false, 684 writeVecRf = true, 685 writeFpRf = true, 686 writeFflags = true, 687 latency = UncertainLatency(), 688 vconfigWakeUp = true, 689 maskWakeUp = true, 690 dataBits = 128, 691 exceptionOut = Seq(illegalInstr), 692 ) 693 694 val VfcvtCfg = FuConfig( 695 name = "vfcvt", 696 fuType = FuType.vfcvt, 697 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 698 srcData = Seq( 699 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 700 ), 701 piped = true, 702 writeVecRf = true, 703 writeFpRf = false, 704 writeFflags = true, 705 latency = CertainLatency(2), 706 vconfigWakeUp = true, 707 maskWakeUp = true, 708 dataBits = 128, 709 exceptionOut = Seq(illegalInstr), 710 ) 711 712 713 val VlduCfg: FuConfig = FuConfig ( 714 name = "vldu", 715 fuType = FuType.vldu, 716 fuGen = null, 717 srcData = Seq( 718 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 719 ), 720 piped = false, // Todo: check it 721 writeVecRf = true, 722 latency = UncertainLatency(), 723 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 724 flushPipe = true, 725 replayInst = true, 726 hasLoadError = true, 727 vconfigWakeUp = true, 728 maskWakeUp = true, 729 dataBits = 128, 730 ) 731 732 val VstuCfg: FuConfig = FuConfig ( 733 name = "vstu", 734 fuType = FuType.vstu, 735 fuGen = null, 736 srcData = Seq( 737 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 738 ), 739 piped = false, 740 writeVecRf = false, 741 latency = UncertainLatency(), 742 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 743 flushPipe = true, 744 replayInst = true, 745 hasLoadError = true, 746 vconfigWakeUp = true, 747 maskWakeUp = true, 748 dataBits = 128, 749 ) 750 751 def allConfigs = Seq( 752 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 753 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 754 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 755 ) 756 757 def VecArithFuConfigs = Seq( 758 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 759 ) 760} 761 762