1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0), 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 immType : Set[UInt] = Set(), 67 // vector 68 vconfigWakeUp : Boolean = false, 69 maskWakeUp : Boolean = false, 70) { 71 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 72 def needFpWen: Boolean = writeFpRf 73 def needVecWen: Boolean = writeVecRf 74 var vconfigIdx = -1 75 var maskSrcIdx = -1 76 if (vconfigWakeUp) { 77 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 78 } 79 if (maskWakeUp) { 80 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 81 } 82 83 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 84 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 85 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 86 87 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 88 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 93 94 def readFp: Boolean = numFpSrc > 0 95 96 def fuSel(uop: ExuInput): Bool = { 97 // Don't add more shit here!!! 98 // Todo: add new FuType to distinguish f2i, f2f 99 uop.fuType === this.fuType.U 100 } 101 102 /** 103 * params(i): data type set of the ith src port 104 * @return 105 */ 106 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 107 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 108 // make srcData is uniform sized to avoid exception when transpose 109 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 110 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 111 } 112 113 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 114 srcData 115 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 116 .filter(_.nonEmpty) 117 .map(_.get) 118 .toSet 119 } 120 121 def hasNoDataWB: Boolean = { 122 !(writeIntRf || writeFpRf || writeVecRf) 123 } 124 125 def getSrcMaxWidthVec = { 126 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 127 } 128 129 def genSrcDataVec: Seq[UInt] = { 130 getSrcMaxWidthVec.map(w => UInt(w.W)) 131 } 132 133 // csr's redirect is in its exception bundle 134 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 135 136 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 137 138 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 139 140 // predict info 141 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 142 143 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 144 145 def needFPUCtrl: Boolean = { 146 import FuType._ 147 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 148 } 149 150 def needVecCtrl: Boolean = { 151 import FuType._ 152 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 153 } 154 155 def isMul: Boolean = fuType == FuType.mul 156 157 def isDiv: Boolean = fuType == FuType.div 158 159 def isCsr: Boolean = fuType == FuType.csr 160 161 def isFence: Boolean = fuType == FuType.fence 162 163 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 164 fuType == FuType.vppu || fuType == FuType.vipu || 165 fuType == FuType.vfalu || fuType == FuType.vfma || 166 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 167 fuType == FuType.vidiv 168 169 def needOg2: Boolean = isVecArith || fuType == FuType.fmisc || fuType == FuType.vsetfwf || fuType == FuType.f2v 170 171 def isSta: Boolean = name.contains("sta") 172 173 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 174 fuType == FuType.fmisc || fuType == FuType.div || 175 fuType == FuType.vfdiv || fuType == FuType.vidiv 176 177 /** 178 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 179 * @param data [[DataConfig]] 180 * @param tips tips if get failed 181 * @return the index of special src data 182 */ 183 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 184 val srcIdxVec = srcData.map(x => x.indexOf(data)) 185 val idx0 = srcIdxVec.head 186 for (idx <- srcIdxVec) { 187 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 188 } 189 idx0 190 } 191 192 override def toString: String = { 193 var str = s"${this.name}: " 194 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 195 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 196 str += s"latency($latency)" 197 str += s"src($srcData)" 198 str 199 } 200} 201 202object FuConfig { 203 val JmpCfg: FuConfig = FuConfig ( 204 name = "jmp", 205 fuType = FuType.jmp, 206 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 207 srcData = Seq( 208 Seq(IntData()), // jal 209 ), 210 piped = true, 211 writeIntRf = true, 212 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 213 ) 214 215 val BrhCfg: FuConfig = FuConfig ( 216 name = "brh", 217 fuType = FuType.brh, 218 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 219 srcData = Seq( 220 Seq(IntData(), IntData()), 221 ), 222 piped = true, 223 immType = Set(SelImm.IMM_SB), 224 ) 225 226 val I2fCfg: FuConfig = FuConfig ( 227 name = "i2f", 228 FuType.i2f, 229 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 230 srcData = Seq( 231 Seq(IntData()), 232 ), 233 piped = true, 234 writeFpRf = true, 235 writeFflags = true, 236 latency = CertainLatency(2), 237 needSrcFrm = true, 238 ) 239 240 val I2vCfg: FuConfig = FuConfig ( 241 name = "i2v", 242 FuType.i2v, 243 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 244 srcData = Seq( 245 Seq(IntData(), IntData()), 246 ), 247 piped = true, 248 writeVecRf = true, 249 writeFpRf = true, 250 latency = CertainLatency(0), 251 dataBits = 128, 252 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 253 ) 254 255 val F2vCfg: FuConfig = FuConfig ( 256 name = "f2v", 257 FuType.f2v, 258 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 259 srcData = Seq( 260 Seq(FpData(), FpData()), 261 Seq(FpData()), 262 ), 263 piped = true, 264 writeVecRf = true, 265 latency = CertainLatency(0), 266 dataBits = 128, 267 ) 268 269 val CsrCfg: FuConfig = FuConfig ( 270 name = "csr", 271 fuType = FuType.csr, 272 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 273 srcData = Seq( 274 Seq(IntData()), 275 ), 276 piped = true, 277 writeIntRf = true, 278 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 279 flushPipe = true, 280 ) 281 282 val AluCfg: FuConfig = FuConfig ( 283 name = "alu", 284 fuType = FuType.alu, 285 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 286 srcData = Seq( 287 Seq(IntData(), IntData()), 288 ), 289 piped = true, 290 writeIntRf = true, 291 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 292 ) 293 294 val MulCfg: FuConfig = FuConfig ( 295 name = "mul", 296 fuType = FuType.mul, 297 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 298 srcData = Seq( 299 Seq(IntData(), IntData()), 300 ), 301 piped = true, 302 writeIntRf = true, 303 latency = CertainLatency(2), 304 ) 305 306 val DivCfg: FuConfig = FuConfig ( 307 name = "div", 308 fuType = FuType.div, 309 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 310 srcData = Seq( 311 Seq(IntData(), IntData()), 312 ), 313 piped = false, 314 writeIntRf = true, 315 latency = UncertainLatency(), 316 hasInputBuffer = (true, 4, true) 317 ) 318 319 val FenceCfg: FuConfig = FuConfig ( 320 name = "fence", 321 FuType.fence, 322 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 323 srcData = Seq( 324 Seq(IntData(), IntData()), 325 ), 326 piped = true, 327 latency = CertainLatency(0), 328 exceptionOut = Seq(illegalInstr, virtualInstr), 329 flushPipe = true 330 ) 331 332 // Todo: split it to simple bitmap exu and complex bku 333 val BkuCfg: FuConfig = FuConfig ( 334 name = "bku", 335 fuType = FuType.bku, 336 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 337 srcData = Seq( 338 Seq(IntData(), IntData()), 339 ), 340 piped = true, 341 writeIntRf = true, 342 latency = CertainLatency(2), 343 ) 344 345 val VSetRvfWvfCfg: FuConfig = FuConfig( 346 name = "vsetrvfwvf", 347 fuType = FuType.vsetfwf, 348 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 349 srcData = Seq( 350 Seq(FpData(), FpData()), 351 ), 352 piped = true, 353 writeVecRf = true, 354 latency = CertainLatency(0), 355 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 356 ) 357 358 val VSetRiWvfCfg: FuConfig = FuConfig( 359 name = "vsetriwvf", 360 fuType = FuType.vsetiwf, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 362 srcData = Seq( 363 Seq(IntData(), IntData()), 364 ), 365 piped = true, 366 writeVecRf = true, 367 latency = CertainLatency(0), 368 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 369 ) 370 371 val VSetRiWiCfg: FuConfig = FuConfig( 372 name = "vsetriwi", 373 fuType = FuType.vsetiwi, 374 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 375 srcData = Seq( 376 Seq(IntData(), IntData()), 377 ), 378 piped = true, 379 writeIntRf = true, 380 latency = CertainLatency(0), 381 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 382 ) 383 384 val FmacCfg: FuConfig = FuConfig ( 385 name = "fmac", 386 fuType = FuType.fmac, 387 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 388 srcData = Seq( 389 Seq(FpData(), FpData()), 390 Seq(FpData(), FpData(), FpData()), 391 ), 392 piped = false, 393 writeFpRf = true, 394 writeFflags = true, 395 latency = UncertainLatency(), 396 needSrcFrm = true, 397 ) 398 399 val F2iCfg: FuConfig = FuConfig ( 400 name = "f2i", 401 fuType = FuType.fmisc, 402 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 403 srcData = Seq( 404 Seq(FpData(), FpData()), 405 Seq(FpData()), 406 ), 407 piped = true, 408 writeIntRf = true, 409 writeFflags = true, 410 latency = CertainLatency(2), 411 needSrcFrm = true, 412 ) 413 414 val F2fCfg: FuConfig = FuConfig ( 415 name = "f2f", 416 fuType = FuType.fmisc, 417 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 418 srcData = Seq( 419 Seq(FpData(), FpData()), 420 Seq(FpData()), 421 ), 422 piped = true, 423 writeFpRf = true, 424 writeFflags = true, 425 latency = CertainLatency(2), 426 needSrcFrm = true, 427 ) 428 429 val FDivSqrtCfg: FuConfig = FuConfig ( 430 name = "fDivSqrt", 431 fuType = FuType.fDivSqrt, 432 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 433 srcData = Seq( 434 Seq(FpData(), FpData()), 435 ), 436 piped = false, 437 writeFpRf = true, 438 writeFflags = true, 439 latency = UncertainLatency(), 440 hasInputBuffer = (true, 8, true), 441 needSrcFrm = true, 442 ) 443 444 val LduCfg: FuConfig = FuConfig ( 445 name = "ldu", 446 fuType = FuType.ldu, 447 fuGen = null, // Todo 448 srcData = Seq( 449 Seq(IntData()), 450 ), 451 piped = false, // Todo: check it 452 writeIntRf = true, 453 writeFpRf = true, 454 latency = UncertainLatency(3), 455 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 456 flushPipe = true, 457 replayInst = true, 458 hasLoadError = true, 459 trigger = true, 460 immType = Set(SelImm.IMM_I), 461 ) 462 463 val StaCfg: FuConfig = FuConfig ( 464 name = "sta", 465 fuType = FuType.stu, 466 fuGen = null, // Todo 467 srcData = Seq( 468 Seq(IntData()), 469 ), 470 piped = false, 471 latency = UncertainLatency(), 472 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 473 trigger = true, 474 immType = Set(SelImm.IMM_S), 475 ) 476 477 val StdCfg: FuConfig = FuConfig ( 478 name = "std", 479 fuType = FuType.stu, 480 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 481 srcData = Seq( 482 Seq(IntData()), 483 Seq(FpData()), 484 ), 485 piped = true, 486 latency = CertainLatency(0) 487 ) 488 489 val HyldaCfg = FuConfig ( 490 name = "hylda", 491 fuType = FuType.ldu, 492 fuGen = null, // Todo 493 srcData = Seq( 494 Seq(IntData()), 495 ), 496 piped = false, // Todo: check it 497 writeIntRf = true, 498 writeFpRf = true, 499 latency = UncertainLatency(3), 500 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 501 flushPipe = true, 502 replayInst = true, 503 hasLoadError = true, 504 immType = Set(SelImm.IMM_I), 505 ) 506 507 val HystaCfg = FuConfig ( 508 name = "hysta", 509 fuType = FuType.stu, 510 fuGen = null, // Todo 511 srcData = Seq( 512 Seq(IntData()), 513 ), 514 piped = false, 515 latency = UncertainLatency(), 516 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 517 immType = Set(SelImm.IMM_S), 518 ) 519 520 val FakeHystaCfg = FuConfig ( 521 name = "hysta", 522 fuType = FuType.stu, 523 fuGen = null, // Todo 524 srcData = Seq(), 525 piped = false, 526 latency = UncertainLatency(), 527 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 528 immType = Set(), 529 ) 530 531 val MouCfg: FuConfig = FuConfig ( 532 name = "mou", 533 fuType = FuType.mou, 534 fuGen = null, // Todo 535 srcData = Seq( 536 Seq(IntData()), 537 ), 538 piped = false, // Todo: check it 539 writeFakeIntRf = true, 540 latency = UncertainLatency(), 541 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 542 trigger = true, 543 ) 544 545 val MoudCfg: FuConfig = FuConfig ( 546 name = "moud", 547 fuType = FuType.mou, 548 fuGen = null, // Todo 549 srcData = Seq( 550 Seq(IntData()), 551 ), 552 piped = true, 553 latency = CertainLatency(0), 554 ) 555 556 val VialuCfg = FuConfig ( 557 name = "vialuFix", 558 fuType = FuType.vialuF, 559 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 560 srcData = Seq( 561 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 562 ), 563 piped = true, 564 writeVecRf = true, 565 writeVxsat = true, 566 needSrcVxrm = true, 567 latency = CertainLatency(1), 568 vconfigWakeUp = true, 569 maskWakeUp = true, 570 dataBits = 128, 571 exceptionOut = Seq(illegalInstr), 572 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 573 ) 574 575 val VimacCfg = FuConfig ( 576 name = "vimac", 577 fuType = FuType.vimac, 578 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 579 srcData = Seq( 580 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 581 ), 582 piped = true, 583 writeVecRf = true, 584 writeVxsat = true, 585 needSrcVxrm = true, 586 latency = CertainLatency(2), 587 vconfigWakeUp = true, 588 maskWakeUp = true, 589 dataBits = 128, 590 exceptionOut = Seq(illegalInstr), 591 ) 592 593 val VidivCfg = FuConfig ( 594 name = "vidiv", 595 fuType = FuType.vidiv, 596 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 597 srcData = Seq( 598 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 599 ), 600 piped = false, 601 writeVecRf = true, 602 latency = UncertainLatency(), 603 vconfigWakeUp = true, 604 maskWakeUp = true, 605 dataBits = 128, 606 exceptionOut = Seq(illegalInstr), 607 ) 608 609 val VppuCfg = FuConfig ( 610 name = "vppu", 611 fuType = FuType.vppu, 612 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 613 srcData = Seq( 614 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 615 ), 616 piped = true, 617 writeVecRf = true, 618 latency = CertainLatency(2), 619 vconfigWakeUp = true, 620 maskWakeUp = true, 621 dataBits = 128, 622 exceptionOut = Seq(illegalInstr), 623 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 624 ) 625 626 val VipuCfg: FuConfig = FuConfig ( 627 name = "vipu", 628 fuType = FuType.vipu, 629 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 630 srcData = Seq( 631 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 632 ), 633 piped = true, 634 writeIntRf = true, 635 writeVecRf = true, 636 latency = CertainLatency(2), 637 vconfigWakeUp = true, 638 maskWakeUp = true, 639 dataBits = 128, 640 exceptionOut = Seq(illegalInstr), 641 ) 642 643 val VfaluCfg = FuConfig ( 644 name = "vfalu", 645 fuType = FuType.vfalu, 646 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 647 srcData = Seq( 648 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 649 ), 650 piped = true, 651 writeVecRf = true, 652 writeFpRf = true, 653 writeIntRf = true, 654 writeFflags = true, 655 latency = CertainLatency(1), 656 vconfigWakeUp = true, 657 maskWakeUp = true, 658 dataBits = 128, 659 exceptionOut = Seq(illegalInstr), 660 needSrcFrm = true, 661 ) 662 663 val VfmaCfg = FuConfig ( 664 name = "vfma", 665 fuType = FuType.vfma, 666 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 667 srcData = Seq( 668 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 669 ), 670 piped = true, 671 writeVecRf = true, 672 writeFpRf = true, 673 writeFflags = true, 674 latency = CertainLatency(3), 675 vconfigWakeUp = true, 676 maskWakeUp = true, 677 dataBits = 128, 678 exceptionOut = Seq(illegalInstr), 679 needSrcFrm = true, 680 ) 681 682 val VfdivCfg = FuConfig( 683 name = "vfdiv", 684 fuType = FuType.vfdiv, 685 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 686 srcData = Seq( 687 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 688 ), 689 piped = false, 690 writeVecRf = true, 691 writeFpRf = true, 692 writeFflags = true, 693 latency = UncertainLatency(), 694 vconfigWakeUp = true, 695 maskWakeUp = true, 696 dataBits = 128, 697 exceptionOut = Seq(illegalInstr), 698 needSrcFrm = true, 699 ) 700 701 val VfcvtCfg = FuConfig( 702 name = "vfcvt", 703 fuType = FuType.vfcvt, 704 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 705 srcData = Seq( 706 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 707 ), 708 piped = true, 709 writeVecRf = true, 710 writeFpRf = true, 711 writeIntRf = true, 712 writeFflags = true, 713 latency = CertainLatency(2), 714 vconfigWakeUp = true, 715 maskWakeUp = true, 716 dataBits = 128, 717 exceptionOut = Seq(illegalInstr), 718 needSrcFrm = true, 719 ) 720 721 722 val VlduCfg: FuConfig = FuConfig ( 723 name = "vldu", 724 fuType = FuType.vldu, 725 fuGen = null, 726 srcData = Seq( 727 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 728 ), 729 piped = false, // Todo: check it 730 writeVecRf = true, 731 latency = UncertainLatency(), 732 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 733 flushPipe = true, 734 replayInst = true, 735 hasLoadError = true, 736 vconfigWakeUp = true, 737 maskWakeUp = true, 738 dataBits = 128, 739 ) 740 741 val VstuCfg: FuConfig = FuConfig ( 742 name = "vstu", 743 fuType = FuType.vstu, 744 fuGen = null, 745 srcData = Seq( 746 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 747 ), 748 piped = false, 749 writeVecRf = false, 750 latency = UncertainLatency(), 751 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 752 flushPipe = true, 753 replayInst = true, 754 hasLoadError = true, 755 vconfigWakeUp = true, 756 maskWakeUp = true, 757 dataBits = 128, 758 ) 759 760 def allConfigs = Seq( 761 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 762 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 763 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 764 ) 765 766 def VecArithFuConfigs = Seq( 767 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 768 ) 769} 770 771