1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param immType the immediate type of this $fu 37 * @param vconfigWakeUp 38 * @param maskWakeUp 39 * 40 * @define fu function unit 41 */ 42case class FuConfig ( 43 name : String, 44 fuType : FuType.OHType, 45 fuGen : (Parameters, FuConfig) => FuncUnit, 46 srcData : Seq[Seq[DataConfig]], 47 piped : Boolean, 48 maybeBlock : Boolean = false, 49 writeIntRf : Boolean = false, 50 writeFpRf : Boolean = false, 51 writeVecRf : Boolean = false, 52 writeFflags : Boolean = false, 53 writeVxsat : Boolean = false, 54 dataBits : Int = 64, 55 latency : HasFuLatency = CertainLatency(0), 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut : Seq[Int] = Seq(), 58 hasLoadError : Boolean = false, 59 flushPipe : Boolean = false, 60 replayInst : Boolean = false, 61 trigger : Boolean = false, 62 needSrcFrm : Boolean = false, 63 immType : Set[UInt] = Set(), 64 // vector 65 vconfigWakeUp : Boolean = false, 66 maskWakeUp : Boolean = false, 67) { 68 var vconfigIdx = -1 69 var maskSrcIdx = -1 70 if (vconfigWakeUp) { 71 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 72 } 73 if (maskWakeUp) { 74 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 75 } 76 77 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 78 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 79 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 80 81 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 82 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 83 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 84 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 85 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 86 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 87 88 def readFp: Boolean = numFpSrc > 0 89 90 def fuSel(uop: ExuInput): Bool = { 91 // Don't add more shit here!!! 92 // Todo: add new FuType to distinguish f2i, f2f 93 if (this.fuType == FuType.fmisc) { 94 this.name match { 95 case FuConfig.F2iCfg.name => uop.rfWen.get && uop.fuType === this.fuType.U 96 case FuConfig.F2fCfg.name => uop.fpu.get.fpWen && !uop.fpu.get.div && !uop.fpu.get.sqrt && uop.fuType === this.fuType.U 97 } 98 } else { 99 uop.fuType === this.fuType.U 100 } 101 } 102 103 /** 104 * params(i): data type set of the ith src port 105 * @return 106 */ 107 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 108 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 109 // make srcData is uniform sized to avoid exception when transpose 110 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 111 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 112 } 113 114 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 115 srcData 116 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 117 .filter(_.nonEmpty) 118 .map(_.get) 119 .toSet 120 } 121 122 def hasNoDataWB: Boolean = { 123 !(writeIntRf || writeFpRf || writeVecRf) 124 } 125 126 def getSrcMaxWidthVec = { 127 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 128 } 129 130 def genSrcDataVec: Seq[UInt] = { 131 getSrcMaxWidthVec.map(w => UInt(w.W)) 132 } 133 134 // csr's redirect is in its exception bundle 135 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 136 137 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 138 139 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.fence).contains(fuType) 140 141 def needFPUCtrl: Boolean = { 142 import FuType._ 143 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 144 } 145 146 def needVecCtrl: Boolean = { 147 import FuType._ 148 Seq(vipu, vialuF, vimac, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 149 } 150 151 def isMul: Boolean = fuType == FuType.mul 152 153 def isDiv: Boolean = fuType == FuType.div 154 155 def isCsr: Boolean = fuType == FuType.csr 156 157 def isFence: Boolean = fuType == FuType.fence 158 159 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 160 fuType == FuType.vppu || fuType == FuType.vipu || 161 fuType == FuType.vfalu || fuType == FuType.vfma || 162 fuType == FuType.vfdiv || fuType == FuType.vfcvt 163 164 def isSta: Boolean = name.contains("sta") 165 166 /** 167 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 168 * @param data [[DataConfig]] 169 * @param tips tips if get failed 170 * @return the index of special src data 171 */ 172 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 173 val srcIdxVec = srcData.map(x => x.indexOf(data)) 174 val idx0 = srcIdxVec.head 175 for (idx <- srcIdxVec) { 176 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 177 } 178 idx0 179 } 180 181 override def toString: String = { 182 var str = s"${this.name}: " 183 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 184 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 185 str += s"latency($latency)" 186 str += s"src($srcData)" 187 str 188 } 189} 190 191object FuConfig { 192 val JmpCfg: FuConfig = FuConfig ( 193 name = "jmp", 194 fuType = FuType.jmp, 195 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 196 srcData = Seq( 197 Seq(IntData()), // jal 198 ), 199 piped = true, 200 writeIntRf = true, 201 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 202 ) 203 204 val BrhCfg: FuConfig = FuConfig ( 205 name = "brh", 206 fuType = FuType.brh, 207 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 208 srcData = Seq( 209 Seq(IntData(), IntData()), 210 ), 211 piped = true, 212 immType = Set(SelImm.IMM_SB), 213 ) 214 215 val I2fCfg: FuConfig = FuConfig ( 216 name = "i2f", 217 FuType.i2f, 218 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 219 srcData = Seq( 220 Seq(IntData()), 221 ), 222 piped = true, 223 writeFpRf = true, 224 writeFflags = true, 225 latency = CertainLatency(2), 226 needSrcFrm = true, 227 ) 228 229 val I2vCfg: FuConfig = FuConfig ( 230 name = "i2v", 231 FuType.i2v, 232 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToVec(cfg)(p).suggestName("i2v")), 233 srcData = Seq( 234 Seq(IntData(), IntData()), 235 ), 236 piped = true, 237 writeVecRf = true, 238 latency = CertainLatency(0), 239 dataBits = 128, 240 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 241 ) 242 243 val CsrCfg: FuConfig = FuConfig ( 244 name = "csr", 245 fuType = FuType.csr, 246 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 247 srcData = Seq( 248 Seq(IntData()), 249 ), 250 piped = true, 251 writeIntRf = true, 252 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 253 flushPipe = true, 254 ) 255 256 val AluCfg: FuConfig = FuConfig ( 257 name = "alu", 258 fuType = FuType.alu, 259 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 260 srcData = Seq( 261 Seq(IntData(), IntData()), 262 ), 263 piped = true, 264 writeIntRf = true, 265 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 266 ) 267 268 val MulCfg: FuConfig = FuConfig ( 269 name = "mul", 270 fuType = FuType.mul, 271 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 272 srcData = Seq( 273 Seq(IntData(), IntData()), 274 ), 275 piped = true, 276 writeIntRf = true, 277 latency = CertainLatency(2), 278 ) 279 280 val DivCfg: FuConfig = FuConfig ( 281 name = "div", 282 fuType = FuType.div, 283 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 284 srcData = Seq( 285 Seq(IntData(), IntData()), 286 ), 287 piped = false, 288 writeIntRf = true, 289 latency = UncertainLatency(), 290 hasInputBuffer = (true, 4, true) 291 ) 292 293 val FenceCfg: FuConfig = FuConfig ( 294 name = "fence", 295 FuType.fence, 296 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 297 srcData = Seq( 298 Seq(IntData(), IntData()), 299 ), 300 piped = true, 301 latency = CertainLatency(0), 302 exceptionOut = Seq(illegalInstr), 303 flushPipe = true 304 ) 305 306 // Todo: split it to simple bitmap exu and complex bku 307 val BkuCfg: FuConfig = FuConfig ( 308 name = "bku", 309 fuType = FuType.bku, 310 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 311 srcData = Seq( 312 Seq(IntData(), IntData()), 313 ), 314 piped = true, 315 writeIntRf = true, 316 latency = CertainLatency(2), 317 ) 318 319 val VSetRvfWvfCfg: FuConfig = FuConfig( 320 name = "vsetrvfwvf", 321 fuType = FuType.vsetiwf, 322 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 323 srcData = Seq( 324 Seq(FpData(), FpData()), 325 ), 326 piped = true, 327 writeVecRf = true, 328 latency = CertainLatency(0), 329 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 330 ) 331 332 val VSetRiWvfCfg: FuConfig = FuConfig( 333 name = "vsetriwvf", 334 fuType = FuType.vsetiwf, 335 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 336 srcData = Seq( 337 Seq(IntData(), IntData()), 338 ), 339 piped = true, 340 writeVecRf = true, 341 latency = CertainLatency(0), 342 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 343 ) 344 345 val VSetRiWiCfg: FuConfig = FuConfig( 346 name = "vsetriwi", 347 fuType = FuType.vsetiwi, 348 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 349 srcData = Seq( 350 Seq(IntData(), IntData()), 351 ), 352 piped = true, 353 writeIntRf = true, 354 latency = CertainLatency(0), 355 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 356 ) 357 358 val FmacCfg: FuConfig = FuConfig ( 359 name = "fmac", 360 fuType = FuType.fmac, 361 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 362 srcData = Seq( 363 Seq(FpData(), FpData()), 364 Seq(FpData(), FpData(), FpData()), 365 ), 366 piped = false, 367 writeFpRf = true, 368 writeFflags = true, 369 latency = UncertainLatency(), 370 needSrcFrm = true, 371 ) 372 373 val F2iCfg: FuConfig = FuConfig ( 374 name = "f2i", 375 fuType = FuType.fmisc, 376 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 377 srcData = Seq( 378 Seq(FpData(), FpData()), 379 Seq(FpData()), 380 ), 381 piped = true, 382 writeIntRf = true, 383 writeFflags = true, 384 latency = CertainLatency(2), 385 needSrcFrm = true, 386 ) 387 388 val F2fCfg: FuConfig = FuConfig ( 389 name = "f2f", 390 fuType = FuType.fmisc, 391 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 392 srcData = Seq( 393 Seq(FpData(), FpData()), 394 Seq(FpData()), 395 ), 396 piped = true, 397 writeFpRf = true, 398 writeFflags = true, 399 latency = CertainLatency(2), 400 needSrcFrm = true, 401 ) 402 403 val FDivSqrtCfg: FuConfig = FuConfig ( 404 name = "fDivSqrt", 405 fuType = FuType.fDivSqrt, 406 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 407 srcData = Seq( 408 Seq(FpData(), FpData()), 409 ), 410 piped = false, 411 writeFpRf = true, 412 writeFflags = true, 413 latency = UncertainLatency(), 414 hasInputBuffer = (true, 8, true), 415 needSrcFrm = true, 416 ) 417 418 val LduCfg: FuConfig = FuConfig ( 419 name = "ldu", 420 fuType = FuType.ldu, 421 fuGen = null, // Todo 422 srcData = Seq( 423 Seq(IntData()), 424 ), 425 piped = false, // Todo: check it 426 writeIntRf = true, 427 writeFpRf = true, 428 latency = UncertainLatency(3), 429 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 430 flushPipe = true, 431 replayInst = true, 432 hasLoadError = true, 433 immType = Set(SelImm.IMM_I), 434 ) 435 436 val StaCfg: FuConfig = FuConfig ( 437 name = "sta", 438 fuType = FuType.stu, 439 fuGen = null, // Todo 440 srcData = Seq( 441 Seq(IntData()), 442 ), 443 piped = false, 444 latency = UncertainLatency(), 445 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 446 immType = Set(SelImm.IMM_S), 447 ) 448 449 val StdCfg: FuConfig = FuConfig ( 450 name = "std", 451 fuType = FuType.stu, 452 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 453 srcData = Seq( 454 Seq(IntData()), 455 Seq(FpData()), 456 ), 457 piped = true, 458 latency = CertainLatency(0) 459 ) 460 461 val HyldaCfg = FuConfig ( 462 name = "hylda", 463 fuType = FuType.ldu, 464 fuGen = null, // Todo 465 srcData = Seq( 466 Seq(IntData()), 467 ), 468 piped = false, // Todo: check it 469 writeIntRf = true, 470 writeFpRf = true, 471 latency = UncertainLatency(3), 472 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 473 flushPipe = true, 474 replayInst = true, 475 hasLoadError = true, 476 immType = Set(SelImm.IMM_I), 477 ) 478 479 val HystaCfg = FuConfig ( 480 name = "hysta", 481 fuType = FuType.stu, 482 fuGen = null, // Todo 483 srcData = Seq( 484 Seq(IntData()), 485 ), 486 piped = false, 487 latency = UncertainLatency(), 488 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 489 immType = Set(SelImm.IMM_S), 490 ) 491 492 val FakeHystaCfg = FuConfig ( 493 name = "hysta", 494 fuType = FuType.stu, 495 fuGen = null, // Todo 496 srcData = Seq(), 497 piped = false, 498 latency = UncertainLatency(), 499 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 500 immType = Set(), 501 ) 502 503 val MouCfg: FuConfig = FuConfig ( 504 name = "mou", 505 fuType = FuType.mou, 506 fuGen = null, // Todo 507 srcData = Seq( 508 Seq(IntData()), 509 ), 510 piped = false, // Todo: check it 511 writeIntRf = true, 512 latency = UncertainLatency(), 513 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct 514 ) 515 516 val MoudCfg: FuConfig = FuConfig ( 517 name = "moud", 518 fuType = FuType.mou, 519 fuGen = null, // Todo 520 srcData = Seq( 521 Seq(IntData()), 522 ), 523 piped = true, 524 latency = CertainLatency(0), 525 ) 526 527 val VialuCfg = FuConfig ( 528 name = "vialuFix", 529 fuType = FuType.vialuF, 530 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 531 srcData = Seq( 532 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 533 ), 534 piped = true, 535 writeVecRf = true, 536 writeVxsat = true, 537 latency = CertainLatency(1), 538 vconfigWakeUp = true, 539 maskWakeUp = true, 540 dataBits = 128, 541 exceptionOut = Seq(illegalInstr), 542 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 543 ) 544 545 val VimacCfg = FuConfig ( 546 name = "vimac", 547 fuType = FuType.vimac, 548 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 549 srcData = Seq( 550 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 551 ), 552 piped = true, 553 writeVecRf = true, 554 writeVxsat = true, 555 latency = CertainLatency(2), 556 vconfigWakeUp = true, 557 maskWakeUp = true, 558 dataBits = 128, 559 exceptionOut = Seq(illegalInstr), 560 ) 561 562 val VppuCfg = FuConfig ( 563 name = "vppu", 564 fuType = FuType.vppu, 565 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 566 srcData = Seq( 567 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 568 ), 569 piped = true, 570 writeVecRf = true, 571 writeVxsat = true, 572 latency = CertainLatency(1), 573 vconfigWakeUp = true, 574 maskWakeUp = true, 575 dataBits = 128, 576 exceptionOut = Seq(illegalInstr), 577 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 578 ) 579 580 val VipuCfg: FuConfig = FuConfig ( 581 name = "vipu", 582 fuType = FuType.vipu, 583 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 584 srcData = Seq( 585 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 586 ), 587 piped = true, 588 writeVecRf = true, 589 latency = CertainLatency(1), 590 vconfigWakeUp = true, 591 maskWakeUp = true, 592 dataBits = 128, 593 exceptionOut = Seq(illegalInstr), 594 ) 595 596 val VfaluCfg = FuConfig ( 597 name = "vfalu", 598 fuType = FuType.vfalu, 599 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 600 srcData = Seq( 601 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 602 ), 603 piped = true, 604 writeVecRf = true, 605 writeFpRf = true, 606 writeIntRf = true, 607 writeFflags = true, 608 latency = CertainLatency(1), 609 vconfigWakeUp = true, 610 maskWakeUp = true, 611 dataBits = 128, 612 exceptionOut = Seq(illegalInstr), 613 ) 614 615 val VfmaCfg = FuConfig ( 616 name = "vfma", 617 fuType = FuType.vfma, 618 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 619 srcData = Seq( 620 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 621 ), 622 piped = true, 623 writeVecRf = true, 624 writeFpRf = true, 625 writeFflags = true, 626 latency = CertainLatency(3), 627 vconfigWakeUp = true, 628 maskWakeUp = true, 629 dataBits = 128, 630 exceptionOut = Seq(illegalInstr), 631 ) 632 633 val VfdivCfg = FuConfig( 634 name = "vfdiv", 635 fuType = FuType.vfdiv, 636 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 637 srcData = Seq( 638 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 639 ), 640 piped = false, 641 writeVecRf = true, 642 writeFpRf = true, 643 writeFflags = true, 644 latency = UncertainLatency(), 645 vconfigWakeUp = true, 646 maskWakeUp = true, 647 dataBits = 128, 648 exceptionOut = Seq(illegalInstr), 649 ) 650 651 val VfcvtCfg = FuConfig( 652 name = "vfcvt", 653 fuType = FuType.vfcvt, 654 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 655 srcData = Seq( 656 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 657 ), 658 piped = true, 659 writeVecRf = true, 660 writeFpRf = false, 661 writeFflags = true, 662 latency = CertainLatency(2), 663 vconfigWakeUp = true, 664 maskWakeUp = true, 665 dataBits = 128, 666 exceptionOut = Seq(illegalInstr), 667 ) 668 669 670 val VlduCfg: FuConfig = FuConfig ( 671 name = "vldu", 672 fuType = FuType.vldu, 673 fuGen = null, 674 srcData = Seq( 675 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 676 ), 677 piped = false, // Todo: check it 678 writeVecRf = true, 679 latency = UncertainLatency(), 680 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 681 flushPipe = true, 682 replayInst = true, 683 hasLoadError = true, 684 vconfigWakeUp = true, 685 maskWakeUp = true, 686 dataBits = 128, 687 ) 688 689 val VstuCfg: FuConfig = FuConfig ( 690 name = "vstu", 691 fuType = FuType.vstu, 692 fuGen = null, 693 srcData = Seq( 694 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 695 ), 696 piped = false, 697 writeVecRf = false, 698 latency = UncertainLatency(), 699 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 700 flushPipe = true, 701 replayInst = true, 702 hasLoadError = true, 703 vconfigWakeUp = true, 704 maskWakeUp = true, 705 dataBits = 128, 706 ) 707 708 def allConfigs = Seq( 709 JmpCfg, BrhCfg, I2fCfg, I2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 710 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 711 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 712 ) 713 714 def VecArithFuConfigs = Seq( 715 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg 716 ) 717} 718 719