1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{ FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeV0Rf : Boolean = false, 54 writeVlRf : Boolean = false, 55 writeFakeIntRf: Boolean = false, 56 writeFflags : Boolean = false, 57 writeVxsat : Boolean = false, 58 dataBits : Int = 64, 59 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 60 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 61 exceptionOut : Seq[Int] = Seq(), 62 hasLoadError : Boolean = false, 63 flushPipe : Boolean = false, 64 replayInst : Boolean = false, 65 trigger : Boolean = false, 66 needSrcFrm : Boolean = false, 67 needSrcVxrm : Boolean = false, 68 writeVConfig : Boolean = false, 69 writeVType : Boolean = false, 70 immType : Set[UInt] = Set(), 71 // vector 72 vconfigWakeUp : Boolean = false, 73 maskWakeUp : Boolean = false, 74) { 75 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 76 def needFpWen: Boolean = writeFpRf 77 def needVecWen: Boolean = writeVecRf 78 def needV0Wen: Boolean = writeV0Rf 79 def needVlWen: Boolean = writeVlRf 80 var vconfigIdx = -1 81 var maskSrcIdx = -1 82 if (vconfigWakeUp) { 83 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 84 } 85 if (maskWakeUp) { 86 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 87 } 88 89 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 90 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 91 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 92 93 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 94 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 95 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 96 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 101 102 def readFp: Boolean = numFpSrc > 0 103 104 def fuSel(uop: ExuInput): Bool = { 105 // Don't add more shit here!!! 106 // Todo: add new FuType to distinguish f2i, f2f 107 uop.fuType === this.fuType.U 108 } 109 110 /** 111 * params(i): data type set of the ith src port 112 * @return 113 */ 114 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 115 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 116 // make srcData is uniform sized to avoid exception when transpose 117 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 118 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 119 } 120 121 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 122 srcData 123 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 124 .filter(_.nonEmpty) 125 .map(_.get) 126 .toSet 127 } 128 129 def hasNoDataWB: Boolean = { 130 !(writeIntRf || writeFpRf || writeVecRf) 131 } 132 133 def getSrcMaxWidthVec = { 134 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 135 } 136 137 def genSrcDataVec: Seq[UInt] = { 138 getSrcMaxWidthVec.map(w => UInt(w.W)) 139 } 140 141 // csr's redirect is in its exception bundle 142 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 143 144 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 145 146 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 147 148 // predict info 149 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 152 153 def needFPUCtrl: Boolean = { 154 import FuType._ 155 Seq(fmac, fDivSqrt, i2f).contains(fuType) 156 } 157 158 def needVecCtrl: Boolean = { 159 import FuType._ 160 Seq(falu, fmac, fDivSqrt, fcvt, 161 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 162 } 163 164 def isMul: Boolean = fuType == FuType.mul 165 166 def isDiv: Boolean = fuType == FuType.div 167 168 def isCsr: Boolean = fuType == FuType.csr 169 170 def isFence: Boolean = fuType == FuType.fence 171 172 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 173 fuType == FuType.vppu || fuType == FuType.vipu || 174 fuType == FuType.vfalu || fuType == FuType.vfma || 175 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 176 fuType == FuType.vidiv 177 178 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || fuType == FuType.f2v 179 180 def isSta: Boolean = name.contains("sta") 181 182 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 183 fuType == FuType.div || fuType == FuType.fDivSqrt || 184 fuType == FuType.vfdiv || fuType == FuType.vidiv 185 186 /** 187 * Get index of special src data, like [[VlData]], [[V0Data]] 188 * 189 * @param data [[DataConfig]] 190 * @param tips tips if get failed 191 * @return the index of special src data 192 */ 193 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 194 val srcIdxVec = srcData.map(x => x.indexOf(data)) 195 val idx0 = srcIdxVec.head 196 for (idx <- srcIdxVec) { 197 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 198 } 199 idx0 200 } 201 202 override def toString: String = { 203 var str = s"${this.name}: " 204 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 205 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 206 str += s"latency($latency)" 207 str += s"src($srcData)" 208 str 209 } 210} 211 212object FuConfig { 213 val JmpCfg: FuConfig = FuConfig ( 214 name = "jmp", 215 fuType = FuType.jmp, 216 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 217 srcData = Seq( 218 Seq(IntData()), // jal 219 ), 220 piped = true, 221 writeIntRf = true, 222 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 223 ) 224 225 val BrhCfg: FuConfig = FuConfig ( 226 name = "brh", 227 fuType = FuType.brh, 228 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 229 srcData = Seq( 230 Seq(IntData(), IntData()), 231 ), 232 piped = true, 233 immType = Set(SelImm.IMM_SB), 234 ) 235 236 val I2fCfg: FuConfig = FuConfig ( 237 name = "i2f", 238 FuType.i2f, 239 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 240 srcData = Seq( 241 Seq(IntData()), 242 ), 243 piped = true, 244 writeFpRf = true, 245 writeFflags = true, 246 latency = CertainLatency(2), 247 needSrcFrm = true, 248 ) 249 250 val I2vCfg: FuConfig = FuConfig ( 251 name = "i2v", 252 FuType.i2v, 253 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 254 srcData = Seq( 255 Seq(IntData(), IntData()), 256 ), 257 piped = true, 258 writeFpRf = true, 259 writeVecRf = true, 260 latency = CertainLatency(0), 261 dataBits = 128, 262 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 263 ) 264 265 val F2vCfg: FuConfig = FuConfig ( 266 name = "f2v", 267 FuType.f2v, 268 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 269 srcData = Seq( 270 Seq(FpData(), FpData()), 271 Seq(FpData()), 272 ), 273 piped = true, 274 writeVecRf = true, 275 latency = CertainLatency(0), 276 dataBits = 128, 277 ) 278 279 val CsrCfg: FuConfig = FuConfig ( 280 name = "csr", 281 fuType = FuType.csr, 282 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 283 srcData = Seq( 284 Seq(IntData()), 285 ), 286 piped = true, 287 writeIntRf = true, 288 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 289 flushPipe = true, 290 ) 291 292 val AluCfg: FuConfig = FuConfig ( 293 name = "alu", 294 fuType = FuType.alu, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 296 srcData = Seq( 297 Seq(IntData(), IntData()), 298 ), 299 piped = true, 300 writeIntRf = true, 301 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 302 ) 303 304 val MulCfg: FuConfig = FuConfig ( 305 name = "mul", 306 fuType = FuType.mul, 307 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 308 srcData = Seq( 309 Seq(IntData(), IntData()), 310 ), 311 piped = true, 312 writeIntRf = true, 313 latency = CertainLatency(2), 314 ) 315 316 val DivCfg: FuConfig = FuConfig ( 317 name = "div", 318 fuType = FuType.div, 319 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 320 srcData = Seq( 321 Seq(IntData(), IntData()), 322 ), 323 piped = false, 324 writeIntRf = true, 325 latency = UncertainLatency(), 326 hasInputBuffer = (true, 4, true) 327 ) 328 329 val FenceCfg: FuConfig = FuConfig ( 330 name = "fence", 331 FuType.fence, 332 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 333 srcData = Seq( 334 Seq(IntData(), IntData()), 335 ), 336 piped = true, 337 latency = CertainLatency(0), 338 exceptionOut = Seq(illegalInstr, virtualInstr), 339 flushPipe = true 340 ) 341 342 // Todo: split it to simple bitmap exu and complex bku 343 val BkuCfg: FuConfig = FuConfig ( 344 name = "bku", 345 fuType = FuType.bku, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 347 srcData = Seq( 348 Seq(IntData(), IntData()), 349 ), 350 piped = true, 351 writeIntRf = true, 352 latency = CertainLatency(2), 353 ) 354 355 val VSetRvfWvfCfg: FuConfig = FuConfig( 356 name = "vsetrvfwvf", 357 fuType = FuType.vsetfwf, 358 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 359 srcData = Seq( 360 Seq(VecData(), VecData()), 361 ), 362 piped = true, 363 writeVecRf = true, 364 writeVConfig = true, 365 writeVType = true, 366 latency = CertainLatency(0), 367 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 368 ) 369 370 val VSetRiWvfCfg: FuConfig = FuConfig( 371 name = "vsetriwvf", 372 fuType = FuType.vsetiwf, 373 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 374 srcData = Seq( 375 Seq(IntData(), IntData()), 376 ), 377 piped = true, 378 writeVecRf = true, 379 writeVConfig = true, 380 writeVType = true, 381 latency = CertainLatency(0), 382 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 383 ) 384 385 val VSetRiWiCfg: FuConfig = FuConfig( 386 name = "vsetriwi", 387 fuType = FuType.vsetiwi, 388 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 389 srcData = Seq( 390 Seq(IntData(), IntData()), 391 ), 392 piped = true, 393 writeIntRf = true, 394 latency = CertainLatency(0), 395 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 396 ) 397 398 val LduCfg: FuConfig = FuConfig ( 399 name = "ldu", 400 fuType = FuType.ldu, 401 fuGen = null, // Todo 402 srcData = Seq( 403 Seq(IntData()), 404 ), 405 piped = false, // Todo: check it 406 writeIntRf = true, 407 writeFpRf = true, 408 latency = UncertainLatency(3), 409 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 410 flushPipe = true, 411 replayInst = true, 412 hasLoadError = true, 413 trigger = true, 414 immType = Set(SelImm.IMM_I), 415 ) 416 417 val StaCfg: FuConfig = FuConfig ( 418 name = "sta", 419 fuType = FuType.stu, 420 fuGen = null, // Todo 421 srcData = Seq( 422 Seq(IntData()), 423 ), 424 piped = false, 425 latency = UncertainLatency(), 426 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 427 trigger = true, 428 immType = Set(SelImm.IMM_S), 429 ) 430 431 val StdCfg: FuConfig = FuConfig ( 432 name = "std", 433 fuType = FuType.stu, 434 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 435 srcData = Seq( 436 Seq(IntData()), 437 Seq(FpData()), 438 ), 439 piped = true, 440 latency = CertainLatency(0) 441 ) 442 443 val HyldaCfg = FuConfig ( 444 name = "hylda", 445 fuType = FuType.ldu, 446 fuGen = null, // Todo 447 srcData = Seq( 448 Seq(IntData()), 449 ), 450 piped = false, // Todo: check it 451 writeIntRf = true, 452 writeFpRf = true, 453 latency = UncertainLatency(3), 454 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 455 flushPipe = true, 456 replayInst = true, 457 hasLoadError = true, 458 immType = Set(SelImm.IMM_I), 459 ) 460 461 val HystaCfg = FuConfig ( 462 name = "hysta", 463 fuType = FuType.stu, 464 fuGen = null, // Todo 465 srcData = Seq( 466 Seq(IntData()), 467 ), 468 piped = false, 469 latency = UncertainLatency(), 470 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 471 immType = Set(SelImm.IMM_S), 472 ) 473 474 val FakeHystaCfg = FuConfig ( 475 name = "hysta", 476 fuType = FuType.stu, 477 fuGen = null, // Todo 478 srcData = Seq(), 479 piped = false, 480 latency = UncertainLatency(), 481 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 482 immType = Set(), 483 ) 484 485 val MouCfg: FuConfig = FuConfig ( 486 name = "mou", 487 fuType = FuType.mou, 488 fuGen = null, // Todo 489 srcData = Seq( 490 Seq(IntData()), 491 ), 492 piped = false, // Todo: check it 493 writeFakeIntRf = true, 494 latency = UncertainLatency(), 495 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 496 trigger = true, 497 ) 498 499 val MoudCfg: FuConfig = FuConfig ( 500 name = "moud", 501 fuType = FuType.mou, 502 fuGen = null, // Todo 503 srcData = Seq( 504 Seq(IntData()), 505 ), 506 piped = true, 507 latency = CertainLatency(0), 508 ) 509 510 val VialuCfg = FuConfig ( 511 name = "vialuFix", 512 fuType = FuType.vialuF, 513 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 514 srcData = Seq( 515 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 516 ), 517 piped = true, 518 writeVecRf = true, 519 writeVxsat = true, 520 needSrcVxrm = true, 521 latency = CertainLatency(1), 522 vconfigWakeUp = true, 523 maskWakeUp = true, 524 dataBits = 128, 525 exceptionOut = Seq(illegalInstr), 526 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 527 ) 528 529 val VimacCfg = FuConfig ( 530 name = "vimac", 531 fuType = FuType.vimac, 532 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 533 srcData = Seq( 534 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 535 ), 536 piped = true, 537 writeVecRf = true, 538 writeVxsat = true, 539 needSrcVxrm = true, 540 latency = CertainLatency(2), 541 vconfigWakeUp = true, 542 maskWakeUp = true, 543 dataBits = 128, 544 exceptionOut = Seq(illegalInstr), 545 ) 546 547 val VidivCfg = FuConfig ( 548 name = "vidiv", 549 fuType = FuType.vidiv, 550 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 551 srcData = Seq( 552 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 553 ), 554 piped = false, 555 writeVecRf = true, 556 latency = UncertainLatency(), 557 vconfigWakeUp = true, 558 maskWakeUp = true, 559 dataBits = 128, 560 exceptionOut = Seq(illegalInstr), 561 ) 562 563 val VppuCfg = FuConfig ( 564 name = "vppu", 565 fuType = FuType.vppu, 566 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 567 srcData = Seq( 568 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 569 ), 570 piped = true, 571 writeVecRf = true, 572 latency = CertainLatency(2), 573 vconfigWakeUp = true, 574 maskWakeUp = true, 575 dataBits = 128, 576 exceptionOut = Seq(illegalInstr), 577 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 578 ) 579 580 val VipuCfg: FuConfig = FuConfig ( 581 name = "vipu", 582 fuType = FuType.vipu, 583 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 584 srcData = Seq( 585 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 586 ), 587 piped = true, 588 writeIntRf = true, 589 writeVecRf = true, 590 latency = CertainLatency(2), 591 vconfigWakeUp = true, 592 maskWakeUp = true, 593 dataBits = 128, 594 exceptionOut = Seq(illegalInstr), 595 ) 596 597 val VfaluCfg = FuConfig ( 598 name = "vfalu", 599 fuType = FuType.vfalu, 600 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 601 srcData = Seq( 602 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 603 ), 604 piped = true, 605 writeVecRf = true, 606 writeFpRf = true, 607 writeFflags = true, 608 latency = CertainLatency(1), 609 vconfigWakeUp = true, 610 maskWakeUp = true, 611 dataBits = 128, 612 exceptionOut = Seq(illegalInstr), 613 needSrcFrm = true, 614 ) 615 616 val VfmaCfg = FuConfig ( 617 name = "vfma", 618 fuType = FuType.vfma, 619 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 620 srcData = Seq( 621 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 622 ), 623 piped = true, 624 writeVecRf = true, 625 writeFflags = true, 626 latency = CertainLatency(3), 627 vconfigWakeUp = true, 628 maskWakeUp = true, 629 dataBits = 128, 630 exceptionOut = Seq(illegalInstr), 631 needSrcFrm = true, 632 ) 633 634 val VfdivCfg = FuConfig( 635 name = "vfdiv", 636 fuType = FuType.vfdiv, 637 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 638 srcData = Seq( 639 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 640 ), 641 piped = false, 642 writeVecRf = true, 643 writeFflags = true, 644 latency = UncertainLatency(), 645 vconfigWakeUp = true, 646 maskWakeUp = true, 647 dataBits = 128, 648 exceptionOut = Seq(illegalInstr), 649 needSrcFrm = true, 650 ) 651 652 val VfcvtCfg = FuConfig( 653 name = "vfcvt", 654 fuType = FuType.vfcvt, 655 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 656 srcData = Seq( 657 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 658 ), 659 piped = true, 660 writeVecRf = true, 661 writeFflags = true, 662 latency = CertainLatency(2), 663 vconfigWakeUp = true, 664 maskWakeUp = true, 665 dataBits = 128, 666 exceptionOut = Seq(illegalInstr), 667 needSrcFrm = true, 668 ) 669 670 val FaluCfg = FuConfig( 671 name = "falu", 672 fuType = FuType.falu, 673 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 674 srcData = Seq( 675 Seq(FpData(), FpData()), 676 ), 677 piped = true, 678 writeFpRf = true, 679 writeIntRf = true, 680 writeFflags = true, 681 latency = CertainLatency(1), 682 dataBits = 64, 683 needSrcFrm = true, 684 ) 685 686 val FmacCfg = FuConfig( 687 name = "fmac", 688 fuType = FuType.fmac, 689 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 690 srcData = Seq( 691 Seq(FpData(), FpData(), FpData()), 692 ), 693 piped = true, 694 writeFpRf = true, 695 writeFflags = true, 696 latency = CertainLatency(3), 697 dataBits = 64, 698 needSrcFrm = true, 699 ) 700 701 val FdivCfg = FuConfig( 702 name = "fdiv", 703 fuType = FuType.fDivSqrt, 704 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 705 srcData = Seq( 706 Seq(FpData(), FpData()), 707 ), 708 piped = false, 709 writeFpRf = true, 710 writeFflags = true, 711 latency = UncertainLatency(), 712 dataBits = 64, 713 needSrcFrm = true, 714 ) 715 716 val FcvtCfg = FuConfig( 717 name = "fcvt", 718 fuType = FuType.fcvt, 719 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 720 srcData = Seq( 721 Seq(FpData()), 722 ), 723 piped = true, 724 writeFpRf = true, 725 writeIntRf = true, 726 writeFflags = true, 727 latency = CertainLatency(2), 728 dataBits = 64, 729 needSrcFrm = true, 730 ) 731 732 val VlduCfg: FuConfig = FuConfig ( 733 name = "vldu", 734 fuType = FuType.vldu, 735 fuGen = null, 736 srcData = Seq( 737 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 738 ), 739 piped = false, // Todo: check it 740 writeVecRf = true, 741 latency = UncertainLatency(), 742 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 743 flushPipe = true, 744 replayInst = true, 745 hasLoadError = true, 746 vconfigWakeUp = true, 747 maskWakeUp = true, 748 dataBits = 128, 749 ) 750 751 val VstuCfg: FuConfig = FuConfig ( 752 name = "vstu", 753 fuType = FuType.vstu, 754 fuGen = null, 755 srcData = Seq( 756 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 757 ), 758 piped = false, 759 writeVecRf = false, 760 latency = UncertainLatency(), 761 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 762 flushPipe = true, 763 replayInst = true, 764 hasLoadError = true, 765 vconfigWakeUp = true, 766 maskWakeUp = true, 767 dataBits = 128, 768 ) 769 770 val VseglduSeg: FuConfig = FuConfig ( 771 name = "vsegldu", 772 fuType = FuType.vsegldu, 773 fuGen = null, 774 srcData = Seq( 775 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 776 ), 777 piped = false, // Todo: check it 778 writeVecRf = true, 779 latency = UncertainLatency(), 780 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 781 flushPipe = true, 782 replayInst = true, 783 hasLoadError = true, 784 vconfigWakeUp = true, 785 maskWakeUp = true, 786 dataBits = 128, 787 ) 788 789 val VsegstuCfg: FuConfig = FuConfig( 790 name = "vsegstu", 791 fuType = FuType.vsegstu, 792 fuGen = null, 793 srcData = Seq( 794 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 795 ), 796 piped = false, 797 writeVecRf = false, 798 latency = UncertainLatency(), 799 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 800 flushPipe = true, 801 replayInst = true, 802 hasLoadError = true, 803 vconfigWakeUp = true, 804 maskWakeUp = true, 805 dataBits = 128, 806 ) 807 808 def allConfigs = Seq( 809 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 810 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 811 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 812 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 813 ) 814 815 def VecArithFuConfigs = Seq( 816 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 817 ) 818} 819 820