1c6d43980SLemover/*************************************************************************************** 2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory 4c6d43980SLemover* 5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2. 6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2. 7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at: 8c6d43980SLemover* http://license.coscl.org.cn/MulanPSL2 9c6d43980SLemover* 10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13c6d43980SLemover* 14c6d43980SLemover* See the Mulan PSL v2 for more details. 15c6d43980SLemover***************************************************************************************/ 16c6d43980SLemover 17cafb3558SLinJiaweipackage xiangshan.backend.fu 18cafb3558SLinJiawei 192225d46eSJiawei Linimport chipsalliance.rocketchip.config.Parameters 20cafb3558SLinJiaweiimport chisel3._ 21cafb3558SLinJiaweiimport chisel3.util._ 221a2cf152SYinan Xuimport utils.XSPerfAccumulate 23cafb3558SLinJiaweiimport xiangshan._ 24e18c367fSLinJiaweiimport xiangshan.backend.fu.fpu._ 25cafb3558SLinJiawei 263e60a357SLinJiaweitrait HasFuLatency { 273e60a357SLinJiawei val latencyVal: Option[Int] 28*23c67001SHaojin Tang val uncertainLatencyVal: Option[Int] 293e60a357SLinJiawei} 303e60a357SLinJiawei 313e60a357SLinJiaweicase class CertainLatency(value: Int) extends HasFuLatency { 323e60a357SLinJiawei override val latencyVal: Option[Int] = Some(value) 33*23c67001SHaojin Tang override val uncertainLatencyVal: Option[Int] = None 343e60a357SLinJiawei} 353e60a357SLinJiawei 36*23c67001SHaojin Tangcase class UncertainLatency(value: Option[Int]) extends HasFuLatency { 373e60a357SLinJiawei override val latencyVal: Option[Int] = None 38*23c67001SHaojin Tang override val uncertainLatencyVal: Option[Int] = value 39*23c67001SHaojin Tang} 40*23c67001SHaojin Tang 41*23c67001SHaojin Tangobject UncertainLatency { 42*23c67001SHaojin Tang def apply(): UncertainLatency = UncertainLatency(None) 43*23c67001SHaojin Tang def apply(value: Int): UncertainLatency = UncertainLatency(Some(value)) 443e60a357SLinJiawei} 453e60a357SLinJiawei 462225d46eSJiawei Linclass FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 47e50fb2d7SLinJiawei val data = UInt(len.W) 48e18c367fSLinJiawei val uop = new MicroOp 49e18c367fSLinJiawei} 50e18c367fSLinJiawei 516cdd85d9SYinan Xuclass FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 5252c3f215SLinJiawei val src = Vec(3, UInt(len.W)) 5314521086SLinJiawei val uop = new MicroOp 546cdd85d9SYinan Xu} 556cdd85d9SYinan Xu 566cdd85d9SYinan Xuclass FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 576cdd85d9SYinan Xu val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 58ead41f51SLinJiawei 59e50fb2d7SLinJiawei val out = DecoupledIO(new FuOutput(len)) 60ead41f51SLinJiawei 6114521086SLinJiawei val redirectIn = Flipped(ValidIO(new Redirect)) 6214521086SLinJiawei} 6314521086SLinJiawei 642225d46eSJiawei Linabstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 6514521086SLinJiawei 6652c3f215SLinJiawei val io = IO(new FunctionUnitIO(len)) 6714521086SLinJiawei 681a2cf152SYinan Xu XSPerfAccumulate("in_valid", io.in.valid) 691a2cf152SYinan Xu XSPerfAccumulate("in_fire", io.in.fire) 701a2cf152SYinan Xu XSPerfAccumulate("out_valid", io.out.valid) 711a2cf152SYinan Xu XSPerfAccumulate("out_fire", io.out.fire) 721a2cf152SYinan Xu 7314521086SLinJiawei} 74