xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision 68c44d2d2e8497ec416de2080de6d6d81b8783af)
1cafb3558SLinJiaweipackage xiangshan.backend.fu
2cafb3558SLinJiawei
3cafb3558SLinJiaweiimport chisel3._
4cafb3558SLinJiaweiimport chisel3.util._
5cafb3558SLinJiawei
6cafb3558SLinJiaweiimport xiangshan._
7b9fd1892SLinJiaweiimport utils._
8cafb3558SLinJiawei
9cafb3558SLinJiaweiimport FunctionUnit._
10cafb3558SLinJiawei
11cafb3558SLinJiawei/*
12cafb3558SLinJiawei    XiangShan Function Unit
13cafb3558SLinJiawei    A Exu can have one or more function units
14cafb3558SLinJiawei */
15cafb3558SLinJiawei
16cafb3558SLinJiaweicase class FuConfig
17cafb3558SLinJiawei(
18cafb3558SLinJiawei  fuType: UInt,
19cafb3558SLinJiawei  numIntSrc: Int,
20cafb3558SLinJiawei  numFpSrc: Int,
21cafb3558SLinJiawei  writeIntRf: Boolean,
22cafb3558SLinJiawei  writeFpRf: Boolean,
23cafb3558SLinJiawei  hasRedirect: Boolean
24cafb3558SLinJiawei)
25cafb3558SLinJiawei
26c84054caSLinJiaweiclass FunctionUnitIO extends XSBundle {
27c84054caSLinJiawei  val in = Flipped(Decoupled(new Bundle {
28c84054caSLinJiawei    val src1 = Output(UInt(XLEN.W))
29c84054caSLinJiawei    val src2 = Output(UInt(XLEN.W))
30c84054caSLinJiawei    val src3 = Output(UInt(XLEN.W))
31c84054caSLinJiawei    val func = Output(FuOpType())
32c84054caSLinJiawei  }))
33c84054caSLinJiawei  val out = Decoupled(Output(UInt(XLEN.W)))
34c84054caSLinJiawei}
35c84054caSLinJiawei
36cafb3558SLinJiaweiabstract class FunctionUnit(cfg: FuConfig) extends XSModule
37cafb3558SLinJiawei
38cafb3558SLinJiaweiobject FunctionUnit {
39c84054caSLinJiawei
40c84054caSLinJiawei  val csrCfg =
41c84054caSLinJiawei    FuConfig(FuType.csr, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
42c84054caSLinJiawei
43cafb3558SLinJiawei  val jmpCfg =
44cafb3558SLinJiawei    FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
45cafb3558SLinJiawei
46cafb3558SLinJiawei  val i2fCfg =
47cafb3558SLinJiawei    FuConfig(FuType.i2f, 1, 0, writeIntRf = false, writeFpRf = true, hasRedirect = false)
48cafb3558SLinJiawei
49cafb3558SLinJiawei  val aluCfg =
50cafb3558SLinJiawei    FuConfig(FuType.alu, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
51cafb3558SLinJiawei
52cafb3558SLinJiawei  val mulCfg =
53cafb3558SLinJiawei    FuConfig(FuType.mul, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
54cafb3558SLinJiawei
55cafb3558SLinJiawei  val divCfg =
56cafb3558SLinJiawei    FuConfig(FuType.div, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
57cafb3558SLinJiawei
58b8f08ca0SZhangZifei  val fenceCfg =
59b8f08ca0SZhangZifei    FuConfig(FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false/*NOTE: need redirect but when commit*/)
60b8f08ca0SZhangZifei
616624015fSLinJiawei  val lduCfg =
62c4459445SLinJiawei    FuConfig(FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false)
636624015fSLinJiawei
646624015fSLinJiawei  val stuCfg =
656624015fSLinJiawei    FuConfig(FuType.stu, 2, 1, writeIntRf = false, writeFpRf = false, hasRedirect = false)
66cafb3558SLinJiawei
67*68c44d2dSAllen  // use ldu's write back port, so set writeIntRf to false
68*68c44d2dSAllen  val mouCfg =
69*68c44d2dSAllen    FuConfig(FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false)
70*68c44d2dSAllen
71cafb3558SLinJiawei  val fmacCfg =
72cafb3558SLinJiawei    FuConfig(FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false)
73cafb3558SLinJiawei
74cafb3558SLinJiawei  val fmiscCfg =
75cafb3558SLinJiawei    FuConfig(FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)
76cafb3558SLinJiawei
77cafb3558SLinJiawei  val fDivSqrtCfg =
78cafb3558SLinJiawei    FuConfig(FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)
79cafb3558SLinJiawei}
80