1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28} 29 30case class CertainLatency(value: Int) extends HasFuLatency { 31 override val latencyVal: Option[Int] = Some(value) 32} 33 34case class UncertainLatency() extends HasFuLatency { 35 override val latencyVal: Option[Int] = None 36} 37 38 39//case class FuConfig 40//( 41// name: String, 42// fuGen: Parameters => FunctionUnit, 43// fuSel: MicroOp => Bool, 44// fuType: UInt, 45// numIntSrc: Int, 46// numFpSrc: Int, 47// numVecSrc: Int = 0, 48// writeIntRf: Boolean, 49// writeFpRf: Boolean, 50// writeVecRf: Boolean = false, 51// writeFflags: Boolean = false, 52// hasRedirect: Boolean = false, 53// latency: HasFuLatency = CertainLatency(0), 54// fastUopOut: Boolean = false, 55// fastImplemented: Boolean = false, 56// hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57// exceptionOut: Seq[Int] = Seq(), 58// hasLoadError: Boolean = false, 59// flushPipe: Boolean = false, 60// replayInst: Boolean = false, 61// trigger: Boolean = false 62//) { 63// def srcCnt: Int = math.max(math.max(numIntSrc, numFpSrc), numVecSrc) 64// def isVectorFU: Boolean = (numVecSrc > 0) && writeVecRf 65// 66// override def toString: String = { 67// s"${name}: SrcNum(${numIntSrc}|${numFpSrc}|${numVecSrc}) " + 68// s"Write(" + 69// (if(writeIntRf) "int|" else "") + 70// (if(writeFpRf) "fp|" else "") + 71// (if(writeVecRf) "vec|" else "") + 72// (if(writeFflags) "fflags" else "") + 73// (if(!writeIntRf && !writeFpRf && !writeVecRf && !writeFflags) "none" else "") + ") " + 74// (if(hasRedirect) "hasRedirect " else "") + 75// (if(latency.latencyVal.getOrElse(99) != 99) "latency " + latency.latencyVal.get+" " else "") + 76// (if(fastUopOut) "hasFastUopOut " else "") + 77// s"inputBuffer (${hasInputBuffer._1},${hasInputBuffer._2},${hasInputBuffer._3}) " 78// } 79//} 80 81 82class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 83 val data = UInt(len.W) 84 val uop = new MicroOp 85} 86 87class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 88 val src = Vec(3, UInt(len.W)) 89 val uop = new MicroOp 90} 91 92class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 93 val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 94 95 val out = DecoupledIO(new FuOutput(len)) 96 97 val redirectIn = Flipped(ValidIO(new Redirect)) 98} 99 100abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 101 102 val io = IO(new FunctionUnitIO(len)) 103 104 XSPerfAccumulate("in_valid", io.in.valid) 105 XSPerfAccumulate("in_fire", io.in.fire) 106 XSPerfAccumulate("out_valid", io.out.valid) 107 XSPerfAccumulate("out_fire", io.out.fire) 108 109} 110 111//abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut 112// 113//trait HasPipelineReg { 114// this: FunctionUnit => 115// 116// def latency: Int 117// 118// require(latency > 0) 119// 120// val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 121// val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B) 122// val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp)) 123// 124// 125// // if flush(0), valid 0 will not given, so set flushVec(0) to false.B 126// val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.robIdx.needFlush(io.redirectIn)) 127// 128// for (i <- 0 until latency - 1) { 129// rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1) 130// } 131// 132// for (i <- 1 to latency) { 133// when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){ 134// validVec(i) := validVec(i - 1) 135// uopVec(i) := uopVec(i - 1) 136// }.elsewhen(flushVec(i) || rdyVec(i)){ 137// validVec(i) := false.B 138// } 139// } 140// 141// io.in.ready := rdyVec(0) 142// io.out.valid := validVec.takeRight(2).head 143// io.out.bits.uop := uopVec.takeRight(2).head 144// 145// def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1) 146// 147// def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable( 148// next, 149// regEnable(i) 150// ) 151// 152// def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next) 153// 154// def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next) 155// 156// def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next) 157// 158// def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next) 159// 160// def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next) 161//} 162