xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision 95bfe4c03ef37cfa7866474159f6afb8e3bcc3cc) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5
6import xiangshan._
7import utils._
8
9import FunctionUnit._
10
11/*
12    XiangShan Function Unit
13    A Exu can have one or more function units
14 */
15
16case class FuConfig
17(
18  fuType: UInt,
19  numIntSrc: Int,
20  numFpSrc: Int,
21  writeIntRf: Boolean,
22  writeFpRf: Boolean,
23  hasRedirect: Boolean
24)
25
26class FunctionUnitIO extends XSBundle {
27  val in = Flipped(Decoupled(new Bundle {
28    val src1 = Output(UInt(XLEN.W))
29    val src2 = Output(UInt(XLEN.W))
30    val src3 = Output(UInt(XLEN.W))
31    val func = Output(FuOpType())
32  }))
33  val out = Decoupled(Output(UInt(XLEN.W)))
34}
35
36abstract class FunctionUnit(cfg: FuConfig) extends XSModule
37
38object FunctionUnit {
39
40  val csrCfg =
41    FuConfig(FuType.csr, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
42
43  val jmpCfg =
44    FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
45
46  val i2fCfg =
47    FuConfig(FuType.i2f, 1, 0, writeIntRf = false, writeFpRf = true, hasRedirect = false)
48
49  val aluCfg =
50    FuConfig(FuType.alu, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
51
52  val mulCfg =
53    FuConfig(FuType.mul, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
54
55  val divCfg =
56    FuConfig(FuType.div, 2, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
57
58  val fenceCfg =
59    FuConfig(FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false/*NOTE: need redirect but when commit*/)
60
61  val lduCfg =
62    FuConfig(FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false)
63
64  val stuCfg =
65    FuConfig(FuType.stu, 2, 1, writeIntRf = false, writeFpRf = false, hasRedirect = false)
66
67  // use ldu's write back port, so set writeIntRf to false
68  val mouCfg =
69    FuConfig(FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false)
70
71  val fmacCfg =
72    FuConfig(FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false)
73
74  val fmiscCfg =
75    FuConfig(FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)
76
77  val fDivSqrtCfg =
78    FuConfig(FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)
79}
80