xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision f7063a43ab34da917ba6c670d21871314340c550) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils.XSPerfAccumulate
23import xiangshan._
24import xiangshan.backend.fu.fpu._
25
26trait HasFuLatency {
27  val latencyVal: Option[Int]
28  val extraLatencyVal: Option[Int]
29  val uncertainLatencyVal: Option[Int]
30}
31
32case class CertainLatency(value: Int, extraValue: Int = 0) extends HasFuLatency {
33  override val latencyVal: Option[Int] = Some(value + extraValue)
34  override val extraLatencyVal: Option[Int] = Some(extraValue)
35  override val uncertainLatencyVal: Option[Int] = None
36}
37
38case class UncertainLatency(value: Option[Int]) extends HasFuLatency {
39  override val latencyVal: Option[Int] = None
40  override val extraLatencyVal: Option[Int] = None
41  override val uncertainLatencyVal: Option[Int] = value
42}
43
44object UncertainLatency {
45  def apply(): UncertainLatency = UncertainLatency(None)
46  def apply(value: Int): UncertainLatency = UncertainLatency(Some(value))
47}
48
49class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
50  val data = UInt(len.W)
51  val uop = new MicroOp
52}
53
54class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle {
55  val src = Vec(3, UInt(len.W))
56  val uop = new MicroOp
57}
58
59class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
60  val in = Flipped(DecoupledIO(new FunctionUnitInput(len)))
61
62  val out = DecoupledIO(new FuOutput(len))
63
64  val redirectIn = Flipped(ValidIO(new Redirect))
65}
66
67abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
68
69  val io = IO(new FunctionUnitIO(len))
70
71  XSPerfAccumulate("in_valid", io.in.valid)
72  XSPerfAccumulate("in_fire", io.in.fire)
73  XSPerfAccumulate("out_valid", io.out.valid)
74  XSPerfAccumulate("out_fire", io.out.fire)
75
76}
77