xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala (revision d8a66f7ecacc2b3538a1083b0716b7066c77ba3f) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import xiangshan.backend._
8import xiangshan.backend.decode.ImmUnion
9import xiangshan.backend.fu.FunctionUnit._
10import xiangshan.backend.decode.isa._
11
12trait HasRedirectOut { this: RawModule =>
13  val redirectOutValid = IO(Output(Bool()))
14  val redirectOut = IO(Output(new Redirect))
15}
16
17class Jump extends FunctionUnit with HasRedirectOut {
18
19  val (src1, jalr_target, pc, immMin, func, uop) = (
20    io.in.bits.src(0),
21    io.in.bits.src(1)(VAddrBits - 1, 0),
22    SignExt(io.in.bits.uop.cf.pc, XLEN),
23    io.in.bits.uop.ctrl.imm,
24    io.in.bits.uop.ctrl.fuOpType,
25    io.in.bits.uop
26  )
27
28  val isJalr = JumpOpType.jumpOpisJalr(func)
29  val isAuipc = JumpOpType.jumpOpisAuipc(func)
30  val offset = SignExt(ParallelMux(Seq(
31    isJalr -> ImmUnion.I.toImm32(immMin),
32    isAuipc -> ImmUnion.U.toImm32(immMin),
33    !(isJalr || isAuipc) -> ImmUnion.J.toImm32(immMin)
34  )), XLEN)
35
36  val redirectHit = uop.roqIdx.needFlush(io.redirectIn, io.flushIn)
37  val valid = io.in.valid
38
39  val isRVC = uop.cf.pd.isRVC
40  val snpc = Mux(isRVC, pc + 2.U, pc + 4.U)
41  val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
42
43  redirectOutValid := valid && !isAuipc
44  redirectOut := DontCare
45  redirectOut.cfiUpdate.target := target
46  redirectOut.level := RedirectLevel.flushAfter
47  redirectOut.roqIdx := uop.roqIdx
48  redirectOut.ftqIdx := uop.cf.ftqPtr
49  redirectOut.ftqOffset := uop.cf.ftqOffset
50  redirectOut.cfiUpdate.predTaken := true.B
51  redirectOut.cfiUpdate.taken := true.B
52  redirectOut.cfiUpdate.target := target
53  redirectOut.cfiUpdate.isMisPred := target =/= jalr_target || !uop.cf.pred_taken
54
55
56  // Output
57  val res = Mux(JumpOpType.jumpOpisAuipc(func), target, snpc)
58
59  io.in.ready := io.out.ready
60  io.out.valid := valid
61  io.out.bits.uop <> io.in.bits.uop
62  io.out.bits.data := res
63
64  // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
65  XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d)\n",
66    io.in.valid,
67    io.in.ready,
68    io.out.valid,
69    io.out.ready,
70    io.redirectIn.valid,
71    io.redirectIn.bits.level,
72    redirectHit
73  )
74  XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res)
75}
76