10bca6cb3SZiyue Zhangpackage xiangshan.backend.fu.wrapper 20bca6cb3SZiyue Zhang 30bca6cb3SZiyue Zhangimport org.chipsalliance.cde.config.Parameters 40bca6cb3SZiyue Zhangimport chisel3._ 50bca6cb3SZiyue Zhangimport chisel3.util._ 6*bb2f3f51STang Haojinimport utility.XSError 70bca6cb3SZiyue Zhangimport xiangshan.backend.fu.FuConfig 80bca6cb3SZiyue Zhangimport xiangshan.backend.fu.vector.Bundles.VSew 90bca6cb3SZiyue Zhangimport xiangshan.backend.fu.vector.{Mgu, VecNonPipedFuncUnit} 100bca6cb3SZiyue Zhangimport xiangshan.backend.rob.RobPtr 110bca6cb3SZiyue Zhangimport xiangshan.ExceptionNO 120bca6cb3SZiyue Zhangimport yunsuan.VidivType 130bca6cb3SZiyue Zhangimport yunsuan.vector.VectorIdiv 140bca6cb3SZiyue Zhang 150bca6cb3SZiyue Zhangclass VIDiv(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(cfg) { 160bca6cb3SZiyue Zhang XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VidivType.dummy, "Vfdiv OpType not supported") 170bca6cb3SZiyue Zhang 180bca6cb3SZiyue Zhang // params alias 192d12882cSxiaofeibao private val dataWidth = cfg.destDataBits 200bca6cb3SZiyue Zhang 210bca6cb3SZiyue Zhang // modules 220bca6cb3SZiyue Zhang private val vidiv = Module(new VectorIdiv) 230bca6cb3SZiyue Zhang private val mgu = Module(new Mgu(dataWidth)) 240bca6cb3SZiyue Zhang 250bca6cb3SZiyue Zhang private val thisRobIdx = Wire(new RobPtr) 260bca6cb3SZiyue Zhang when(io.in.ready){ 270bca6cb3SZiyue Zhang thisRobIdx := io.in.bits.ctrl.robIdx 280bca6cb3SZiyue Zhang }.otherwise{ 290bca6cb3SZiyue Zhang thisRobIdx := outCtrl.robIdx 300bca6cb3SZiyue Zhang } 310bca6cb3SZiyue Zhang 320bca6cb3SZiyue Zhang /** 330bca6cb3SZiyue Zhang * [[vidiv]]'s in connection 340bca6cb3SZiyue Zhang */ 350bca6cb3SZiyue Zhang vidiv.io match { 360bca6cb3SZiyue Zhang case subIO => 370bca6cb3SZiyue Zhang subIO.div_in_valid := io.in.valid 380bca6cb3SZiyue Zhang subIO.div_out_ready := io.out.ready & io.out.valid 390bca6cb3SZiyue Zhang subIO.sew := vsew 400bca6cb3SZiyue Zhang subIO.sign := VidivType.isSigned(fuOpType) 410bca6cb3SZiyue Zhang subIO.dividend_v := vs2 420bca6cb3SZiyue Zhang subIO.divisor_v := vs1 430bca6cb3SZiyue Zhang subIO.flush := thisRobIdx.needFlush(io.flush) 440bca6cb3SZiyue Zhang } 450bca6cb3SZiyue Zhang 460bca6cb3SZiyue Zhang io.in.ready := vidiv.io.div_in_ready 470bca6cb3SZiyue Zhang io.out.valid := vidiv.io.div_out_valid 480bca6cb3SZiyue Zhang 490bca6cb3SZiyue Zhang private val outFuOpType = outCtrl.fuOpType 500bca6cb3SZiyue Zhang private val outIsDiv = VidivType.isDiv(outFuOpType) 510bca6cb3SZiyue Zhang private val resultData = Mux(outIsDiv, vidiv.io.div_out_q_v, vidiv.io.div_out_rem_v) 520bca6cb3SZiyue Zhang private val notModifyVd = outVl === 0.U 530bca6cb3SZiyue Zhang 540bca6cb3SZiyue Zhang mgu.io.in.vd := resultData 550bca6cb3SZiyue Zhang mgu.io.in.oldVd := outOldVd 560bca6cb3SZiyue Zhang mgu.io.in.mask := outSrcMask 570bca6cb3SZiyue Zhang mgu.io.in.info.ta := outVecCtrl.vta 580bca6cb3SZiyue Zhang mgu.io.in.info.ma := outVecCtrl.vma 590bca6cb3SZiyue Zhang mgu.io.in.info.vl := outVl 600bca6cb3SZiyue Zhang mgu.io.in.info.vlmul := outVecCtrl.vlmul 610bca6cb3SZiyue Zhang mgu.io.in.info.valid := io.out.valid 620bca6cb3SZiyue Zhang mgu.io.in.info.vstart := outVecCtrl.vstart 630bca6cb3SZiyue Zhang mgu.io.in.info.eew := outVecCtrl.vsew 640bca6cb3SZiyue Zhang mgu.io.in.info.vsew := outVecCtrl.vsew 650bca6cb3SZiyue Zhang mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 660bca6cb3SZiyue Zhang mgu.io.in.info.narrow := outVecCtrl.isNarrow 670bca6cb3SZiyue Zhang mgu.io.in.info.dstMask := outVecCtrl.isDstMask 680bca6cb3SZiyue Zhang mgu.io.in.isIndexedVls := false.B 690bca6cb3SZiyue Zhang io.out.bits.res.data := Mux(notModifyVd, outOldVd, mgu.io.out.vd) 700bca6cb3SZiyue Zhang io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 710bca6cb3SZiyue Zhang} 72