1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper, XSError} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 54 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 55 } 56 57 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 58 val sqIdx = new SqPtr 59 val lqIdx = new LqPtr 60 val numLsElem = NumLsElem() 61 } 62 63 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 64 val robIdx = new RobPtr 65 val resp = RespType() 66 val fuType = FuType() 67 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 68 val sqIdx = OptionWrapper(params.needFeedBackSqIdx, new SqPtr()) 69 } 70 71 object RespType { 72 def apply() = UInt(2.W) 73 74 def isBlocked(resp: UInt) = { 75 resp === block 76 } 77 78 def succeed(resp: UInt) = { 79 resp === success 80 } 81 82 val block = "b00".U 83 val uncertain = "b01".U 84 val success = "b11".U 85 } 86 87 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 88 val status = new Status() 89 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 90 val payload = new DynInst() 91 } 92 93 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 94 val flush = Flipped(ValidIO(new Redirect)) 95 val enq = Flipped(ValidIO(new EntryBundle)) 96 //wakeup 97 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 98 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 99 // vl 100 val vlIsZero = Input(Bool()) 101 val vlIsVlmax = Input(Bool()) 102 //cancel 103 val og0Cancel = Input(ExuOH(backendParams.numExu)) 104 val og1Cancel = Input(ExuOH(backendParams.numExu)) 105 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 106 //deq sel 107 val deqSel = Input(Bool()) 108 val deqPortIdxWrite = Input(UInt(1.W)) 109 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 110 //trans sel 111 val transSel = Input(Bool()) 112 // vector mem only 113 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 114 val sqDeqPtr = Input(new SqPtr) 115 val lqDeqPtr = Input(new LqPtr) 116 }) 117 } 118 119 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 120 //status 121 val valid = Output(Bool()) 122 val canIssue = Output(Bool()) 123 val fuType = Output(FuType()) 124 val robIdx = Output(new RobPtr) 125 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 126 //src 127 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 128 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 129 //deq 130 val isFirstIssue = Output(Bool()) 131 val entry = ValidIO(new EntryBundle) 132 val cancelBypass = Output(Bool()) 133 val deqPortIdxRead = Output(UInt(1.W)) 134 val issueTimerRead = Output(UInt(2.W)) 135 //trans 136 val enqReady = Output(Bool()) 137 val transEntry = ValidIO(new EntryBundle) 138 // debug 139 val entryInValid = Output(Bool()) 140 val entryOutDeqValid = Output(Bool()) 141 val entryOutTransValid = Output(Bool()) 142 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 143 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 144 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 145 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 146 } 147 148 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 149 val validRegNext = Bool() 150 val flushed = Bool() 151 val clear = Bool() 152 val canIssue = Bool() 153 val enqReady = Bool() 154 val deqSuccess = Bool() 155 val srcWakeup = Vec(params.numRegSrc, Bool()) 156 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 157 val vlWakeupByWb = Bool() 158 val srcCancelVec = Vec(params.numRegSrc, Bool()) 159 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 160 val srcLoadDependencyNext = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 161 } 162 163 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 164 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 165 common.flushed := status.robIdx.needFlush(commonIn.flush) 166 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 167 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 168 common.srcWakeupByWB := commonIn.wakeUpFromWB.map{ bundle => 169 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 170 if (params.numRegSrc == 5) { 171 bundle.bits.wakeUp(psrcSrcTypeVec.take(3), bundle.valid) :+ 172 bundle.bits.wakeUpV0(psrcSrcTypeVec(3), bundle.valid) :+ 173 bundle.bits.wakeUpVl(psrcSrcTypeVec(4), bundle.valid) 174 } 175 else 176 bundle.bits.wakeUp(psrcSrcTypeVec, bundle.valid) 177 }.transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 178 common.canIssue := validReg && status.canIssue 179 common.enqReady := !validReg || common.clear 180 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 181 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 182 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 183 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 184 srcCancel := srcLoadCancel || ldTransCancel 185 } 186 common.srcLoadDependencyNext.zip(status.srcStatus.map(_.srcLoadDependency)).foreach { case (ldsNext, lds) => 187 ldsNext.zip(lds).foreach{ case (ldNext, ld) => ldNext := ld << 1 } 188 } 189 if(isEnq) { 190 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 191 } else { 192 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 193 } 194 if (params.numRegSrc == 5) { 195 // only when numRegSrc == 5 need vl 196 common.vlWakeupByWb := common.srcWakeupByWB(4) 197 } else { 198 common.vlWakeupByWb := false.B 199 } 200 } 201 202 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 203 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 204 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 205 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 206 val srcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 207 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 208 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 209 val canIssueBypass = Bool() 210 } 211 212 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 213 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map{(bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 214 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 215 if (params.numRegSrc == 5) { 216 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 217 bundle.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 218 bundle.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 219 } 220 else 221 bundle.bits.wakeUpFromIQ(psrcSrcTypeVec) 222 }.toSeq.transpose 223 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 224 225 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 226 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 227 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 228 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 229 hasIQWakeupGet.srcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 230 case (exuOH, regExuOH) => 231 exuOH := 0.U.asTypeOf(exuOH) 232 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 233 } 234 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 235 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 236 wakeupVec.asUInt.orR | state 237 }).asUInt.andR 238 } 239 240 241 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 242 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 243 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 244 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 245 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 246 case ((dep, originalDep), deqPortIdx) => 247 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 248 dep := 1.U 249 else 250 dep := originalDep << 1 251 } 252 } 253 } 254 255 def wakeUpByVf(OH: Vec[Bool])(implicit p: Parameters): Bool = { 256 val allExuParams = p(XSCoreParamsKey).backendParams.allExuParams 257 OH.zip(allExuParams).map{case (oh,e) => 258 if (e.isVfExeUnit) oh else false.B 259 }.reduce(_ || _) 260 } 261 262 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 263 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 264 val cancelByLd = common.srcCancelVec.asUInt.orR 265 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 266 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 267 entryUpdate.status.robIdx := status.robIdx 268 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 269 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 270 val cancel = common.srcCancelVec(srcIdx) 271 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 272 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 273 val wakeup = common.srcWakeup(srcIdx) 274 275 val ignoreOldVd = Wire(Bool()) 276 val vlWakeUpByWb = common.vlWakeupByWb 277 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 278 val isWritePartVd = entryReg.payload.vpu.isWritePartVd 279 val vta = entryReg.payload.vpu.vta 280 val vma = entryReg.payload.vpu.vma 281 val vm = entryReg.payload.vpu.vm 282 val vlIsZero = commonIn.vlIsZero 283 val vlIsVlmax = commonIn.vlIsVlmax 284 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 285 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 286 val srcIsVec = SrcType.isVp(srcStatus.srcType) 287 if (params.numVfSrc > 0 && srcIdx == 2) { 288 /** 289 * the src store the old vd, update it when vl is write back 290 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 291 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 292 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 293 */ 294 ignoreOldVd := srcIsVec && vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 295 } else { 296 ignoreOldVd := false.B 297 } 298 299 srcStatusNext.psrc := srcStatus.psrc 300 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 301 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 302 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 303 // Vf / Mem -> Vf 304 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 305 MuxCase(srcStatus.dataSources.value, Seq( 306 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 307 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 308 srcStatus.dataSources.readBypass -> DataSource.bypass2, 309 srcStatus.dataSources.readBypass2 -> DataSource.reg, 310 )) 311 } 312 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 313 // Vf / Int -> Mem 314 MuxCase(srcStatus.dataSources.value, Seq( 315 wakeupByIQ -> DataSource.bypass, 316 (srcStatus.dataSources.readBypass && wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.bypass2, 317 (srcStatus.dataSources.readBypass && !wakeUpByVf(srcStatus.srcWakeUpL1ExuOH.get)) -> DataSource.reg, 318 srcStatus.dataSources.readBypass2 -> DataSource.reg, 319 )) 320 } 321 else { 322 MuxCase(srcStatus.dataSources.value, Seq( 323 wakeupByIQ -> DataSource.bypass, 324 srcStatus.dataSources.readBypass -> DataSource.reg, 325 )) 326 }) 327 if(params.hasIQWakeUp) { 328 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 329 srcStatusNext.srcLoadDependency := Mux(wakeupByIQ, 330 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 331 common.srcLoadDependencyNext(srcIdx)) 332 } else { 333 srcStatusNext.srcLoadDependency := common.srcLoadDependencyNext(srcIdx) 334 } 335 } 336 entryUpdate.status.blocked := false.B 337 entryUpdate.status.issued := MuxCase(status.issued, Seq( 338 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 339 commonIn.deqSel -> true.B, 340 !status.srcReady -> false.B, 341 )) 342 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 343 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, Mux(status.issueTimer === "b11".U, status.issueTimer, status.issueTimer + 1.U), "b11".U)) 344 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 345 entryUpdate.imm.foreach(_ := entryReg.imm.get) 346 entryUpdate.payload := entryReg.payload 347 if (params.isVecMemIQ) { 348 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 349 } 350 } 351 352 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 353 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 354 commonOut.valid := validReg 355 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 356 else common.canIssue && !common.flushed) 357 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 358 commonOut.robIdx := status.robIdx 359 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 360 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 361 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 362 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 363 dataSourceOut.value := (if (isComp) 364 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) { 365 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 366 (wakeupByIQWithoutCancel && !isWakeupByMemIQ) -> DataSource.forward, 367 (wakeupByIQWithoutCancel && isWakeupByMemIQ) -> DataSource.bypass, 368 )) 369 } else { 370 MuxCase(status.srcStatus(srcIdx).dataSources.value, Seq( 371 wakeupByIQWithoutCancel -> DataSource.forward, 372 )) 373 } 374 else 375 status.srcStatus(srcIdx).dataSources.value) 376 } 377 commonOut.isFirstIssue := !status.firstIssue 378 commonOut.entry.valid := validReg 379 commonOut.entry.bits := entryReg 380 if(isEnq) { 381 commonOut.entry.bits.status := status 382 } 383 commonOut.issueTimerRead := status.issueTimer 384 commonOut.deqPortIdxRead := status.deqPortIdx 385 386 if(params.hasIQWakeUp) { 387 commonOut.srcWakeUpL1ExuOH.get.zipWithIndex.foreach{ case (exuOHOut, srcIdx) => 388 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 389 if (isComp) 390 ExuOHGen(exuOHOut, wakeupByIQWithoutCancelOH, hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 391 else 392 ExuOHGen(exuOHOut, 0.U.asTypeOf(wakeupByIQWithoutCancelOH), hasIQWakeupGet.srcWakeupL1ExuOH(srcIdx)) 393 } 394 } 395 396 val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 397 val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) 398 if(params.hasIQWakeUp) { 399 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 400 val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) 401 srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => 402 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 403 wakeupSrcLoadDependency(srcIdx), 404 status.srcStatus(srcIdx).srcLoadDependency) 405 else status.srcStatus(srcIdx).srcLoadDependency) 406 } 407 srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => 408 ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, 409 wakeupSrcLoadDependencyNext(srcIdx), 410 common.srcLoadDependencyNext(srcIdx)) 411 else common.srcLoadDependencyNext(srcIdx)) 412 } 413 } else { 414 srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) 415 srcLoadDependencyOut := common.srcLoadDependencyNext 416 } 417 commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) 418 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => 419 ldOut := srcLoadDependencyOut(srcIdx) 420 } 421 422 commonOut.enqReady := common.enqReady 423 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 424 commonOut.transEntry.bits := entryUpdate 425 // debug 426 commonOut.entryInValid := commonIn.enq.valid 427 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 428 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 429 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 430 if (params.hasIQWakeUp) { 431 commonOut.perfLdCancel.get := common.srcCancelVec.map(_ && validReg) 432 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 433 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 434 } 435 // vecMem 436 if (params.isVecMemIQ) { 437 commonOut.uopIdx.get := entryReg.payload.uopIdx 438 } 439 } 440 441 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 442 val fromLsq = commonIn.fromLsq.get 443 val vecMemStatus = entryReg.status.vecMem.get 444 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 445 vecMemStatusUpdate := vecMemStatus 446 447 // update blocked 448 entryUpdate.status.blocked := false.B 449 } 450 451 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 452 val origExuOH = 0.U.asTypeOf(exuOH) 453 when(wakeupByIQOH.asUInt.orR) { 454 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 455 }.otherwise { 456 origExuOH := regSrcExuOH 457 } 458 exuOH := 0.U.asTypeOf(exuOH) 459 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 460 } 461 462 object IQFuType { 463 def num = FuType.num 464 465 def apply() = Vec(num, Bool()) 466 467 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 468 val res = 0.U.asTypeOf(fuType) 469 fus.foreach(x => res(x.id) := fuType(x.id)) 470 res 471 } 472 } 473 474 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 475 //wakeup 476 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 477 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 478 //cancel 479 val srcLoadDependency = Input(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 480 val og0Cancel = Input(ExuOH(backendParams.numExu)) 481 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 482 } 483 484 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 485 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 486 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 487 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 488 val srcCancelByLoad: Vec[Bool] = Vec(params.numRegSrc, Bool()) 489 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 490 } 491 492 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 493 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 494 wakeup := enqDelayIn.wakeUpFromWB.map{ x => 495 if (i == 3) 496 x.bits.wakeUpV0((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 497 else if (i == 4) 498 x.bits.wakeUpVl((status.srcStatus(i).psrc, status.srcStatus(i).srcType), x.valid) 499 else 500 x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 501 }.reduce(_ || _) 502 } 503 504 if (params.hasIQWakeUp) { 505 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map{ x => 506 val psrcSrcTypeVec = status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType) 507 if (params.numRegSrc == 5) { 508 x.bits.wakeUpFromIQ(psrcSrcTypeVec.take(3)) :+ 509 x.bits.wakeUpV0FromIQ(psrcSrcTypeVec(3)) :+ 510 x.bits.wakeUpVlFromIQ(psrcSrcTypeVec(4)) 511 } 512 else 513 x.bits.wakeUpFromIQ(psrcSrcTypeVec) 514 }.toIndexedSeq.transpose 515 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 516 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 517 } else { 518 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 519 } 520 521 if (params.hasIQWakeUp) { 522 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 523 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 524 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 525 } 526 enqDelayOut.srcCancelByLoad.zipWithIndex.foreach { case (ldCancel, i) => 527 ldCancel := LoadShouldCancel(Some(enqDelayIn.srcLoadDependency(i)), enqDelayIn.ldCancel) 528 } 529 } else { 530 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 531 enqDelayOut.srcCancelByLoad := 0.U.asTypeOf(enqDelayOut.srcCancelByLoad) 532 } 533 534 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 535 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 536 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 537 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 538 dp := 1.U << (delay - 1) 539 else 540 dp := ldp << delay 541 } 542 } 543 } 544} 545