1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15 16case class IssueBlockParams( 17 // top down 18 private val exuParams: Seq[ExeUnitParams], 19 val numEntries : Int, 20 numEnq : Int, 21 numDeqOutside : Int = 0, 22 numWakeupFromOthers : Int = 0, 23 XLEN : Int = 64, 24 VLEN : Int = 128, 25 vaddrBits : Int = 39, 26 // calculate in scheduler 27 var idxInSchBlk : Int = 0, 28)( 29 implicit 30 val schdType: SchedulerType, 31) { 32 var backendParam: BackendParams = null 33 34 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 35 36 val allExuParams = exuParams 37 38 def updateIdx(idx: Int): Unit = { 39 this.idxInSchBlk = idx 40 } 41 42 def inMemSchd: Boolean = schdType == MemScheduler() 43 44 def inIntSchd: Boolean = schdType == IntScheduler() 45 46 def inVfSchd: Boolean = schdType == VfScheduler() 47 48 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstaCnt > 0 || HyuCnt > 0) 49 50 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 51 52 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 53 54 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 55 56 def isVecMemAddrIQ: Boolean = inMemSchd && (VlduCnt > 0 || VstaCnt > 0) 57 58 def isVecLdAddrIQ: Boolean = inMemSchd && VlduCnt > 0 59 60 def isVecStAddrIQ: Boolean = inMemSchd && VstaCnt > 0 61 62 def isVecStDataIQ: Boolean = inMemSchd && VstdCnt > 0 63 64 def isVecMemIQ: Boolean = (isVecLdAddrIQ || isVecStAddrIQ || isVecStDataIQ) 65 66 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 67 68 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 69 70 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 71 72 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 73 74 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 75 76 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 77 78 def numSrc: Int = exuBlockParams.map(_.numSrc).max 79 80 def readIntRf: Boolean = numIntSrc > 0 81 82 def readFpRf: Boolean = numFpSrc > 0 83 84 def readVecRf: Boolean = numVecSrc > 0 85 86 def readVfRf: Boolean = numVfSrc > 0 87 88 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 89 90 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 91 92 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 93 94 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 95 96 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 97 98 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 99 100 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 101 102 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 103 104 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 105 106 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 107 108 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 109 110 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 111 112 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 113 114 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 115 116 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 117 118 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 119 120 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 121 122 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 123 124 def numDeq: Int = numDeqOutside + exuBlockParams.length 125 126 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 127 128 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 129 130 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 131 132 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 133 134 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 135 136 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 137 138 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 139 140 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 141 142 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 143 144 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 145 146 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 147 148 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 149 150 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 151 152 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 153 154 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 155 156 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 157 158 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 159 160 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 161 162 def LdExuCnt = LduCnt + HyuCnt 163 164 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 165 166 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 167 168 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 169 170 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 171 172 def VstaCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "vsta")).sum 173 174 def VstdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "vstd")).sum 175 176 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 177 178 /** 179 * Get the regfile type that this issue queue need to read 180 */ 181 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 182 183 /** 184 * Get the regfile type that this issue queue need to read 185 */ 186 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 187 188 /** 189 * Get the max width of psrc 190 */ 191 def rdPregIdxWidth = { 192 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 193 } 194 195 /** 196 * Get the max width of pdest 197 */ 198 def wbPregIdxWidth = { 199 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 200 } 201 202 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 203 204 /** Get exu source wake up 205 * @todo replace with 206 * exuBlockParams 207 * .flatMap(_.iqWakeUpSinkPairs) 208 * .map(_.source) 209 * .distinctBy(_.name) 210 * when xiangshan is updated to 2.13.11 211 */ 212 def wakeUpInExuSources: Seq[WakeUpSource] = { 213 SeqUtils.distinctBy( 214 exuBlockParams 215 .flatMap(_.iqWakeUpSinkPairs) 216 .map(_.source) 217 )(_.name) 218 } 219 220 def wakeUpOutExuSources: Seq[WakeUpSource] = { 221 SeqUtils.distinctBy( 222 exuBlockParams 223 .flatMap(_.iqWakeUpSourcePairs) 224 .map(_.source) 225 )(_.name) 226 } 227 228 def wakeUpToExuSinks = exuBlockParams 229 .flatMap(_.iqWakeUpSourcePairs) 230 .map(_.sink).distinct 231 232 def numWakeupToIQ: Int = wakeUpInExuSources.size 233 234 def numWakeupFromIQ: Int = wakeUpInExuSources.size 235 236 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 237 238 def numWakeupFromWB = { 239 val pregSet = this.pregReadSet 240 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 241 } 242 243 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 244 245 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) || x.hasLoadFu).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 246 247 def needWakeupFromVfWBPort = backendParam.allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 248 249 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 250 251 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 252 253 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 254 255 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 256 257 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 258 259 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 260 261 // set load imm to 32-bit for fused_lui_load 262 def deqImmTypesMaxLen: Int = if (isLdAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 263 264 def needImm: Boolean = deqImmTypes.nonEmpty 265 266 // cfgs(exuIdx)(set of exu's wb) 267 268 /** 269 * Get [[PregWB]] of this IssueBlock 270 * @return set of [[PregWB]] of [[ExeUnit]] 271 */ 272 def getWbCfgs: Seq[Set[PregWB]] = { 273 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 274 } 275 276 def canAccept(fuType: UInt): Bool = { 277 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 278 } 279 280 def bindBackendParam(param: BackendParams): Unit = { 281 backendParam = param 282 } 283 284 def wakeUpSourceExuIdx: Seq[Int] = { 285 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 286 } 287 288 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 289 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 290 } 291 292 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 293 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 294 } 295 296 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 297 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 298 } 299 300 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 301 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 302 } 303 304 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 305 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 306 } 307 308 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 309 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 310 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 311 case _ => Seq() 312 } 313 val vfBundle = schdType match { 314 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 315 case _ => Seq() 316 } 317 MixedVec(intBundle ++ vfBundle) 318 } 319 320 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 321 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyPdest, x.iqWakeUpSourcePairs.size / x.copyDistance)))) 322 } 323 324 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 325 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 326 } 327 328 def genOGRespBundle(implicit p: Parameters) = { 329 implicit val issueBlockParams = this 330 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 331 } 332 333 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 334 implicit val issueBlockParams = this 335 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 336 } 337 338 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 339 implicit val issueBlockParams = this 340 MixedVec(exuBlockParams.map{ x => 341 new WbFuBusyTableReadBundle(x) 342 }) 343 } 344 345 def genWbConflictBundle()(implicit p: Parameters) = { 346 implicit val issueBlockParams = this 347 MixedVec(exuBlockParams.map { x => 348 new WbConflictBundle(x) 349 }) 350 } 351 352 def getIQName = { 353 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 354 } 355} 356