1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 exuBlockParams : Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers: Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 def updateIdx(idx: Int): Unit = { 34 this.idxInSchBlk = idx 35 } 36 37 def inMemSchd: Boolean = schdType == MemScheduler() 38 39 def inIntSchd: Boolean = schdType == IntScheduler() 40 41 def inVfSchd: Boolean = schdType == VfScheduler() 42 43 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 44 45 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 46 47 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 48 49 def numExu: Int = exuBlockParams.length 50 51 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 52 53 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 54 55 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 56 57 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 58 59 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 60 61 def numSrc: Int = exuBlockParams.map(_.numSrc).max 62 63 def readIntRf: Boolean = numIntSrc > 0 64 65 def readFpRf: Boolean = numFpSrc > 0 66 67 def readVecRf: Boolean = numVecSrc > 0 68 69 def readVfRf: Boolean = numVfSrc > 0 70 71 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 72 73 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 74 75 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 76 77 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 78 79 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 80 81 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 82 83 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 84 85 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 86 87 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 88 89 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 90 91 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 92 93 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 94 95 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 96 97 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 98 99 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 100 101 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 102 103 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 104 105 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 106 107 def numDeq: Int = numDeqOutside + exuBlockParams.length 108 109 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 110 111 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 112 113 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 114 115 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 116 117 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 118 119 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 120 121 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 122 123 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 124 125 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 126 127 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 128 129 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 130 131 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 132 133 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 134 135 def LduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "ldu")).sum 136 137 def StaCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "sta")).sum 138 139 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 140 141 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 142 143 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 144 145 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 146 147 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 148 149 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 150 151 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 152 153 /** 154 * Get the regfile type that this issue queue need to read 155 */ 156 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 157 158 /** 159 * Get the regfile type that this issue queue need to read 160 */ 161 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 162 163 /** 164 * Get the max width of psrc 165 */ 166 def rdPregIdxWidth = { 167 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 168 } 169 170 /** 171 * Get the max width of pdest 172 */ 173 def wbPregIdxWidth = { 174 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 175 } 176 177 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 178 179 /** Get exu source wake up 180 * @todo replace with 181 * exuBlockParams 182 * .flatMap(_.iqWakeUpSinkPairs) 183 * .map(_.source) 184 * .distinctBy(_.name) 185 * when xiangshan is updated to 2.13.11 186 */ 187 def wakeUpInExuSources: Seq[WakeUpSource] = { 188 SeqUtils.distinctBy( 189 exuBlockParams 190 .flatMap(_.iqWakeUpSinkPairs) 191 .map(_.source) 192 )(_.name) 193 } 194 195 def wakeUpOutExuSources: Seq[WakeUpSource] = { 196 SeqUtils.distinctBy( 197 exuBlockParams 198 .flatMap(_.iqWakeUpSourcePairs) 199 .map(_.source) 200 )(_.name) 201 } 202 203 def wakeUpToExuSinks = exuBlockParams 204 .flatMap(_.iqWakeUpSourcePairs) 205 .map(_.sink).distinct 206 207 def numWakeupFromIQ: Int = wakeUpInExuSources.size 208 209 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 210 211 def numWakeupFromWB = { 212 val pregSet = this.pregReadSet 213 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 214 } 215 216 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 217 218 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 219 220 // cfgs(exuIdx)(set of exu's wb) 221 222 /** 223 * Get [[PregWB]] of this IssueBlock 224 * @return set of [[PregWB]] of [[ExeUnit]] 225 */ 226 def getWbCfgs: Seq[Set[PregWB]] = { 227 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 228 } 229 230 def canAccept(fuType: UInt): Bool = { 231 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 232 } 233 234 def bindBackendParam(param: BackendParams): Unit = { 235 backendParam = param 236 } 237 238 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 239 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 240 } 241 242 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 243 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuOutputBundle))) 244 } 245 246 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 247 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuOutputBundle))) 248 } 249 250 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 251 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuBypassBundle))) 252 } 253 254 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 255 MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 256 } 257 258 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 259 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 260 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 261 case _ => Seq() 262 } 263 val vfBundle = schdType match { 264 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 265 case _ => Seq() 266 } 267 MixedVec(intBundle ++ vfBundle) 268 } 269 270 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 271 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 272 } 273 274 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 275 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 276 } 277 278 def genOGRespBundle(implicit p: Parameters) = { 279 implicit val issueBlockParams = this 280 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 281 } 282 283 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 284 implicit val issueBlockParams = this 285 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 286 } 287 288 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 289 implicit val issueBlockParams = this 290 MixedVec(exuBlockParams.map{ x => 291 new WbFuBusyTableReadBundle(x) 292 }) 293 } 294 295 def genWbConflictBundle()(implicit p: Parameters) = { 296 implicit val issueBlockParams = this 297 MixedVec(exuBlockParams.map { x => 298 new WbConflictBundle(x) 299 }) 300 } 301 302 def getIQName = { 303 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 304 } 305} 306