xref: /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala (revision 60deaca22c5a1ded25c3f9c16f75f7cb68ab214c)
1b034d3b9SLinJiaweipackage xiangshan.backend.rename
2b034d3b9SLinJiawei
3b034d3b9SLinJiaweiimport chisel3._
4b034d3b9SLinJiaweiimport chisel3.util._
5b034d3b9SLinJiaweiimport xiangshan._
6b9fd1892SLinJiaweiimport utils.{ParallelOR, XSDebug}
7b034d3b9SLinJiawei
86624015fSLinJiaweiclass BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule {
9b034d3b9SLinJiawei  val io = IO(new Bundle() {
10b034d3b9SLinJiawei    val flush = Input(Bool())
11b034d3b9SLinJiawei    // set preg state to busy
12b034d3b9SLinJiawei    val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
1375bc8863Slinjiawei    // set preg state to ready (write back regfile + roq walk)
146624015fSLinJiawei    val wbPregs = Vec(numWritePorts, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
15*60deaca2SLinJiawei    // set preg state to busy when replay
16*60deaca2SLinJiawei    val replayPregs = Vec(ReplayWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
17b034d3b9SLinJiawei    // read preg state
186624015fSLinJiawei    val rfReadAddr = Vec(numReadPorts, Input(UInt(PhyRegIdxWidth.W)))
196624015fSLinJiawei    val pregRdy = Vec(numReadPorts, Output(Bool()))
20b034d3b9SLinJiawei  })
21b034d3b9SLinJiawei
22767bd21fSLinJiawei  val table = RegInit(0.U(NRPhyRegs.W))
23767bd21fSLinJiawei
24*60deaca2SLinJiawei  def reqVecToMask(rVec: Vec[Valid[UInt]]): UInt = {
25*60deaca2SLinJiawei    ParallelOR(rVec.map(v => Mux(v.valid, UIntToOH(v.bits), 0.U)))
26*60deaca2SLinJiawei  }
27*60deaca2SLinJiawei
28*60deaca2SLinJiawei  val wbMask = reqVecToMask(io.wbPregs)
29*60deaca2SLinJiawei  val allocMask = reqVecToMask(io.allocPregs)
30*60deaca2SLinJiawei  val replayMask = reqVecToMask(io.replayPregs)
31767bd21fSLinJiawei
3284a015b1Slinjiawei  val tableAfterWb = table & (~wbMask).asUInt
3384a015b1Slinjiawei  val tableAfterAlloc = tableAfterWb | allocMask
34*60deaca2SLinJiawei  val tableAfterReplay = tableAfterAlloc | replayMask
35b034d3b9SLinJiawei
36b034d3b9SLinJiawei  for((raddr, rdy) <- io.rfReadAddr.zip(io.pregRdy)){
3784a015b1Slinjiawei    rdy := !tableAfterWb(raddr)
38b034d3b9SLinJiawei  }
39b034d3b9SLinJiawei
40*60deaca2SLinJiawei  table := tableAfterReplay
41b034d3b9SLinJiawei
42767bd21fSLinJiawei//  for((alloc, i) <- io.allocPregs.zipWithIndex){
43767bd21fSLinJiawei//    when(alloc.valid){
44767bd21fSLinJiawei//      table(alloc.bits) := true.B
45767bd21fSLinJiawei//    }
46767bd21fSLinJiawei//    XSDebug(alloc.valid, "Allocate %d\n", alloc.bits)
47767bd21fSLinJiawei//  }
48767bd21fSLinJiawei
49767bd21fSLinJiawei
50767bd21fSLinJiawei//  for((wb, i) <- io.wbPregs.zipWithIndex){
51767bd21fSLinJiawei//    when(wb.valid){
52767bd21fSLinJiawei//      table(wb.bits) := false.B
53767bd21fSLinJiawei//    }
54767bd21fSLinJiawei//    XSDebug(wb.valid, "writeback %d\n", wb.bits)
55767bd21fSLinJiawei//  }
56b034d3b9SLinJiawei
57b034d3b9SLinJiawei  when(io.flush){
58767bd21fSLinJiawei    table := 0.U(NRPhyRegs.W)
59b034d3b9SLinJiawei  }
60a6ad6ca2SYinan Xu
61767bd21fSLinJiawei  XSDebug(p"table    : ${Binary(table)}\n")
6284a015b1Slinjiawei  XSDebug(p"tableNext: ${Binary(tableAfterAlloc)}\n")
63767bd21fSLinJiawei  XSDebug(p"allocMask: ${Binary(allocMask)}\n")
64767bd21fSLinJiawei  XSDebug(p"wbMask : ${Binary(wbMask)}\n")
65a6ad6ca2SYinan Xu  for (i <- 0 until NRPhyRegs) {
66a6ad6ca2SYinan Xu    XSDebug(table(i), "%d is busy\n", i.U)
67a6ad6ca2SYinan Xu  }
68b034d3b9SLinJiawei}
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